1:5)
`United States Patent
`4,951,259
`Aug, 21, 1990
`[45] Date of Patent:
`Sato et al.
`
`[11] Patent Number:
`
`[54] SEMICONDUCTOR MEMORYDEVICE
`WITH FIRST AND SECOND WORD LINE
`DRIVERS
`
`[75]
`
`Inventors: Yoichi Sato, Iruma; Satoshi
`Shinagawa, Ohme, both of Japan
`
`{73] Assignees: Hitachi, Ltd.; Hitachi VLSI
`Engineering Corp., both of Tokyo,
`Japan
`
`[21] Appl. No.: 156,742
`
`[22] Filed:
`
`Feb. 18, 1988
`
`Foreign Application Priority Data
`[30]
`Feb. 18, 1987 [JP]
`Japan ......scsssessssseerseerseeeeeees 62-33201
`
`Int. Cho eeeeeseeeseeenens G11C 7/60; G11C 8/00
`[ST]
`[52] U.S. C0. once cesceeenene 365/230.06; 365/189.03;
`365/204
`[58] Field of Search ............... 365/189, 206, 230, 204,
`365/230.06, 189.03; 307/463
`References Cited
`U.S. PATENT DOCUMENTS
`
`[56]
`
`4,620,299 10/1986 Remington .......cseceseeees 365/230
`4,685,088
`8/1987 Tanne ou...seecssseceesesesnees 365/230
`
`4,706,222 11/1987 Kwiatkowski etal.
`............ 365/230
`
`4,719,603
`1/1988 Shinagawa ......sessernenseeee 365/230
`
`4,763,304
`
`8/1988 Uesugt ....crercseserererees 365/230 X
`
`Primary Examiner—Stuart N. Hecker
`Assistant Examiner—Alyssa H. Bowler
`Attorney, Agent, or Firm—Antonelli, Terry, Stout &
`Kraus
`
`ABSTRACT
`57]
`A semiconductor memory device is provided which
`includes a plurality of word line drivers and logic de-
`coding circuitry coupled to the inputs of the word line
`drivers. In large memoryarrays, the word line driver
`circuits can place large capacitive loads on the outputof
`the logic decoding circuit because the wordline driver
`transistors must be relatively large. This large load on
`the logic decoding circuitry adversely effects the oper-
`ating speed of the memory. Accordingly, to reduce this
`load, a switching arrangement is provided between the
`outputof the logic decoding circuitry and the wordline
`drivers. This switching arrangement can be controlled
`to respectively connect the output of the logic decoding
`circuit to the word line drivers based on control output
`signals of a pre-decoder. Reset MOSFETscan also be
`provided to prevent the inputs of the wordline drivers
`from floating.
`
`19 Claims, 4 Drawing Sheets
`
`FROMXADB
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`US. Patent
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`Aug. 21, 1990
`
`Sheet 1 of 4
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`4,951,259
`
`FIG.
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`US. Patent—Aug. 21, 1990 Sheet 2 of 4 4,951,259
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`FIG. 2
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`US. Patent
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`Aug. 21, 1990
`
`Sheet3 of4
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`4,951,259
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`US. Patent—Aug. 21, 1990 Sheet4 of4 4,951,259
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`FROM XADB
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`

`1
`
`4,951,259
`
`SEMICONDUCTOR MEMORY DEVICE WITH
`FIRST AND SECOND WORD LINE DRIVERS
`
`BACKGROUND OF THE INVENTION
`
`3
`
`'
`
`2
`above, the drain capacitance as well as gate capacitance
`of these MOSFETs become great and loads on the
`pre-decoder PDCRand on the decoding NAND gate
`circuit increase, too. The influenceofthe increase of the
`loads becomesparticularly remarkable in the decoding
`NAND gatecircuit in which a plurality of MOSFETs
`This invention relates to semiconductor memory
`are connectedin series, and this is one of the factors that
`devices and to a technique which will be effective when
`prevent a higher operation speed of static RAMs.
`applied, for example, to CMOS (Complementary MOS)
`It is therefore an object of the present invention to
`static RAMs (Random Access Memories).
`provide a semiconductor memory device such as a
`CMOSstatic RAMsincluding clocked static decod-
`CMOSstatic RAM which speedsupthe selection oper-
`ers are knownin the art. A method of improving chip
`layoutefficiency has been proposed by disposing a pre-
`ation of the X address decoder and the operation speed
`decoder PDCR shown in FIG. 5 in an X address de-
`of memory access.
`coder XDRCof such a CMOSstatic RAM.
`The above and other objects and novelfeaturesofthe
`Japanese Pat. Laid-Open No. 74890/1981, for exam-
`present invention will become more apparent from the
`ple, describes the address decoder of suchastatic
`following description when. taken in conjunction with
`RAM.This publication is hereby incorporated byrefer-
`the accompanying drawings.
`ence.
`Amongtheinventionsdisclosedherein, the following
`In FIG. 5, the X address decoder XDCR of the
`will illustrate a typical example.
`CMOSstatic RAM includes one pre-decoder PDCR
`A capacitance cut MOSFETis provided for receiv-
`and a plurality of NAND gates for decoding repre-
`ing a corresponding outputsignal of a pre-decoder, for
`sented by a NANDgate circuit NAG 0. Here,the pre-
`example, at its gate. This capacitance(cut MOSFETis
`decoder PDCR receives lower 2-bit complementary
`disposed between a decoding logic gate circuit of an X
`‘internal address signals ax0 and ax1 (where an internal
`address decoder and each wordline drive circuit. It
`address signal such as ax0 having the same phase as an
`should be noted that the term “‘capacitance cut MOS-
`external address signal AX0, and an internal address
`FET” means a MOSFETprovidedto reduce the capac-
`signal such as ax0 having an opposite phase to the phase
`itive load of a circuit which it is coupled to the output
`of the external address signal AXO are together ex-
`of(e.g., in this case, for cutting the capacitive load of
`pressed as complementary internal address signal ax0),
`the decoding logic gate and the pre-decoder). In addi-
`for example, and generates selection signals 6x0 ~ x3.
`tion, a reset MOSFETis provided which is connected
`As represented typically by the NAND gatecircuit
`at its source, for example, to the power source voltage
`NAG0in FIG. 5, each NANDgatecircuit consists of
`of the circuit and receives at its gate a selection control
`a plurality of N-channel MOSFETs Q,2 ~Qg3 which are
`signal. This reset MOSFET is disposed at the input
`connected in series to receive complementary internal
`terminal of each wordline drive circuit.
`address signals ax2~axi combined with one anotherin
`According to the means described above, since the
`such a manner as to correspond to the gates of these
`capacitance cut MOSFETis disposed in such a manner
`transistors, and a P-channel MOSFET Qgi and an N-
`channel MOSFET Qoyadisposed between these MOS-
`as to correspond to each wordline drivecircuit, driva-
`FETs Qg2, Qe3 and a power source voltage Vcc and
`bility of the word line drive circuit can be increased
`ground potential of the circuit, respectively.
`without increasing loads on the output signals of the
`As represented by word lines W0~ W3, each word
`pre-decoderand on the decodinglogic gate circuit, that
`line of a memory array M-ARYis connected to.a word
`is, without exerting any undesirable influences on the
`line drive circuit corresponding thereto. These word
`selection operation of the X address decoder. Accord-
`line drive circuits each consist of a P-channel MOSFET
`ingly, it becomes possible to increase the memory ca-
`Qai and an N-channel MOSFET Qz,2 connected in a
`pacity of a semiconductor memory device such as a
`CMOSinverter circuit arrangement. Four word line
`CMOSstatic RAM and to attain its higher operation
`drive circuits are connected to each decoding NAND
`speed.
`gate circuit of the X address decoder XDCR. Each
`BRIEF DESCRIPTION OF THE DRAWINGS
`wordline drive circuit has the function of a part of the
`X address decoder XDCR when the corresponding
`FIG: 1 is a circuit diagram showing an X address
`selection signal }x0~x3 is supplied from the pre-
`decoder of a static RAM in accordance with thefirst
`decoder PDCR described above to the source of the
`embodimentof the present invention;
`P-channel MOSFET Qa.constituting that word line
`FIG. 2 is a circuit diagram showing the X address
`drive circuit.
`decoderof the static RAM in accordance with the sec-
`ond embodimentof the present invention;
`FIG. 3 a circuit diagram showing the X address de-
`coder of the static RAM in accordance with the third
`embodimentof the present invention;
`FIG.4 is a block circuit diagram showing one em-
`bodiment of the static RAM in accordance with the
`present invention, and
`FIG. 5 is a circuit diagram showing an example of an
`X address decoder of a conventional static RAM.
`
`45
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`SUMMARY OF THE INVENTION
`
`However, the inventors of the present invention have
`clarified as a result of their studies that the following
`problem develops in the static X address decoderof the
`kind described above when the memory capacity of
`CMOSstatic RAMSis increased. The parasitic capaci-
`tance connected to each word line increases with the
`increase in the memory capacity of the CMOSstatic
`RAM,andtherise of the voltage level of the word line
`which is brought into the selection state is delayed. If 65
`the sizes of MOSFETs Qui and Qu are increased to
`increase the driving capacity of the word line drive
`circuit in order to cope with the problem described
`
`60
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`Embodiment 1
`
`6
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`

`

`3
`FIG. 4 shows a block circuit diagram of a CMOS
`static RAM in accordance with the first embodiment of
`the present invention. Each circuit element of the draw-
`ing is formed on one semiconductor substrate such as
`single crystal silicon by known fabrication technique of
`CMOSintegrated circuits, though not particularly limi-
`tative. In the drawings to follow, MOSFETsrepre-
`sented by an arrow at their channel (back gate) are of a
`P-channel type while MOSFETsnot having the arrow
`are of an N-channel type.
`In FIG. 4, a memory array M-ARYconsists of m+1
`wordlines WO~ Wm, n+1 complementary data lines
`D0-D0~Dn-Dn and (m+1)x(n+1) memory cells dis-
`posed at the points of intersection of these word lines
`and complementary data lines.
`Thoughnotparticularly limitative, each memorycell
`consists fundamentally of two sets of CMOSinverter
`circuits consisting in turn of a P-channel MOSFET Q21
`and an N-channel MOSFETQ1and a P-channel MOS-
`FET Q22 and an N-channel MOSFET Q2. The input
`and output terminals of these CMOSinverter circuits
`are cross-connected with each other in the latch form
`and constitute a flip-flop as a memory device of this
`CMOSstatic RAM.
`The drains of MOSFETs Q21 and Q1 and the drains
`of MOSFETs Q22 and Q2that are connected in com-
`monare used as the input and output nodes ofthis flip-
`flop and further connectedto the corresponding com-
`plementary data lines DO-DO through N-channel trans-
`fer gate MOSFETs Q3and Q4,respectively. The gates
`of these transfer gate MOSFETs Q3 and Q4are con-
`nected in common to the corresponding word line WO.
`The other memory cells MC have the same circuit
`construction as described above and are connected
`likewise to the corresponding data and word lines,
`thereby forming a memorycell matrix and a memory
`array M-ARY.In other words, the input/output nodes
`of the memory cells MC disposed on the same row are
`connected_to the corresponding complementary data
`lines DO-D0~ Dn-Dn through the corresponding trans-
`fer gate MOSFETs,andthegates of transfer gate MOS-
`FETsof the memory cells MC disposed on the same
`column are connected in commonto the corresponding
`word lines WO~ Wm,respectively.
`As showntypically in FIG. 4, N-channel type load
`MOSFETpairs Q5-Q6~Q7-Q8 aredisposed between
`the complementary data lines D0-D0~Dn-Dn and the
`powersource voltage Vcc ofthe circuit.
`The word lines W0~ Wm are connected to the X
`address decoder XDCR. Complementary internal ad-
`dress signals ax0 ~axi (an internal address signal such as
`ax0 having the same phase as an externaladdresssignal
`AX0, and an internal address signal ax0 having the
`opposite phase to the phase of an external addresssignal
`AX0will be hereinafter expressed together as the com-
`plementary internal address signal ax0) from an X ad-
`dress buffer ADB are supplied to this X address de-
`coder XDCR.A timing signal $ce(a selection control
`signal) is supplied, too, from a later-discussed timing
`control circuit TC to the X address decoder XDCR.
`This timing signal dce is generated in accordance with
`achip enable signal CE supplied as a controlsignal from
`outside and is kept at a high level under the selection
`state of this CMOSstatic RAM. Aswill be described
`later, the X address.decoder XDCRis selectively actu-
`ated by the timing control signal @ce, decodes the com-
`plementary internal address signals ax0@~axi and sets
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`one of the word lines designated by the X address sig-
`nals AX0~ AXito the high level selection state.
`Thedefinite circuit construction and operation ofthe
`X address decoder will be described later in further
`detail.
`The X address buffer XADB receives the X address
`signals AXO~ AXi supplied through external terminals
`AX0~AXi and generates the complementary internal
`address signals ax0~.axi on the basis of these signals
`AX0~Axi and supplies them to the X address decoder
`XDCR.
`the complementary data lines
`On the other hand,
`D0-D0~Dn-Dn of the memory array M-ARYare con-
`nected selectively to the complementary common data
`lines CD-CD through the corresponding switch MOS-
`FET pairs Q9-Q10~Q11-Q12 of the column switch
`SW,respectively. The gates of these switch MOSFET
`pairs Q9-Q10~Q11-Q12 are connected in common and
`the corresponding data line selection signals YO~ Yn
`are supplied thereto from the Y address decoder
`YDCR.
`Y address decoder YDCRgenerates data line selec-
`tion signals Y0~ Yn forselecting one set of complemen-
`tary data lines and for connectingthem to the comple-
`mentary commondata lines CD-CD by decoding the
`complementary internal address signals ay0~ayj sup-
`plied from the Y address buffer YADB. This Y address
`decoder YDCRis operated selectively in accordance
`with the timing signal oce supplied from the timing
`control circuit TC in the same way as the X address
`decoder XDCR.
`__
`The complementary common data lines CD-CD are
`connectedto the input terminals of a sense amplifier SA
`and to the output terminals of a write amplifier WA.
`The output terminals of the sense amplifier SA are con-
`nected to the input terminals of a data output buffer
`DOB while the input terminals of the write amplifier
`WAare connected to the output terminals of a data
`input buffer DIB.
`The sense amplifier SA is operated selectively in
`accordance with the timing signal $sa supplied from the
`timing control circuit TC and amplifies the read signal
`outputted from the selected memory cell MC through
`the complementary common data lines CD-CD. The
`outputsignal of the sense amplifier SA is supplied to the
`data output buffer DOB.
`Thedata output buffer DOBis operated selectively in
`accordance with the timing signal poe supplied from
`the timing control circuit TC in the read mode of
`CMOSstatic RAM. The data output buffer DOB fur-
`ther amplifies the read signal of the memorycell output-
`ted from the sense amplifier SA and deliversit to exter-
`nal devices through the input/output terminals DIO.
`The output of the data output buffer DOBis in a high
`impedancestate under the non-selection state of CMOS
`static RAM in which the timing signal doeis at the low
`level and in the write mode.
`On the other hand,
`the data input buffer DOB
`supplies write data supplied from an external device
`through the input/output terminals DIO to a write
`amplifier WA as a complementary write signal in the
`write mode of CMOSstatic RAM.
`In the write mode of CMOSstatic RAM,the write
`amplifier is operated selectively in accordance with the
`timing signal @we supplied from the timing control
`circuit TC. The write amplifier WA supplies a write
`current, which relies on the complementary write sig-
`nals supplied from the data input buffer DIB, to the
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`5
`selected memory cell MCthrough the complementary
`common data lines CD-CD. The output of the write
`amplifier WA is ina high impedance state under the
`non-selection state of CMOS static RAM where the
`timing signal dwe is at the low level, and in its read
`mode.
`The timing control circuit TC generates various tim-
`ing signals described above on the basis of a chip enable
`signal CE, a write enable signal WE and an output
`enable signal OE supplied as controlsignals from out-
`side, and supplies each timing signal to each circuit in
`the manner described above.
`FIG.1 showsa circuit diagram of one example of the
`X address decoder XDCR of the CMOSstatic RAM
`shown in FIG.4.
`In FIG. 1, the X address decoder XDCR of the
`CMOSstatic RAM includes the pre-decoder PDCR
`which receives the lower 2-bit complementary internal
`address signals ax0 and axl and k+1 decoding NAND
`gate circuits NAGO~ NAGkto which the complemen-
`tary internal address signals ax2~axi other than the
`lower twobits in respective combinations are supplied,
`thoughthe circuit configuration is not particularly limi-
`tative.
`The pre-decoder PDCR decodes the lower 2-bit
`complementary internal address signals ax0 and axl
`supplied thereto from the X address bufferXADB and
`generates selection signals px0~x3. These selection
`signals @x0~ x3 are formedselectively in accordance
`with the complementary internal address signals ax0
`and ax1. In other words,the selection signal 0is set to
`the high logic level when both the inversed internal
`address signals ax0 and ax] are at the high logic level.
`Similarly, the selection signals 6x1, 6x2 and $x3areset
`to the high logic level when both the non-inversed
`internal address signal ax0 and. the inversed internal
`addresssignal axi are at the high logic level, when both
`the inversed internal address signal
`ax@ and non-
`inversed internal address signal ax1are at the high logic
`level and when both the non-inversed internal address
`signals ax@ and ax1 are at the high logic level, respec-
`tively.
`Onthe other hand, each of the decoding NAND gate
`circuits NAGO~ NAGKconsists of a P-channel MOS-
`FET Qgl, N-channel MOSFETs Qg2, Qg3 and N-
`channel MOSFET Qgeé4disposed in series between the
`powersource voltage Vccofthe circuit and the ground
`potential. The gates of MOSFETs Qgi and Qgé4 are
`connected in commonandthe timing signal ce (selec-
`tion control signal) described aboveis supplied to them.
`The complementary internal addresssignals ax2~axi in
`the corresponding combinationsare applied to the gates
`of MOSFETs Q2g~ Qg3.In other words, the inversed
`internal address signals ax2~ax1 are all applied to the
`gates of MOSFETs Qg2~Qg3 of the NANDgate cir-
`cuit NAG 0 and the non-inversed internal address sig-
`nals ax2~axi are all supplied to the gates of MOSFETs
`Qg2~Qg3 of the NAND gate circuit NAG k. Simi-
`larly, the complementary internal address signals ax2-
`~axi which are combined in such a manneras to be the
`binary number corresponding to the number of the
`respective NAND gate circuit using the complemen-
`tary internal address signal ax2 as the lowermostbit are
`supplied to the gates of MOSFETs Qg2~Qg3 of the
`NANDgate circuits NAG1~ NAGKk-1.
`Accordingly, the output signal of the NAND_gate
`circuit NAGO,thatis, the inversed selection signal SO,is
`ordinarily at the high logic level under the non-selec-
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`tion state of CMOSstatic RAM,andis set to the low
`logic level in synchronism with the timing signal ¢ce
`when all the inversed internal address signals ax2~ axi
`are at the high logic level. In other words, the inversed
`selection signal $0 is at the low logic level when the
`CMOSstatic RAM is undertheselection state and any
`one of the word lines WO through W3is designated by
`the X address signal AX0-AXi. Similarly, the output
`signal of the NAND gate circuit NAGk, that is, the
`inversed selection signal Sk, is at the low logic level in
`synchronism with the timing signal @ce when all the
`non-inversed internal address signals ax2 ~ axi are at the
`highlogic level. In other words, the inversed selection
`signals Sk is at the low logic level when CMOSstatic
`RAMis under the selection state and any one of the
`word lines Wm-3~ Wm is designated by the X address
`signal AXO0~AXi. The output signals of the NAND
`gate circuits NAGI1~NAGk-1,
`that is,
`the inversed
`selection signals $1~Sk-1, which are not shownin the
`drawing, are generated by the same logic as described
`above.
`(m-+1) word line drive circuits WD0~WDm are
`disposed in the X address decoder XDCR of this
`CMOSstatic RAM in such a manneras to correspond
`to the word lines W0~Wm of the memory array
`M-ARY. As represented typically by. the word line
`drive circuits WD0, WD3, WDm-3 and WDm shownin
`FIG. 1, these word line drive circuits WD0~WDm
`each comprise a CMOSinverter circuit which consists
`of a P-channel MOSFET Qd1 and an N-channel MOS-
`FET Qd2. In order to provide a CMOSstatic RAM
`with a relatively large memory capacity, a relatively
`large memory capacitance consisting primarily of the
`gate capacitance of the transfer gate MOSFET ofthe
`memorycell is connected to each word line WO~ Wm
`of the memory array M-ARY.For this reason, MOS-
`FETs Qdl and Qd2 havea relatively large conductance
`and each wordline drive circuit WDO~Wdm is de-
`signed to have relatively large drivability.
`The selection signals S0~Sk generated by the
`NANDgate circuits NAG@~NAGkare supplied to
`the corresponding four sets of wordline drive circuits
`WD0~WD3 or WDm-3~WDmthrough the corre-
`sponding capacitance cut MOSFETs Q13~Q14 or
`Q15~Q16, respectively. Among the four capacitance
`cut MOSFETsofeach set, the selection signal x0 is
`supplied in commonfrom the pre-decoder PDCRto the
`gate of the first MOSFET represented by MOSFETs
`Q13 and Q15, and the selection signal x3 is supplied in
`common to the gate of the fourth MOSFET repre-
`sented by MOSFETsQ14 and Q16. Similarly, the selec-
`tion signals }xl and x2 are supplied in common from
`the pre-decoder PDCR to the gates of the second and
`third MOSFETs amongthe four capacitance cut MOS-
`FETs of each set, respectively. Accordingly, the in-
`versed selection signal S0~Skofthe low logic levelis
`transmitted to only the word line drive circuit corre-
`sponding to one wordline that is designated by the X
`address signal Ax0~ Axi.
`These capacitance cut MOSFETs Q13~Q16 are
`disposed between the output terminals of the decoding
`NAND gate circuits NAGO~NAGk and the input
`terminals of the word line drive circuits WD0~WDm;
`hence the level of the input terminal of each word line
`drive circuit under the non-selectionstate is in the float-
`ing state. To prevent this, a P-channel reset MOSFET
`Q23 ~ Q24 or Q25~Q26 is disposed between the input
`terminal of each wordline drive circuit and the power
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`4,951,259
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`roy 5
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`7
`drawing, the construction and operation of the same
`source voltage Vccofthe circuit. The timing signal oce
`circuit portions as those ofthe first embodiment will not
`described above is supplied in commonto the gates of
`these
`reset MOSFETs. These
`reset MOSFETs
`be explained.
`the X address decoder XDCR of the
`In FIG. 2,
`Q23~Q24 or Q25~ Q26 are turned ON together under
`CMOSstatic RAM of this embodiment includes one
`the non-selection state of the CMOSstatic RAM where
`pre-decoder PDCR and k+1 decoding NAND gate
`the timing signal dce is at the low logic level, and set
`circuits NAGO~NAGKin the same wayas in the first
`the level of the input terminals of the corresponding
`embodiment described already. The word line drive
`wordline drive circuits WD0~WDmto the high logic
`circuits WD0~ WDmaredisposed in such a manner as
`level. Accordingly, the output terminal of each word
`to correspond to the word lines W0~ Wm of the mem-
`line drive circuit, that is, the level of the word line
`ory array M-ARY.
`WO~ Wn,is fixed at the low level non-selectionstate.
`In the X address decoder XDCRofthis embodiment,
`When the CMOSstatic RAM is brought into the selec-
`N-channel capacitance cut MOSFETs Q17~Q18 for
`tion state and the timing signal ce rises to the high
`receiving the corresponding selection signals ox0~ 6x3
`logic
`level,
`the reset MOSFETs Q23~Q24 or
`at their gates from the pre-decoder PDCRare disposed
`Q25~Q26 are turned OFF. Atthis time, the inversed
`between the decoding NANDgate circuit NAGO and
`selection signal of the low logic level is supplied to the
`the corresponding four sets of word line drive circuits
`wordline drive circuit corresponding to the wordline
`WD0~Wd3. These selection signals @x0~x3 are
`whichis designated by the X address signal AX0~ AXi.
`generated in accordance with the same logic condition
`Therefore, the output terminal of this word line drive
`as that ofthe first embodiment.
`circuit, that is, the designated word line, is under the
`P-channel reset MOSFETs Q27 ~ Q28 are juxtaposed
`high level selection state. On the other hand, the input
`terminals of the wordline drive circuits which are not
`with the capacitance cut MOSFETs Q17 ~ Q18,respec-
`tively. The gates of these reset MOSFETs -Q27 ~ Q28
`underthe selection state are in the floating state because
`are connected in common and receive the afore-men-
`both the corresponding reset MOSFET and capaci-
`tioned timing signal ce from the timing control circuit
`tance cut MOSFETare OFF. However,since the time
`TC.
`in which CMOSstatic RAM is underthe selection state
`The pre-decoder PDCR,the decoding NAND gate
`is short, the corresponding word line keeps the non-
`NAGO, the word line drive circuits WD0~WD3 and
`selection state due to the high level charge built up in
`the capacitance cut MOSFETs Q17~Q18 perform the
`the gate capacitance of MOSFETs Qd1 and Qd2 of
`each wordline drive circuit.
`sameselection operation as that of the first embodiment
`and bring one wordline designated by the X address
`As described above,
`in the X address decoder of
`signal AXO~ Axi to the high level selection state.
`CMOSstatic RAM ofthis embodiment, capacitance cut
`The reset MOSFETs Q27~Q28 are turned ONto-
`MOSFETsfor receiving the selection signals 60~ x3 ©
`gether when the CMOSstatic RAM is under the non-
`of the pre-decoder PDCR are disposed between the
`selection state and the timing signal ce is at the low
`decoding NAND gate circuits and the four sets of word
`logic level. In this instance, the input terminal of each
`line drive circuits corresponding thereto. Moreover,
`wordline drive circuit WD0~ WD3is connected to the
`reset MOSFETsfor receiving the timing signal ce
`output terminal of the corresponding NANDgatecir-
`(selection control signal) are disposed between the input
`cuit NAGO through the corresponding reset MOSFET
`terminal of each word line drive circuit and the power
`Q27 ~ Q28. As described already, P-channel MOSFET
`source voltage Vcc ofthe circuit. Accordingly, the load
`Qgi for receiving the timing signal dce at its gate is
`to the output signal of the pre-decoder PDCR,thatis,
`disposed between the output terminal of the NAND
`the load to the selection signal 6x0~ x3, is only the
`gate circuit NAGO and the powersource voltage of the
`capacitance cut MOSFET havingarelatively small
`circuit. This MOSFETQg1is turned ON together with
`conductance, while the load to the outputsignal of each
`reset MOSFETs Q27~Q28 when the CMOSstatic
`decoding NANDgate circuit,that is, the load to the
`RAM is under the non-selection state and the timing
`inversed selection signal SO~Sk, is only one wordline
`signal ce is at the low logic level. Therefore, the input
`drive circuit connected through a corresponding capac-
`terminal of each word line drive circuit is fixed to the
`itance cut MOSFET.In other words, the loads to the
`high logic level by the power source voltage Vccof the
`output signals of the predecoder PDCR and decoding
`circuit which is supplied through this MOSFET Qg1
`NANDgate circuit are not muchaffected, even though
`and the corresponding reset MOSFET.Since the input
`a relatively large parasitic capacitance is connected to
`terminal of each wordline drive circuit is at the high
`each word line of the memory array M-ARYand the
`logic level,
`its output signal,
`that is,
`the word line
`side of MOSFETs Qd1 and Qd2 constituting the word
`W0~ Wn,is fixed to the low level non-selection state.
`line drive circuit is relatively large due to the large
`On the other hand, when this CMOSstatic RAM is
`memory capacity of CMOSstatic RAM.Therefore, the
`underthe selection state and the timing signal dceis at
`selection operation of the X address decoder XDCRis
`the high logic level, all the reset MOSFETs Q27 ~ Q28
`sped up and memory access of the CMOSstatic RAM
`are turned OFF, so that the corresponding selection
`is sped up, too.
`Embodiment 2
`signal 6x0 ~ x3 of the pre-decoder PDCRrises to the
`high logic level and the inversed selection signal the
`FIG. 2 shows the circuit diagram of the X address
`decoder XDCR of a CMOSstatic RAM in accordance
`corresponding NAND circuit is transmitted to only the
`word line drive circuit whose corresponding capaci-
`with the second embodiment of the present invention.
`tance cut MOSFET is turned ON. When the corre-
`The drawingillustrates partially the NAND gate circuit
`spondingselection signal @x0~ x3 of the pre-decoder
`NAGO, the word line drive circuits WD0~Wd3 and
`associated circuits of the X address decoder XDCR.
`PDCRis at the low logic level, reset MOSFETs and
`capacitance cut MOSFETs are turned OFF simulta-
`Therefore, refer to the circuits described in the first
`embodimentfor the detail of the circuits which are not
`neously and the level of the input terminal of the corre-
`sponding wordline drive circuit is in the floatingstate.
`shown. Furthermore, among the circuits shown in the
`
`40
`
`60
`
`65
`
`9
`
`

`

`5
`
`= 5
`
`25
`
`30
`
`4,951,259
`10
`9
`Q29~ Q30 are connected in commonto the gates of the
`However, in the same wayas in the first embodiment,
`since the time in which the CMOSstatic RAM is under
`corresponding capacitance cut MOSFET Q19~Q20,
`and the corresponding selection signals 6x0 ~ x3 are
`the selection state is short, the corresponding wordline
`supplied to them, respectively.
`keeps the low level non-selection state due to the high
`Reset MOSFETs Q29~ Q30 are turned ON when the
`level charge whichis built up in the gate capacitance of
`corresponding selection signals @xo~ x3 of the pre-
`MOSFETs Qd1and Qdz2of each word line drivecir-
`cuit.
`decoder PDCRare atthe low logic level and the corre-
`sponding wordline drive circuits are under the non-
`Asdescribed above, capacitance cut MOSFETsfor
`selection state, and set the input terminals of the word
`receiving the selection signals 6x0~x3 of the pre-
`line drive circuits to the high logic level. When the
`decoder PDCR are disposed between the decoding
`corresponding selection signals #x0~x3 of the pre-
`NAND gatecircuits and the corresponding four sets of
`word line drive circuits in the X address decoder
`decoder PDCRare at the high logic level, these reset
`XDCR of CMOSstatic RAM of this embodiment.
`MOSFETsare turned OFF but since corresponding
`capacitance cut MOSFETsare turned ON complemen-
`Reset MOSFETsfor receiving the timing signal dce
`tarily, the level of the input terminals of the correspond-
`(selection control signal) at their gates are disposed for
`ing word line drive circuits is determined by the level of
`these capacitance cut MOSFETs, respectively. Ac-
`the outputsignals of the corresponding wordline drive
`cordingly, in the same way as in the first embodiment,
`circuits. In other words, in the case of this embodiment,
`the load to the output signal of the pre-decoder PDCR,
`since each reset MOSFETand corresponding capaci-
`thatis, the load to the selection signal x0 ~ x3,is only
`tance cut MOSFET are turned ON complementarily,
`the capacitance cut MOSFEThavingarelatively small
`the level of the input terminal of each word line drive
`conductance and the load to the output signal of each
`circuit does not enter the floating state. For this reason,
`decoding NAND gatecircuit,that is, the load to the
`the output signal of each wordlinedrive circuit, thatis,
`inversed selection signal S0~ Sk, is only one wordline
`the level of the word lines WO~ Wm of the memory
`drive circuit connected through the capacitance cut
`array M-ARY,becomestabilized.
`MOSFET.Therefore, even though the CMOSstatic
`As described above, capacitance cut MOSFETsfor
`RAM has a large memorycapacity, the selection opera-
`receiving the selection signals @x0~x3 of the pre-
`tion of the X address decoder XDCRis sped up and the
`decoder PDCR are disposed between the decoding
`memory access of CMOSstatic RAM is sped up, as
`well.
`NAND gate circuit and the corresponding foursets of
`Embodiment3
`wordline drive circuits in the X address decoder of the
`CMOSstatic RAM of this embodiment, respectively. .
`FIG. 3 showsthe circuit diagram of the X address
`Reset MOSFETS whose gates are connected in com-
`decoder XCDR of the CMOSstatic RAM in accor-
`mon to the gates of the corresponding capacitance cut
`dance with the third embodiment of the present inven-
`MOSFETsare disposed between the input terminal of
`tion. The drawing shows only the NAND gate circuit
`each wordline drive circuit and the power source volt-
`NAGO, the word line drive circuits WD0O and associ-
`ated circuits of the X address deco