BOSTON SPH L523 750
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`IEEE JUURNHL UF SOLID STRTE CIRCUITS.
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`IEEE JOURNAL OF SOLID-STATE CIRCUITS
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`ii
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`

`

`IEEE JOURNAL OF
`
`SOLID-STATE
`
`CIRCUITS
`
`A PUBLICATION OF THE IEEE SOLID-STATE CIRCUITS SOCIETY
`
`
`
`DECEMBER 2003
`
`VOLUME 43
`
`NUMBER 12
`
`IJSCBC
`
`(ISSN 0013-9200)
`
`SPECIAL ISSUE ON THE 2008 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC)
`
`..
`
`M I
`
`ntroduction to the Special Issue on the 2008 IEEE International Solid-State Circuits Conference ........................................
`
`.................................................................................. S. Tsttkumoto. S.-I Lin. 5'. Heine», R. Thewes. and]. Lee 2587'm
`DATA CONVERTER PAPERS
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`A 108 dB SNR' 1'] mW Oversampling Au‘jio DAC With A Three-level DEM Technique ................................................
`............................................................... K. Nguyen. A. Buit(iropadhvuy, B. Adams; K. Sn'eerland, and P. Bugiuski
`A NoiseuCoupled Time-Interleaved Delta-Sigma ADC With 4.2 M Hz Bandwidth. —98 dB TH D. and 79 dB SNDR ...................
`.................................................. K. Lee. J. Cline. M. Anim. K. Hunmsht'rrt. K. Tnkasuka. S. Tltkettcht'. and G. C. Tamar
`A 14-?) IOU-MS/s Pipelined ADC With it Merged SHA and First MDAC
`B.-G. Lee, B.-M. Min. G. Mangtmam, and J. W. Vat'trmm
`All Over-60 dB True Rail—to-Rail Perfonnance Using Correlated Level Shifting and an Opatnp With Only 30 dB Loop Gain ..........
`................................................................................................................. B. R. Gregoire and U. Moon
`A I50 MS/s 133 th 7 bit ADC in 90 nm Digital CMOS ..................................................... G. Plus and B. Verbmggen
`Highly Interleaved 5-bit. ESO-MSample/s. LZ-mW ADC With Redundant Channels in 65-nrn CMOS ...................................
`
`
`B. P. Ginsburg and A. F! Churtdrrtkttran.............................................................................................. 264]W...“
`RF PAPERS
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`2592
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`260]
`2613
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`2620
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`2651
`
`2660
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`A 52 Gllz Phased-Array Receiver Front-End in 90 ntn Digital CMOS ......................................................................
`....................................................................... K. Scf'tt'r'r. S. Smut-ken. J. Bar-remain. P. I‘v/ctmbncq. and Y. Roim'n
`A Scalable 6-to-18 GHz Concurrent Dual-Band Quad-Beam Phased-Array Receiver in CMOS ..........................................
`................................................... S. Jenn, X'J. Wang, H. Wang, F. b‘m'm, A. Natunfinn. A. Bubakhani, and A. Hajt'mt'ri
`Transmitter Architectures Based on Near-Field Direct Antenna Modulation ........... A. Bubakimni, D. B. Rutledge. wtdA. Ilctjt’mt'ri
`A Compact Wideband FrOntrEnd Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS ....................................
`...................................... J. Bm'remmu, A. Bevihthtm. S. Brmtekt‘rr. M. DE‘Il’t’HI. M. Kut'jk, P. Munbncq. and J. Cranincrkx
`The BLIXER. a Wideband Balun-LNA-I/Q-Mixer Topology ..................................................................................
`............................................................... S. C. Bitmkmeer: E. A. 1'”. Klmnperink, D. M, W. Lecturer”, and B, Naum
`Class-C Harmonic CMOS VCOS. Will] a General Result on Phase Noise ................................. A. Mazmnri and P. Andmcmt'
`Tcrahcrtz CMOS Frequency Generator Using Linear Superposition Technique ............................................................
`...................................... D. Huang, T R. LuRrrc't'n, M.-C. F. Chang. L. Samoa-kn. A. thg. R. Campbell. and M. Andrews
`A 56—65 Gllz Injection-Leckcd Frequency Tripler With Quadrature Outputs in 90-nm CMOS ............. W. L Chan and]. R. Lang
`A Fully-Integrated Quad-Band GSM/GPRS CMOS Power Amplifier .......................................................................
`2747
`............................ I. Aoki, 3. Km. R. Mngmm. R. Apurict'o, E Balm. J. Zuct'trm, G. Hatchet: D. Mc'Clymrmt. and A. Htu't'mirt'
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`
`2693
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`2706
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`2730
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`
`A Fiddfrogrammable Analog Array of 55 Digitally Tunable OTAs in a Hexagonal Lattice ..............................................
`.................................................................... J. Becket: F. Henriei. S. firndvlrnhm'g. M. Orrmwmr. and Y. Mcumii
`A Current-Feedback Instrultlentation Amplifier With 5 11V Offset for Bidirectional High—Side Current-Sensing ........................
`2769
`.......................................................................................... J. E Wine, J. H. Hmjst'ng. and K. A. A. Mrtkt‘nwa
`
`
`2759
`
`*
`
`©IEEE
`
`iii
`
`

`

`—__~_.-——.___—_________——._—________
`
`A Low-Noise Wide~BW 3.6-GHz Digital AS Fractional-N Frequency Synthesizer With a Noiseishaping Time-to—Digital Converter
`and Quantization Noise Cancellation .................................................... C.-H. Hm, M. Z. Straayt'r. and M. H. PI’ITUII
`Spurious Tone Suppression Techniques Applied to a WideiBandwidth 2.4 GHz FractionalAN PLL .......................................
`................................................................................................ K. J. Wang. A. Swamr'iirrllmn. and I. Calm"
`Load-Independent Control of Switching DC-DC Converters With Freewheeling Current Feedback ......................................
`................................................................................. Yi-J. W00. H.-P. Le. G.-II. Clio. (1-H. Clio. (HMS-I. Kim
`A to MHz Bandwidth. 2 mV Ripple PA Regulator for CDMA Transmitters ................... W—l’. Chit. B. Brifrkctlnghr. and S. Kiwi
`A Pulse—Based Ultra-Widcbattd Transmitter in 90-nm CMOS for WPANS .............................. M. Demir'tl'an and R. R. Spencer
`A Fully Integrated [4 Band. 3.] to 10.6 GI-lz 0.13 pm SiGe BiCMOS UWB RF Transceiver .............................................
`........................... 0. Wr-‘r'rhm; M. Cuw‘n. A. Schneider: R. Rr'nm'nger: B. Lirmg, L. Bu, Y. fin. J. Rogers, and J. Murcincrwrrge
`UWB Fast—Hopping Frequency Generation Based on Sub-Harmonie Injection Locking ...................................................
`............................................. S. Dal Test), A. Bevilrtt'qtm. M. Tiebum. 5. Mrtrzrili. C. Summer. A. German. and A. Nevimii
`Equalization of Third-Order lntertttodulntion Products in Wideband Direct Conversion Receivers ........ E. A. Kec'hr rrrrdA. Hujimiri
`A Low-Power WCDMA Transmitter With an Integrated Notch Filter ......................................... A. Mirmei and H. Bambi
`A Dual-Band CMOS MEMO Radio SOC for [El—CE: 302.l in Wireless LAN .................................................................
`......................................................... M. Zcrrgan’. L. Y. Nathan-rid. H, Srmtttl'rtfi, S. S. Maria. A. Klwirkl'im'ii, P. Chen.
`K. Gang. 8. l/(rkiii-Amiui, J. A. Hit-ring, S. Chen. M. Teri-minis. B. Kai-:ynski. S. Linmlyrw'cis, M. P. Mark. H. Grin. M. Lee. R. Chang,
`H. Dagrm. S. AIJII'UIIHI'IF-AII'IJI’M. B. Brtyrr'kt'n. K. Ottndera. S. Memt'is. A. Chung. K thjrrvi. S. H. Jen, D. K. Sn, and B. A. “bailey
`A Single-Chip CMOS Bluetooth v2.1 Radio SoC ................................................................................. W. W. Si,
`2896
`D. Wehw: S. AIJJO-Iiflhi'diibflik. M- Lee, R. Chang. H. Dngrm, H. Gun,
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`2882
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`~— I6 dB Return Loss Over 10 GHz
`A T—CoiI-Enhanced 8.5 Gb/s Higthwing SST Transmitter in 65 mn Bulk CMOS With 4:
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`A ”L3 (iii/5 BUISI'MOUC CDR Using a 3: DAC
`J- Teradu, K. Nisltimtrm. S. Kimurrr, H. Kurstrmr'. N.
`lhritirrmm. and Y. 0}”me
`A 40-Gh/s C‘DR Circuit With Adaptive Decision-Point Control Based on Eye‘Opening Monitor Feedback ..............................
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`A 90 nm CMOS DSP MLSD Transceiver With Integrated AFE for Electronic Dispersion Compensation of Multimnde Optical Fibers
`at It) Gb/s ..................................................................................................................... 0. E. Agazzi,
`M. R. Harrie, D. E. Crt'velli. H. S. Crrrrer: A. Nrtzemi. G. Lmtrr, F. RGHKJS, R. Lripec. C. Grace. 3. Kobr’issy. C. Aiiidr'rt, M. Krrzemi,
`M. Ktrrgm: C. Marque; S. Rampmsrrd, F. Bully. V. Purse. S. Ming, G. Asmrmis. G. Eaton, N. Swansea. 7? Lindsrrv. and F. Voois
`Fast Power Transient Management for (DC-192 WDM Add/Drop Networks
`H.—M. Brie. J. Ashbrrmk, N. Shrmbhrtg, and/i. Singer
`Low-Spur. Loquhase-Noise Cluck Multiplier Based on 3 Combination of PLL and Recirculating DLL With Dual-Pulse Ring Oscillator
`2967
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`A Multi-Aperture Image Sensor With 0.7 pm Pixels in 0.! l {It'll CMOS Technology ......... K. Fife. A. El Grtrtml. and H.-S. P. Wang
`A 5 pW/Channel Spectral Analysis [C for Chronic Bidirectional BraineMachine Interfaces ..............................................
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`A 200 er Eight-Channel EEG Acquisition ASIC for Ambulatory EEG Systems ..........................................................
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`A Mode-Matching SA Closed-Loop Vibratory Gyroscope Readout Interface With a 0.004°Is/\/Hz Noise Floor Over a 50 Hz Band
`............................................................................................................... C. D. Ear/ore and B. E. Honor
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`3006
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`3025
`
`3039
`
`M 3
`
`049
`2003 INDEX .....................................................................................................................................
`M
`
`iv
`
`iv
`
`

`

`This material may be protected by Copyright law (Title 17 U.S. Code)
`
`

`

`lliltl
`
`IlElilEJUURNAL ()l: SOLID-STATE CIRCUITS. Vll[.. 4}. NO.
`
`|'.‘. IJIEClEMIlIER ZEltlli
`
`———I—mnm-—|-fl—1
`
`DSP
`
`
`E 5
`‘3
`.5.
`_
`h m
`% g 3
`RFenvelnpe
`I g g
`
`
`M
`2 n. g
`1 g g
`
`o
`VRFtl)
`I
`CD (9
`8
`
`lRF uptput
`Dan ennfl
`
`il
`
`th
`
`
`
`RF
`Carrier. 00.:
`
`Fig. 2. Typical polar modulation based transmitter block diagram.
`
`comFSD(dac)
`Composite
`pso-tdficl
`
`CDMAamalnpa
`
`Frequency (MHz)
`(bl
`
`Fig. 3. Power spectral density (PSDlol'ta) composite CDMA signal and (b) its
`extracted envelope.
`
`using an accurate current sensing technique. efficiency and lin-
`earity of the supply modulator is further optimized. The organ-
`ization of this paper is as follows: Section ll describes the op-
`eration of the PA supply modulator and techniques for perfor-
`mance optimization. Section III details the circuit level imple-
`mentations of the linear amplifier. switch-mode regulator and
`current sensing circuit. The measurement setup and results are
`presented in Section N. followed by a conclusion in Section V.
`
`II. DESIGN OF MASTER-SLAVE PA REGULATOR
`
`A. Operation
`
`Fig. 4 shows the block diagram of the proposed master—slave
`linear and switch-mode combined supply modulator loaded
`
`with a PA. A high GBW linear amplifier in voltage follower
`configuration ensures that output node Va“) tracks the refer-
`ence envelope voltage AU). A current sensing circuit. high gain
`transimpcdance amplifier and switch-mode regulator forms a
`global feedback control loop that suppresses the current output
`from the linear amplifier within the switch-mode regulator
`bandwidth. Consequently, a large portion of the load current is
`provided by the switch-mode regulator. The lower efficiency
`linear amplifier sources small amounts of output current 15,,(6)
`to cancel out switch-mode regulator ripple and high frequency
`signal content. The transient response of currents at the output
`of the switch-mode regulator Andi}, the linear amplifier Inuit)
`and combined master-slave supply modulator IOU.) is shown
`in Fig. 5. Assuming an infinite GBW linear amplifier.
`this
`architecture will generate a ripple free output current IOU.) to
`the load. However. due to finite GBW of the linear amplifier.
`only the ripple energy within the linear amplifier is cancelled.
`This tradeoff between GBW of linear amplifier and ripple size
`will he discussed later
`
`To gain lurlher insight on the operation 01 master—slave
`supply modulators the current-mode lrequeney response oi
`the linear amplifier, switch-mode regulator, and their com-
`bined response are analyzed. The steady state output current
`of switch-mode regulator 15,“ can be defined by the linear
`regulator current Ir," as follows:
`
`1
`l.
`1
`Ilin
`15:11:—'Atia"—'—"‘.,I—'— (I)
`
`where n is the current sense ratio, Am. is the transimpedance
`gain. 8, is the slope of the ramp in the switch-mode regulator
`and [BL is the equivalent PA load resistance. The sensed current
`is amplilied by the transimpedance amplifier, comparator and
`the voltage divider formed by equivalent series resistance (ESR)
`of the loading inductor and resistive component RL of the PA
`load. The second-order LC filter and the ESR set the dominant
`
`pole location of the frequency response.
`From (1 ), we can derive the transfer function of the combined
`output current 10 as follows:
`
`I
`_"
`
`A
`
`l
`l
`=— —
`HL 1+—.-1+
`
`(2)
`
`

`

`CHi' H “L: PA REGULATDR FOR L'DMA TRANSMITTERS
`
`2811
`
`Supply Modulator
`
`Class AB Outputi V0“
`
`
`Envelope
`
`Class A3
`All) _
`ransllnea
`
`Biasing
`amp
`
`
`Switch
`Mode Out-ut
`
`
`
`
`
`
`i etching
`
`vastt}
`
`
`
`Fig. 4. The proposed master—slave linear and switch-mode PA regulator block diagram.
`
`Current Loop
`
`|
`Response. Klf)
`LIn ear
`,
`Switch Mode
`
`Amplifier
`ct Amplifier
`
`
`
`Fig. 3. Simplified block diagram ofthe proposed regulator showing ripple cancellation.
`
`
`
`Lit)
`
`where .-'l represents the input envelope signal and Arm is the
`open loop gain of the linear amplifier. The switch-mode regu-
`lator output current I5“, can be shown as
`
`
`= —..~—— - _ ' — [3)
`r -$,.'[1+s--L-C)-R ,
`L
`1 + i
`Am
`i
`RL
`1 + An"
`
`A
`
`and finally the linear amplifier output current In“ is represented
`by
`
`E rl-Sr-(t+sg-L-C)I
`:‘1
`Aria
`
`
`t
`—-
`l + slim
`
`(4)
`
`the output current response of the
`As shown in (3) and (4).
`switch-mode amplifier has a two—pole transfer function forming
`a second-order low-pass characteristic. while the output current
`response ofthe linear amplifier has a two-zero transfer function
`that contains a second-order high-pass characteristic. At low fre-
`quencies, the linear amplifier current output is suppressed and
`the switch-mode regulator dominates the output current. Con-
`versely. at high frequencies. the switch-mode regulator current
`response starts rolling off and the linear amplifier takes over the
`output current, The switch-mode regulator and linear amplifier
`current response combine and form a flat frequency response for
`the master—slave regulator. The frequency where switch-mode
`regulator current response rolls off and linear amplifier current
`response takes over is called transition frequency. fr. This fre-
`quency plays an important role on efficiency optimization and
`will he discussed in the next section.
`
`
`
`Currert(mA)
`
`700
`500
`
`100
`
`1
`
`1K
`
`1M
`
`16
`
`Frequency (Hz)
`
`t3. Current-mode frequency response of the linear amplilicr. the switch-
`Fig.
`mode regulator and the master—slave combined regulator.
`
`Fig. 6 plots the current—mode frequency response of the linear
`amplifier. switch-mode regulator and mastcrfislave regulator. As
`predicted in the mathematical analysis, second-order low-pass
`and high-pass characteristics were obtained. The resulted flat
`output current response is suitable for high linearity implemen-
`tation. In addition. the overall bandwidth extended by the linear
`amplifier makes the supply modulator suitable for wide band-
`width signal transmission.
`
`

`

`llilili JOURNAL OF SOLID-STATE CIRL'L'ITS. VOL 43. N0 ll DECEMBER 2|}!!!
`
`In“):
`
`Low FT
`
` Frequency
`(3)
`
`1mm
`
`PSDtdBe).Currentth)
`
`(mA)
`
`PSD(dBcl.Cun’ent
`
`
`
`High Fr
`
`Frequency
`
`([1)
`
`Fig. 8. Portion of CDMA spectrum amplified by linear amplifier and switch-
`mode regulator at ta) low f;- and (b) high fr.
`
`the envelope PSD contains high DC content and most of the
`envelope energy is accumulated at frequencies less than 2 MHZ
`with a small portion ofthe envelope energy rolling offal higher
`frequencies. The bandwidth specifications of the switch-mode
`regulator can be relaxed further reduce the switching losses and
`use the linear amplifier to amplify the high frequency portion
`of the signal. However, as the bandwidth of the high efficiency
`switch-mode regulator becomes too low.
`the low efficiency
`lincar amplifier dominates the output current, reducing overall
`efficiency. Fig. 8 shows the portions of the envelope spectrum
`amplified by the linear amplifier and switch-mode regulator
`with different transition frequencies fr. Fig. 9 shows that peak
`efficiency of the supply modulator with a 20 dBm. 4-00 kHz
`SSB suppressed carrier modulated input waveform is achieved
`at 100 kHz fr.
`As discussed earlier, output ripple is another critical spec-
`ification requirement for PA supply modulator design due to
`stringent ACPR and spurious emission requirements. [8].
`In
`the proposed master—slave linear and switch-mode regulator.
`a significant portion of current ripple from the switch—mode
`
`A 20
`
`aa
`
`Dm
`D.
`ia0
`
`e 5Eeg
`
`U
`
`
`
`4
`
`1
`
`o
`
`10
`
`”mi
`
`40
`
`tit/l
`50
`
`l
`
`so
`20
`FrequencthIrt)
`(a)
`
`rum—c—Mflfi
`za-
`
`e
`
`5
`
`E 8
`
`E
`a
`as
`2
`
`-2t]i
`|
`u.
`r 40!
`
`sol
`;
`-an:
`l
`
`m
`
`{LI-“ML.”
`th
`
`Emmi
`
`
`42!);
`o
`10
`20
`30
`4e
`50
`Frequencth-tz)
`(h)
`
`Fig. '3. Ripple energy for a 10 dBm. 100 kHz SSB suppressed carrier modulav
`tion wa\‘uform for {a} a synchronous rectifier versus lb] 3 hysteretic controller.
`
`B. Peljfiu'mrtrtce Opriritizarr'mt
`
`Master—slave regulator configuration is commonly used for
`audio amplifiers, and for these applications a switch-mode
`regulator is typically configured in hysteretie control mode.
`Hysteretic controllers do not need a clocked comparator; instead
`they use a window comparator. and frequency of operation
`depends on the load conditions. The loop response ot‘hysteretic
`controllers is quite fast during load transients. However. this
`variable frequency operation generates wideband spurious
`emissions at the regulator output. This in turn increases the AC
`power from the linear amplifier since more ripple energy falls
`within class—AB amplifier bandwidth. The two power spectral
`density plots in Fig. 7 represent the ripple energy for a 10 (”3111.
`100 kHz single sideband (SSB) suppressed carrier modulation
`waveform for a synchronous rectifier versus a hysteretic con-
`troller. As shown in this figure. the integrated ripple energy
`within the class-AB bandwidth is much higher for a hysteretic
`controller. For wideband modulation schemes.
`this analysis
`shows that synchronous rectifiers are a better choice for low
`power. low spurious emissions design.
`To optimize the efficiency of a PA supply modulator. two
`properties of the envelope signals should he considered: the
`power level probability density function (PDF) discussed in
`Fig.
`I and power spectral density {PSD). As shown in Fig. 3.
`
`

`

`Etna
`
`Va
`
`VM
`
`omparator
`
`
`G = L2 = fl: Vm
`°
`V...
`we
`V.
`
`T
`
`Vraf
`
`Ramp
`Vat)
`
`C
`
`Vri/l/M/l
`
`Fia. 11‘
`g
`
`Gain calculation in comparator. D is the duty cycle of i 'pme ).
`
`
`Current
`
`
`
`Amplililr
`
`
`
`
`Comparator
`I
`Linear Model
`Fig. 1'2. Linear model for master—slave linear and switch-mode regulator.
`
`-5... l:mma
`
`SUdH
`
`,
`Transrmperlanee
`amplifier
`
`1MB% CONFIRM
`
`Dfl
`
`LC tiller
`
`4°65
`
`F
`
`5"
`
`Combined
`response
`
`Individual block and the combined frequency responses in switch-
`Fig l3.
`mode regulator feedback loop.
`
`0 dB and used —55 dBc per 30 kHz bandwidth ACPR require-
`ments to extract a maximum ripple specification of 2 mVpp
`at the overall regulator output [8]. As shown in Fig.
`lOtc). as
`the linear regulator unity gain-bandwidth increases. the voltage
`ripple at
`the output reduces. with the expense of reduced
`efficiency and increased linear regulator power consumption.
`For a given 2 mVpp ripple specification at a typical
`to dBm
`output power level. a linear regulator unity gain-bandwidth of
`tilt) Mill is selected.
`
`C. Switch-Mode Regulator Feedback Loop
`
`The switch—mode regulator feedback loop includes a current
`sensing circuit. an error amplifier, a comparator. power stage and
`a low-pass filter and is designed with maximum loop gain for
`
`CHU er «1.: PA REGULA‘l'UR l-‘UR L'DMA 'I'RANSMITTl-IRS
`
`
`
`Efficiency(“Hal
`
`38
`
`4:.o
`
`10
`
`100
`
`1000
`
`Transition frequency Ff (kHz)
`
`Fig. 9. Efficiency optimization of a 20 dBm, 400 kHz SSE suppressed carrier
`modulation envelope waveform by varying trartsition frequency IT,
`
`at)
`so
`40
`an
`
`20
`10
`
`D
`
`20
`
`
`
`(mV)
`Outputripple
`
`
`60
`4D
`hductance {qu
`
`BD
`
`100
`
`50
`a IOMHz
`Switching frequency (MHz)
`.. __ .
`
`100
`
`
`
`0
`
`100
`50
`Supply modulator BWlMHzl
`
`150
`
`
`
`
`
`Outputripple(mV)
`
`7
`S 5
`E 5
`E 4
`E
`3
`g 2
`8
`
`10
`
`ltl. Peak-to-pcnk output voltage ripple versus
`Fig,
`(b) switching frequency. and (c) linenr amplifier GBW.
`
`(a)
`
`load inductor.
`
`regulator is cancelled by the linear amplifier. This results in a
`much smaller residue voltage and current ripple at the PA drain.
`Output inductor and switching frequency also play an important
`role on output ripple value. Fig. 10{a) and (b) shows output
`ripple versus load inductor and switching frequency for the
`proposed composite regulator. Since both ripple frequency and
`output tiller corner is determined by the transition frequency.
`these parameters cannot be used for ripple optimization. There-
`fore. the effectiveness of current ripple cancellation depends on
`the GBW of the linear amplifier. For the ripple specification. we
`have assumed a worst case PA power supply rejection (PSR) of
`
`

`

`2M4
`
`IIEIEIE JUURNAL UI: SULID-STATESCIRCUITS. VOL. 4.1.310. II. DECEMBER 200E
`
`
`
`Rail-tn-ru’l
`Input Stage
`
`Class AB
`
`Translinear Biaslng
`
`Output Stage
`
`Fig. 14. Rait-to-rail input linear class-AB ampliticr with common-source output stage in voltage follower configuration for ripple cancellation and master—slave
`supply modulator bandwidth extension.
`
`
`l Im(t)=lmhtt)-|M(t)
`.— Igntt)
` Vutt) : voltage is set
`
`
`by linear amplifier
`
`Fig. 15. Switch-mode regulator in master—slave supply modulator for high efficiency amplification.
`
`accurate envelope tracking and highest linear amplifier output
`current suppression. For AC analysis. a linear model is utilized.
`As shown in Fig. l l. linearized gain ot‘the comparator is defined
`by the ratio of its output voltage swing to the amplitude of its
`ramp input. prmttl is the switching version of I"; (t) that has
`equal magnitude but contains stronger and more high-frequency
`harmonics. A linear model is obtained and Fig. 12 shows the
`linearized model of the system.
`In the comparator design a ramp voltage swing of il.3 V is
`used. yielding an equivalent gain of It). This gain is optimized
`in such a way that there is minimum penalty to the loop band-
`width and phase margin. The disadvantage of using a smaller
`rarnp voltage is the increased comparator response time. This
`delay results in degradation in envelope tracking accuracy of the
`switch mode output current and consumes more linear amplifier
`output current to correct the time delay errors. Furthermore. ex-
`cess comparator delays degrade the phase margin of the feed-
`back loop around the combined regulator. In this design. with
`the switching frequency of the supply modulator at 10 MHz
`and a comparator BW of 96 MHz, the comparator achieves a
`response time of less than 0 as. The delay introduces a phase
`shift of less than |° and requires almost no extra current from
`the linear amplifier.
`To ensure the stability of the feedback loop in the switch-
`modc regulator. the bandwidth of the switch-mode regulating
`
`loop should be at least ten times less than the switching fre-
`quency. The limited operating bandwidth filters the high fre-
`quency contents of the output current ripple and prevents insta-
`bility. To minimize current use from the linear amplifier. cl