\EEE JOURNAL OF
`SOLID-STATE
`
`
`
`‘nECEMBER 2007
`
`VOLUME 42
`
`NUMBER 12
`
`WSCBC
`
`?
`
`(ISSN 0018-9200)
`
`2635
`
`
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`ANALOG CIRCUITS AND CONVERTERS
`
`2639
`2631
`2666
`2677
`2688
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`2696
`
`oa veneer eewaee pees aed bee ee enoe
`
`2706
`H.-P. Le, C.-S. Chae, K.-C, Lee, S.-W. Wang, G.-H. Cho, and G.-H. Cho
`
`
`INTEL 1311
`
`
`AL ISSUE ON THE 2007 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC)
`
`Introduction tothe Special bom. tye 207 TreatSosermmtactel SellsSete Cleslts Coeieeence ia
`cert: ait bexeaasabsi i Lael be RBs uakidmalfeee cade ee rds
`. J. Sevenhons, J.T. Stonick, M. Miller, andJ. E D.‘Hurwitz
`
`AWide-Bundwidth 29.4 Cieia150M Band Fractionsl-N PLL Wish AdaptivePhisse Noise Cancellation...
`
`_A. Swaminathan, K. J, Wane.“sind Galion
`AMic-opowerinterfaceASICforaCapacitive3-AxisMicro-Accelernmeter SeeELEN Rete FsEoaeerecpy es
`
`|
`_..--. M. Puavola, M. Kamirdinen, J. A.M, Jéirvinen, M. Saukoski, M. Latha, and K. Af Halonen
`
`[A2'WCMOSHydSwitching Amplitude Peeteenctecsennero
`_OT-W. Kwak,M.-C.Lee,and G.-H. Cho
`ye> gua
`
`AZe1
`Based8-bit 200 MS/sPipelinedADC......,.0...00..-sieeenere-oerenocessesnen L. Brooks and H.-S. Lee
`A 10-1208!
`« 1,0-mm? 90-nin CMOSPipeline ADC for Flat Panel Display Applications...
`S.C. Lee, ¥-D. Jeon, J-K. Kwon,‘tind Kin
`
`4 56iWContinuous-Time QuadratureCascaded52Modulator With 77 dB DRin a Neat Zero-IF 20 MHz Band ..
`wae - -SIBIUSA TE ERS INO oon eee erteprenrspyenecane LJ. Breems, R. Rutten, RH, M, van Veldhoven, and G. van der Weide
`
`ASingle:Inductorsila DC-DCConverterWithFiveOutputsand Ordered Power-DistributiveControl .......-...
`
`
`2715
`40-Go/s High-Gain Distributed Amplifiers With Cascaded Guitt Stages in 0. 18-em CMOS... 1-C Chienand L.-H. Lu
`
`LA4044 Ghis 3% Oversampling CMOS CDR/1:16 DEMUX _N. Nedwvic,
`N. Tzartzanis, H. Tamura, FM. Rotella, M. Wiklund. Y. Mizutani,¥.Okaniwa, T, Kuroda,J.‘Ogawa,and W. W. Walker
`2726
`Aee Integrated 4 x 10-Gt¥s DWDM Optoelectronic Traisceiver Implemented in a Standard 0.13 jm CMOS SOI
`[TeHRIONOIBY ots Serenwett bncensos A. Narasimha, B, Analui, ¥. Liang, T. 4. Sleboda, §. Abdalla, E. Balmater, 8. Gloeckner.
`2736
`| D Guckenberger, M. Harrison, R. G. M. P. Kowitans, D. Kuehsirski, A, Mekis,S. Mirsuidi, D. Song. and T, Pinguet
`
`_ (Contents Continued on Back Cover)
`
`
`
`IEEE
`
`i
`
`INTEL 1311
`
`

`

`IEEE JOURNAL OF SOLID-STATE CIRCUITS
`The IEEE JOURNAL OF SOLID-STATE CIRCUITS is published by the IEEE Solid-State Circuits Society, All TEEE membersare eligible for membership and will receive this J
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`Digital Object Identifier 10.1109/JSSC.2007.912792
`
`ii
`
`

`

`
`A PUBLICATION OF THE IEEE SOLID-STATE CIRCUITS SOCIETY
`
`
`
`VOLUME 42
`
`NUMBER 12
`
`IJSCBC
`
`(ISSN 0018-9200)
`
`| SPECIAL ISSUE ON THE 2007 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE(ISSCC)
`SSSSSS
`Introduction to the Special Issue on the 2007 IEEE International Solid-State Circuits Conference ..............eseeseeeee
`RED ne OEAy id. A onl me er aut J. Sevenhans, J. T. Stonick, M. Miller, and J. E. D. Hurwitz
`
`2635
`
`
`
`
`2639
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`
`
`‘A Wide-Bandwidth 2.4 GHz ISM BandFractional-N PLL With Adaptive Phase Noise Cancellation ....................5.
`PIN Meee TO i eee er Me Aste ee ec ei Lie A. Swaminathan, K. J. Wang, andI. Galton
`ANMicropower Interface ASIC for a Capacitive 3-Axis Micro-Accelerometer .............:.cceecee eee e entre rete nee e nee cen ees
`
`Pe te cree wate dae M. Paavola, M. Kdméirdinen, J. A. M. Jaérvinen, M. Saukoski, M. Laiho, and K. A. I. Halonen
`
`A 2 W CMOSHybrid Switching Amplitude Modulator for EDGE Polar Transmitters ................ceseseeeeee sees e ene
`2666
`Se ELE 1 ae Fe dU ae aes aee eea T.-W. Kwak, M.-C. Lee, and G.-H. Cho
`
`2677
`A Zero-Crossing-Based 8-bit 200 MS/s Pipelined ADC ......... 0.0... cece seers settee erent ee ee ene L, Brooks and H.-S. Lee
`A 10-bit 205-MS/s 1.0-mm? 90-nm CMOS Pipeline ADC for Flat Panel Display Applications .................6:seeseees
`TAT Ws MSMONPITY A OLSEN, Rene eee CN NI ODI ys | HAMS tye. or slelsls steele Sr eee S.-C. Lee, Y.-D. Jeon, J.-K. Kwon, and J, Kim—2688
`
`
`
`Mr cael Foes Soe Me rece Meer ee oA a be Ho obs L. J. Breems, R. Rutten, R. H. M. van Veldhoven, and G. van der Weide
`A Single-Inductor Switching DC-DC Converter With Five Outputs and Ordered Power-Distributive Control ............
`2706
`SR ssc. eee ee LEE ee eG H.-P. Le, C.-S. Chae, K.-C. Lee, S.-W. Wang, G.-H. Cho, and G.-H. Cho
`
`
`2651
`
`2696
`
`40-Gb/s High-Gain Distributed Amplifiers With Cascaded Gain Stagesin 0.18-jam CMOS.... J.-C. Chien and L.-H.Lu
`A 40-44 Gb/s 3x Oversampling CMOS CDR/1:16 DEMUX ........ 6c cece cece cette eee ne tenon enene nae ees N. Nedovic,
`N. Tzartzanis, H. Tamura, F. M. Rotella, M. Wiklund, Y. Mizutani, Y. Okaniwa, T. Kuroda, J. Ogawa, and W. W. Walker
`A Fully Integrated 4 x 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 4m CMOS SOL
`lechnology Ube tetas... oe A. Narasimha, B. Analui, Y. Liang, T. J. Sleboda, S. Abdalla, E, Balmater, S. Gloeckner,
`2736
`_ D. Guckenberger, M. Harrison, R. G. M. P. Koumans, D. Kucharski, A. Mekis, S. Mirsaidi, D. Song, and T, Pinguet
`
`
`2715
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`2726
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`IEEE
`
`
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`iii
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`

`A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS 20... ccc ccc cee cree ene reer Ee ene reer EERE EE EEE EEE EEE Eee,
`Lae. i oe J. Poulton, R. Palmer A. M. Fuller, T. Greer, J. Eyles, W. J. Dally, and M. Horowitz
`A Self-Calibrated On-Chip Phase-Noise MeasurementCircuit With —75 dBcSingle-ToneSensitivity at 1|OOkHz Offset
`...
`pe, Biyylbet oe SEER ETON: <> «VS OARTRRR ERC + 0- fie" on oe. See (0 Sees W. Khalil, B. Bakkaloglu, and S. Kiaej
`
`WIRELESS AND RF
`
`A BlockerFiltering Technique for SAW-Less Wireless Receivers ......... 0.0: cece cree cree ee ee ence eran e ene tes H. Darabi
`A Multimode Transmitter in 0.13 ;zm CMOSUsing Direct-Digital RF Modulator ................:.e ce eee nent eee
`ie PT DM eo cs ee eos ac els ofa. MOR Fo is «WOT P. Eloranta, P. Seppinen, S. Kallioinen, T. Saarela, and A. Parssinen
`A Single-Chip Dual-Band CDMA2000Transceiver in 0.13 ppm CMOS........ 0 eect eee etter tet iny
`opie et RE re Be ore J. Zipper, C. Stéger, G. Hueber, R. Vazny, W. Schelmbauer, B. Adler, and R. Hagelauer
`A Fully Integrated MIMO Multiband Direct Conversion CMOSTransceiver for WLAN Applications (802.11n).........
`4 he A. Behzad, K. A, Carter, H.-M. Chien, S. Wu, M.-A. Pan, C. P. Lee, Q. Li, J. C. Leete, S. Au, M. S. Kappes,
`Z. Zhou, D. Ojo, L. Zhang, A. Zolfaghari, J. Castanada, H. Darabi, B. Yeung, A. Rofougaran, M. Rofougaran,
`J. Trachewsky, T. Moorti, R. Gaikwad, A. Bagchi, J. S. Hammerschmidt, J. Pattin, J. J. Rael, and B. Marholey
`SiP Tuner With Integrated LC Tracking Filter for Both Cable and Terrestrial TV Reception ...........-.:.:seseetteeeeeees
`J.R. Tourret, S. Amiot, M. Bernard, M. Bouhamame, C. Caron, O. Crand, G. Denise,V. Filldtre, T. Kervaon, M.Kristen,
`L. Lo Coco, F. Mercier, J. M. Paris, F. Pichon, S. Prouet, V. Rambeau, S. Robert, J. van Sinderen, and O. Susplugas
`A 900 MHz UHF RFID ReaderTransceiver IC ........ cece eee enn enn nen eee E EERE DE Err EEE EES EEE EG
`on meena e one noe oe a S. Chiu, L. Kipnis, M. Loyer, J. Rapp, D. Westberg, J. Johansson, and P. Johansson
`An Integrated Ultra-Wideband Timed Array Receiver in 0.13 m CMOS Using a Path-Sharing True Time Delay
`FATChiteGtURe er AERC CREPE eer GEE CURE GEe EEC ECE E CL EEEE CEE GS e a oC Cect eer ore T.-S. Chu, J. Roderick, and H. Hashemi
`A 2.5 nJ/bit 0.65 V Pulsed UWB Receiver in 90 nm CMOS..............2..cceeeene eee E_S. Lee and A. P. Chandrakasan
`A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWBAll-Digital TX in 90 nm CMOSfor IEEE 802.15.4a .........cscereneeeeeneness
`HOUSER oo ao a als OP OGUTMVG oe TOMES J. Ryckaert, G. Van der Plas, V. De Heyn, C. Desset, B. Van Poucke, and J. Craninckx
`A Magnetically Tuned Quadrature Oscillator ............ G. Cusmai, M. Repossi, G. Albasini, A. Mazzanti, and F- Svelto
`A 23-to-29 GHz Transconductor-Tuned VCO MMIC in 0.13 pam CMOS 0... ce ceceer cerns K. Kwok and J. R. Long
`Heterodyne Phase Locking: A Technique for High-Speed Frequency Division .................ssseseeeeeeeeee ees B. Razavi
`Millimeter-Wave Devices and Circuit Blocks up to 104 GHz in 90 nm CMOS........... ccc cece eect reer eee
`Re ei Si cloutqesacee oite 1 ae MEE Pr eecebiae. seep shel ss cae B. Heydari, M. Bohsali, E. Adabi, and A. M. Niknejad
`
`2745
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`2758
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`2766
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`2774
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`2785
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`2795
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`2809
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`2822
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`2834
`2851
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`2860
`2870
`2878
`2887
`
`2893
`
`IMAGING, MEMS, MEDICAL, AND DISPLAYS
`
`2904)
`
`A Continuous-Grain Silicon-System LCD With Optical Input Function ........... 0.6: :cceeeee etre terete nent e ene
`selec ede Oba wee de Ny OME SLOUE oes ce UR. oe memes Seer, ceri, vento WE C. J. Brown, H. Kato, K. Maeda, and B. Hadwen
`10-bit Driver IC Using 3-bit DAC Embedded Operational Amplifier for Spatial Optical Modulators (SOMs).............
`Erni ee ee ere fe otee J.-S. Kang, J.-H. Kim, S.-Y. Kim, J.-¥. Song, O.-K. Kwon,
`Y.-J. Lee, B.-H. Kim, C.-W. Park, K.-S. Kwon, W.-T. Choi, S.-K. Yun, 1.-J. Yeo, K.-B. Han, T.-S. Kim, and S.-I. Park
`CMOSSingle-Chip Electronic Compass With Microcontroller ............ C. Schott, R. Racz, A. Manco, and N. Simonne
`A 2 W 100 nVAtHz Chopper-Stabilized Instrumentation Amplifier for Chronic Measurement of Neural Field
`Potentialso See = eS ce ees ORE ers T. Denison, K. Consoer, W. Santa, A.-T. Avestruz, J. Cooley, and A. Kelly
`A 232-Channel Epiretinal Stimulator ASIC ...........cc.ccceee eee M. Ortmanns, A. Rocke, M, Gehrke, and H.-J. Tiedtke
`A 1/2.7-in 2.96 MPixel CMOSImage Sensor With Double CDS Architecture for Full High-Definition Camcorders.....
`voce reese ie BOE, Me en eee gt On oe SeECe Ree REEC ROE ee oeenre cr er Serie H. Takahashi, T. Noda, T. Matsuda,
`T. Watanabe, M. Shinohara, T. Endo, S. Takimoto, R. Mishima, S. Nishimura, K. Sakurai, H. Yuzurihara, and S. Inoue
`Multiple-Ramp Column-Parallel ADC Architectures for CMOS Image Sensors...............-..2:05e00(ees:
`2968
`he oo EE ae Eee Eee. tee M.F Snoeij, A. J. P. Theuwissen, K. A. A. Makinwa, and J. H. Huijsing
`A Spatial-Temporal Multiresolution CMOS Image Sensor With Adaptive Frame Rates for Tracking the Moving Objects
`2978|
`in Region-of-Interest and Suppressing Motion Blur............ J. Choi, S.-W. Han, S.-J. Kim, S.-I. Chang, and E. Yoon
`aaaSS
`
`2913
`2923
`
`2934
`2946
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`2960
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`This material may be protected by Copyright law (Title 17 U.S. Code)
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`
`KWAK etal: 2 W CMOS HYBRID SWITCHING AMPLITUDE MODULATOR FOR EDGE POLAR TRANSMITTERS
`
`2667
`
`Amplitude Modulator
`
`v(t)
`
`R(t)—
`
`1, Q
`
`Phase Modulator
`i)
`Patoo2*
`preg Ly
`
`[D/A)IA
`
`
`
` R)=VP +Q
`
` Linear Amp Switching Amp
`
`g(t) =tan"(Q/1)
`
`v(t)
`
`. Block diagram of a polar transmitter.
`
`B. Proposed Hybrid Switching Amplifier
`As shown in Fig. 3(a), the PWM control is used for the
`switching stage to mitigate the difficulties in the design of the
`linear amplifier. Hence, the switching frequency f, is fixed,
`which makesthe unity-gain frequency constant as well. In addi-
`tion, the peak-to-peak ripple current of the PWM-based hybrid
`switching amplifier is less than that of the hysteresis-based one
`[5] with the constant ripple current on the assumption that the
`switching frequency of the former is equal to the maximum
`switching frequency of the latter. This is because the relation
`between the switching frequency and the peak-to-peak ripple
`current Ai,. is expressed as follows for both cases:
`
`fs Aip = (Vaa/L)-D-(1— D)
`
`(2)
`
`where D is the dutyratio, Vaq is the supply voltage, and L is
`the inductance.
`However, when we use the PWM control, we must consider
`the loopstability. From Fig. 3(a), the current loop gain f can be
`found by
`
`A(s) =
`
`(3)
`A,ArAm/(4L+8l)
`where As, Ay, and Ajg are the current sense gain, integrator
`gain, and modulation gain, respectively, and (Zz, + sL)is the
`impedancefrom a switching node V,,. The modulation gain A jy
`is the ratio of Vag to a peak-to-peak magnitude ofa triangular
`wave. For loop compensation, as shown in Fig. 3(b), one zero
`at about 160 kHzis inserted into the integrator since two poles
`result from the integrator and the inductorin the currentloop.
`
`C. Third-Order Ripple Filter and Current Feedback
`Although the linear amplifier has low output impedance, the
`switching ripple current should be reduced to decrease both
`the output ripple voltage and the power consumption of the
`linear amplifier. For this purpose, as shown in Fig. 4, a third-
`orderfilter with £,, L2, and Cr is used in the current loop.
`
`(b)
`(a)
`
`(a) Conceptual diagram of the hybrid switching amplifier. (6) Phase
`‘Fig. 2.
`diagram of each current.
`
`
`(EER) applications [6], it has not been used for polar transmit-
`ters in CMOSprocess becauseofthe difficulty of designing a
`
`linear amplifier with a wide bandwidth,a low output impedance,
`
`and a high current-driving capability. However,if the switching
`
`‘Stage with a wide bandwidth and a low ripple current is used
`
`for the hybrid switching amplifier, such burdens of the linear
`
`amplifier can be reduced. By the way, a bandwidth and a ripple
`
`current are influenced by the control method. Compared with
`
`‘pulsewidth modulation (PWM)control, a hysteretic control of
`
`the switching amplifier relatively has a narrow bandwidth and
`
`alarge constantripple current because the switching frequency
`
`Varies according to the output voltage and the bandwidth is
`
`limited by the minimum switching frequency. Therefore, the
`
`Conventional hybrid switching amplifier based on the hysteretic
`
`Control has a relatively lower bandwidth and a larger ripple
`
`Current. To extend the narrow bandwidth wider,
`the linear
`
`
`‘amplifier must have a high current-driving capability according
`
`fo (1) to provide more signal current for making up for the
`
`Mistortion from the switching stage. In case of a large ripple
`
`‘Current, in particular, the linear amplifier must have a lower
`
`‘Output impedance at the switching frequency to reduce the
`
`“Sutput ripple voltage because the multiplication of the output
`
`Impedance of the linear amplifier and the ripple current makes
`
`the outputripple voltage.
`
`
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`

`

`2668
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL. 42, NO.12, DECEMBER 9900
`
` Au
`
`aol
`
`Se,ee re nae
` Current Loop B
`
`
`B(S) = ig /ig = AsAiAm/ (Zi + SL)
`
`1/(R.+ sl)
`
`ae
`
`wn
`
`160K
`
`Ri=4
`L=4uH
`
`
`Fig. 4. Hybrid switching amplifier with the third-orderripplefilter and the cur. i r
`rent feedback.
`
`pomecsseseess,
`
`
`AmAdB
`
`(b)
`
`Fig. 5. Hybrid switching amplifier with the feedforward path.
`
`
`
`(a) Simplified block diagram of the hybrid switching amplifier. (b) Bode
`Fig.3.
`plots for the currentloop design.
`
`In spite of the desirability of lowering the resonant frequency
`for greater reduction of the ripple current, two additional poles
`should have little impact on the current loop. Accordingly, the
`resonant frequency is chosen between the unity-gain frequency
`of the current loop and the switching frequency. Additionally,
`a dampingresistor Rg is inserted, taking a quality factor into
`account, because an excessively small Rg can generate an un-
`wanted resonance.
`To stabilize the current loop in spite of the relatively small
`Fa, the current feedback suggested in [7] is introduced. The
`ripple information is used for the hysteretic control in the ref-
`erence, whereas only a high-frequency signal current passing
`through the capacitor C'p is used for the PWM control with the
`same but negative gain as the current sense gain As, because the
`
`sensed ripple information is attenuated at the output of the in
`tegrator. The current loop therefore remains stable because the
`same voltage Vsrn, as in the case of a single inductor,is recov:
`ered without losing the high-frequency current component.
`
`D. Feedforward Path
`
`Asgivenin (1),the linear amplifier should provide some com
`pensation current to prevent the output voltage from being diss
`
`torted by the delay ofthe currentloopat the high frequency. The
`
`higherthe frequency, the more the compensation current flows: i
`There are higher frequency components than the EDGE base
`bandsignal of about 270 kHz in the amplitude pathof the polat|
`
`transmitter. Hence, an auxiliary circuit is necessary to alleviat® |
`the burden ofthe linear amplifier.
`ie
`If we add a feedforward path,like the one showninFig. 5, the
`
`input signal can directly control the switching amplifier. Such?
`
`
`
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`

`

`etal. 2 W CMOS HYBRID SWITCHING AMPLITUDE MODULATOR FOR EDGE POLAR TRANSMITTERS
`
`2669
`
`quae
`
`Feedforward Patheee
`
`,.
`
`>x2
`
`
`
`Poe
`
`SummingCircuit + Integrator
`
`
`Ripple Filter +
`Current Feedback
`
`Vo
`
`
`
`E.
`
`
`Fig. 6. Detailed block diagram of the hybrid switching amplifier.
`
`
`path is faster than the feedback current path formed by sensing
`the output current of the linear amplifier. Although the feedfor-
`
`ward signal can be injectedafter the integrator, it is added before
`the integrator in Fig. 5 considering the implementation of the
`
`summing circuit and integrator as will be explained in the next
`section. With this feedforward path, we can express the output
`currentas follows:
`
`Implementation of a Hybrid Switching Amplifier
`Fig. 6 showsthe detailed circuit of the hybrid switching am-
`plifier. In CMOSdesign, although three voltage signals can be
`added andthen integrated as shownin Figs. 4 and 5, the simul-
`taneous summation and integration of the signals at the node
`V., after the conversion of the three voltage signals into cur-
`rent ones, is advantageous,that is, the sensed output currentof
`the linear amplifier, the feedforward current, and the high-fre-
`jazeloes
`= Ayf ‘Vin
`quencycurrent throughtheripple filter are added together and
`% =
`= iat (As :ta+Ar-vin):Ar- Am:
`4L+ sb
`ZL
`integrated at the node with the inverted polarity of the last one.
`(4)
`Tn this case, the de gain of the integrator Ayo is replaced by
`Ryo and the sensing ratio of the output current of the linear
`where A,y is the overall closed-loop gain of 1/F. Since the
`amplifier is 1 to N so that the current sense gain As is 1/N.
`output current of the linear amplifier 7, ideally has to be equal
`The feedforward path gain Ap(s) given in (5) can be expressed
`lo zero, the gain of the feedforward path Ap (s) is given as
`as Apy(s)/Rbecause the input voltage Vj, is converted into
`the current by Ry after passing through the lead compensator
`ip(@) =e Ppa L+ s/wy Zr+sh
`Ary (s). As mentioned before, the zero and the pole of Ary(s)
`Ay Aro 14 s/w,
`ZL
`|
`should be located at the pole and the zero of the integrator, re-
`
`
`
`spectively.If the transfer functionsofthe integrator and Apy(s)
`are given, the value of Ry can be foundto set the de gain of
`Am Aro 1+s/w,
`Ar(s). The capacitor in the feedforward path C; is a coupling
`capacitor with a large capacitance.
`After the high-frequency current that passes through the
`ripplefilter is sensed as a voltage by the dampingresistor Ra,
`the voltage is converted into the current by R,¢. Since the
`
`
`
`
`
`
`
`
`f x Avg 11+s/wp (5)
`
`
`Where the integrator gain A;(s) is Azo-((1+s/wz)/(1+s/wp)).
`Notice that the gain of the feedforward path has the reciprocal
`
`characteristic of the integrator and the inductor to compensate
`for their delays.
`
`
`
`

`

`2670
`
`high-frequency current should be transferred to the integrator
`with the same gain of 1/.N as the output current of the linear
`amplifier, the value of R.- is set equal to N - Ry. The capacitor
`C> is also a coupling capacitor like C1.
`
`F. Design for the Class-E2 EDGE
`
`The Class-E2 EDGEspecifications require an average output
`power of 26 dBm and a peak-to-average powerratio of 3.2 dB.
`Accordingly, the amplitude modulator should be able to supply
`more than about 2.2 W, assuming that the RF power amplifier
`has a maximum efficiency of 40%. This meansthat the equiva-
`lent dc load resistance is approximately 4 2 when the maximum
`output voltage of the amplitude modulatoris 3 V at Vag = 3.5 V
`[2]. Hence, the hybrid switching amplifier is designed to drive a
`power amplifier with an equivalent impedance of 4 2 while its
`output voltage varies from 0.4 to 3 V.
`Despite the EDGE signal bandwidth of about 270 kHz, the
`amplitude modulator should have a bandwidth wider than 2 MHz
`to satisfy the error vector magnitude (EVM) and the spectral
`mask requirements because, as mentioned before, the amplitude
`component for the polar modulator becomes much wider than
`that of the original EDGE signal in the process of extractingit
`[1], [2]. Fortunately, however, the low-speed switching amplifier
`can efficiently supply mostof the output current because most of
`the EDGE amplitude signal power is concentrated on the low-
`frequency bandof less than 50 kHz, as shownin [1]. This is why
`the current loop @ is designed to have a unity-gain frequency
`of about 460 kHz using a 2 MHzswitching frequency with a
`4 ,H inductance, as shown in Fig. 3(b). As a result, a switching
`ripple current of about 110 mA,, is generated without the use
`of the third-order ripple filter at a duty ratio of 0.5. However,it
`is reduced up to about 40 mA,,,, with the third-orderripple filter
`and the current feedback. The values of the used components are
`as follows: L) = 3H, Ly = 1 pH, Cy = 100nF, Ry = 22,
`and Rep = 3909,
`On the other hand, the linear amplifier should have a band-
`width that is much wider than 2 MHz to compensate for the
`fast varying amplitude components that the switching ampli-
`fier cannot follow. The driving capability of the linear amplifier
`should also be more than at least 80 mA, including a switching
`ripple current and a high-frequency signal current, because, ac-
`cording to (1) and Fig. 3(b), the required output current of the
`linear amplifier is approximately 34 mA on the condition that
`the maximum output voltage at 50 kHz, V, = 1.25 - sin(2z -
`50 &- t) + 1.75 Vq., is applied to a 4 2 load. To putit con-
`cretely, [3] = 9.2, = 90° at 50 kHz from Fig. 3(b), and the
`output current from the switching stage is slower than the output
`current by a = 6.2°.
`
`Tl. LINEAR AMPLIFIER WITH A NOVEL CLASS-AB BUFFER
`
`A. Critical Design Parameters for the Linear Amplifier
`If the amplitude modulator has an input signal of a(t) and
`an output signal of a’(t) with a closed-loop gain of1, a’(t) is
`expressed as the summation of a(t) and the switching ripple
`voltage of ap - cos(wrt + 6), where wp is the switching fre-
`quency. By assuming the phase-modulated signal of cos(w,¢ +
`6(t)) is applied at the input of the RF power amplifier, we can
`
`IEEE JOURNAL OFSOLID-STATE CIRCUITS,VOL.42, NO. 12, DECEMBp8 2007
`
`Sc(t) =a(t) + cos (wet + O(t)) + aR: cos(wpt + $)
`cos (wot + O(t))
`
`
`
`express the output of the power amplifier sc(t) bythe any i
`tude modulation of a’(t) and cos(w.t + @(t)) as follows:
`f
`
`
`Thelast term is caused by the outputripple voltage ofthe ,
`plitude modulator, that is, the ripplevoltage from the switehi
`
`amplifier results in unwantedinterference with the phase-“mM
`lated carrier at the offset frequency of wp away fromthe Cattier
`
`frequency w,. Consequently, the fundamental component oft
`output ripple voltage should be a factor of approximately 7
`
`less than the outputvoltage of the amplitude modulatorto sati
`the spectral requirement of about —63 dBe for the maxim
`
`output powerof 29,2 dBm at the switching frequency [13],
`
`Because the switching ripple voltage at the outputofthe hy.
`brid switching amplifier is generated by the multiplication 9of.
`
`the ripple current and the output impedanceofthe linear ampli.
`
`fier, it is crucial to design the linear amplifier with low output |
`impedance. In this design, when we considertheripple current
`
`source the ipa current at any level of the output volt
`varying in the positive range during operation. In other words} }
`
`
`
`
`
`
`amplifier. We based our definition of the four-quadrant opel
`tion on the assumption that the output voltage at the center is)
`half Vaq because of using a single supply voltage:
`
`B. Conventional Class-AB Output Stages
`
`slew rate.
`
`A local negative feedback using an operational transcon-
`ductance amplifier (OTA) has often been applied to reduce the
`
`output impedancein a CS outputstage [9]. The loop gainof the |
`
`local feedback loop effectively reduces the output impedance |
`together with that of a global feedback loop. The higher the|
`
`loop gain of the OTA, the greater the decrease of the output|
`
`impedance. However, the output impedanceincreases at a high|
`
`frequency because the gains of both feedback loops decreas”
`
`due to the bandwidth limitation. While increasing the transco™ |
`
`ductance of the output transistor in a CS output stage help
`to reduce the output impedance with a Miller compensatiO®
`capacitorat a high frequency,it requires much power consump"
`tion and large area to obtain the desired output impedance.
`
`
`
`

`

`
`
`+Vag
`
`
`
`clipped
`by Muse
`
`(b)
`
`biasing circuit to achieve the four-quadrant operation required
`for the hybrid switching amplifier.
`
`C. Proposed Class-AB Output Stage With Low Output
`Impedance and Four-Quadrant Operation
`
`As shownin Fig. 8, a low output impedance and a four-quad-
`rant operation can be achieved by combining the twostructures
`shown in Fig. 7(a) and (b). Because the nMOSCStransistor
`Myczis added for the push-pull operation, four local loops can
`be found in the middle range of the output voltage. In addition,
`t