Attorney Docket No. PR00096
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`EVERLIGHT ELECTRONICS CO., LTD.
`Petitioner
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`v.
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`DOCUMENT SECURITY SYSTEMS, INC.
`Patent Owner
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`
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`U.S. Patent No. 7,256,486
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`
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`PETITION FOR INTER PARTES REVIEW OF
`
`U. S. PATENT NO. 7,256,486
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`UNDER 35 U.S.C. §§ 311-319 AND 37 C.F.R. § 42.100 ET SEQ.
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`Table of Contents
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`INTRODUCTION ........................................................................................... 1
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`I.
`II.
`REQUIREMENTS FOR AN INTER PARTES REVIEW PETITION ............ 1
`A. GROUNDS FOR STANDING (37 C.F.R. § 42.104(A)) ........................................ 1
`B. NOTICE OF LEAD AND BACKUP COUNSEL AND SERVICE INFORMATION
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`(37 C.F.R. § 42.8(B)(3)) ................................................................................ 1
`C. NOTICE OF REAL-PARTIES-IN-INTEREST (37 C.F.R. § 42.8(B)(1)) ................. 2
`D. NOTICE OF RELATED MATTERS (37 C.F.R. § 42.8(B)(2)) .............................. 2
`E.
`F.
`III.
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`FEE FOR INTER PARTES REVIEW ..................................................................... 2
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`PROOF OF SERVICE ........................................................................................2
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`IDENTIFICATION OF CLAIMS BEING CHALLENGED
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`THE BACKGROUND OF THE INVENTION .......................................................... 3
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`THE PURPORTED SOLUTION ........................................................................... 4
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`(§ 42.104(B)) .................................................................................................... 3
`IV. THE PURPORTED INVENTION .................................................................. 3
`A.
`B.
`V.
`SUMMARY OF THE RELEVANT PROSECUTION HISTORY ................. 6
`VI. CLAIM CONSTRUCTION ............................................................................. 8
`A.
`B.
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`“METALLIZED . . . SURFACE” .......................................................................... 8
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`“THE METALLIZED TOP MAJOR SURFACE COMPRISES A FIRST ELECTRODE .
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`. . AND THE METALLIZED BOTTOM MAJOR SURFACE COMPRISES A SECOND
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`ELECTRODE” ................................................................................................ 11
`VII. PERSON HAVING ORDINARY SKILL IN THE ART .............................. 13
`VIII. BRIEF DESCRIPTION OF THE PRIOR ART ............................................ 14
`A.
`B.
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`JAPANESE PATENT APPLICATION PUBLICATION NO. 2003-17754 (ROHM).. 14
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`JAPANESE PATENT APPLICATION PUBLICATION NO. 2001-352102
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`(MATSUSHITA) .............................................................................................. 15
`C. U.S. PATENT NO. 5,376,580 TO KISH ET AL. (“KISH”) ................................. 17
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`D. U.S. PATENT NO. 5,523,589 TO EDMOND ET AL. (“EDMOND 589”) .............. 18
`IX. PRECISE REASONS FOR THE RELIEF REQUESTED............................ 19
`A. GROUND 1: CLAIMS 1-3 ARE RENDERED OBVIOUS BY ROHM ALONE OR
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`IN VIEW OF KISH .......................................................................................... 19
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`Dependent Claim 2 .................................................................................. 28
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`Independent Claim 1 ............................................................................... 19
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`1.
`2.
`3.
`Dependent Claim 3 .................................................................................. 32
`B. GROUND 2: CLAIMS 1-3 ARE RENDERED OBVIOUS BY MATSUSHITA IN
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`VIEW OF EDMOND 589 ................................................................................. 33
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`1.
`2.
`3.
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`Independent Claim 1 ............................................................................... 33
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`Dependent Claim 2 .................................................................................. 43
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`Dependent Claim 3 .................................................................................. 50
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`X.
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`CONCLUSION .............................................................................................. 51
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`CERTIFICATE OF SERVICE
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`CERTIFICATE OF COMPLIANCE WITH 37 C.F. R. § 42.24
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`PETITIONER’S EXHIBIT LIST
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`Exhibit Description
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`1001
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`U.S. Patent No. 7,256,486 (“’486 patent”)
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`1002
`
`Prosecution History of U.S. Patent No. 7,256,486 (“Prosecution
`History”)
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`1003
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`Declaration of Eric Bretschneider, PhD
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`1004
`
`Modern Dictionary of Electronics (7th ed. 1999)) pg. 239 and 467
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`1005
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`Microchip Fabrication (4th ed. 2000) pg. 396
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`1006
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`Pecht et al. “Plastic Encapsulated Microelectronics” (1995) pg. 459
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`1007
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`Merriam Webster’s Collegiate Dictionary (10th ed. 1997) pg. 730
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`1008
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`1009
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`Japanese Patent Application Publication No. 2003-17754, English
`translation of Japanese Patent Application Publication No. 2003-17754
`and Translator Declaration (Rohm)
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`Japanese Patent Application Publication No. 2001-352102 English
`translation of Japanese Patent Application Publication No. 2001-
`352102 and Translator Declaration (Matsushita)
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`1010
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`U.S. Patent No. 5,376,580 (“Kish”)
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`1011
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`U.S. Patent No. 5,523,589 (“Edmond 589)
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`1012
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`U.S. Patent No. 6,791,119 (”Slater”)
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`1013
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`U.S. Patent No. 5,416,342 (“Edmond 342”)
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`1014
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`CV of Eric Bretschneider, PhD
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`1015
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`Pecht, M., R. Agarwal, P. McCluskey, T. Dishongh, S. Javadpour, and
`R. Mahajan, Electronic Packaging Materials and their Properties,
`CRC Press, Boca Raton, FL, 1999 pg. 37 (“Electronic Packaging”)
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`iii
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`I.
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`
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`INTRODUCTION
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`On behalf of Everlight Electronics Co., Ltd. ( “Petitioner”) and in accordance
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`with 35 U.S.C. § 311 and 37 C.F.R. § 42.100, inter partes review of claims 1-3 of
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`United States Patent No. 7,256,486 to Lee et al., entitled “Packaging Device For
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`Semiconductor Die, Semiconductor Device Incorporating Same And Method Of
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`Making Same” (hereinafter “the ’486 patent”) is requested. This Petition establishes
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`that Petitioner has a reasonable likelihood of prevailing with respect to at least one
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`of claims 1-3. A copy of the ’486 patent is provided as Ex. 1001.
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`II. REQUIREMENTS FOR AN INTER PARTES REVIEW PETITION
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`A.
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`Grounds for Standing (37 C.F.R. § 42.104(a))
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`Petitioner certifies that the ’486 patent is available for inter partes review and
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`that Petitioner and the Real Parties in Interest are not barred or estopped from
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`requesting an inter partes review challenging claims 1-3 of the ’486 patent on the
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`grounds identified herein.
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`B. Notice of Lead and Backup Counsel and Service Information (37
`C.F.R. § 42.8(b)(3))
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`Lead Counsel:
`John F. Rabena (Reg. No. 38,584)
`j r a b e n a @ s u g h r u e . c o m
`2100 Pennsylvania Ave., N.W.
`Suite 800
`Washington, DC 200037
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`Backup Counsel:
`William H. Mandir (Reg. No. 32,156 )
`wmandir@sughrue.com
`2100 Pennsylvania Ave., N.W.
`Suite 800
`Washington, DC 200037
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`1
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`C.
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`Notice of Real-Parties-in-Interest (37 C.F.R. § 42.8(b)(1))
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`Everlight Electronics Co., Ltd. and Everlight Americas, Inc.
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`D.
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`Notice of Related Matters (37 C.F.R. § 42.8(b)(2))
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`Based on the information known to Petitioner, the following matters are
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`related: Document Security Systems, Inc. v. Seoul Semiconductor Co. Ltd., No. 8:17-
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`cv-00981 (C.D. Cal.); Document Security Systems, Inc. v. Cree, Inc., No. 2:17-cv-
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`04263 (C.D. Cal.); Document Security Systems, Inc. v. Everlight Electronics Co.,
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`Ltd. et al., No. 2:17-cv-04273 (C.D. Cal.); Document Security Systems, Inc. v. Lite-
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`On, Inc., No. 2:17-cv-06050 (C.D. Cal.) ; and Document Security Systems, Inc. v.
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`Nichia Corporation et al, No. 2:17-cv-08849(C.D. Cal.)
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`In addition, this Petition is substantively identical to the Petition in IPR2018-
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`00333 filed by Seoul Semiconductor Co. Ltd. ("SSC's IPR").
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`E.
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`Fee for Inter Partes Review
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`The Director is authorized to charge any extra fee specified by 37 CFR §
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`42.15(a) to Deposit Account No. 19-4880.
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`F.
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`Proof of Service
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`2
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`Proof of service of this petition is provided in Attachment A.
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`III.
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`IDENTIFICATION OF CLAIMS BEING CHALLENGED
`(§ 42.104(B))
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`• Ground 1: Claims 1-3 Are Rendered Obvious by Rohm alone or in
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`view of Kish; and
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`• Ground 2: Claims 1-3 Are Rendered Obvious by Matsushita in view
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`of Edmond 589.
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`IV. THE PURPORTED INVENTION
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`A.
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`The Background of the Invention
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`The ’486 patent has an earliest U.S. filing date of June 27, 2003. The patent
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`begins with a description of “conventional” semiconductor packaging technology
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`based on a metal lead frame. Ex. 1001 (’486 patent) 1:17-20. The ’486 patent
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`describes that conventional technology as follows:
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`A metallization layer of aluminum located on the bottom surface of the
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`semiconductor die is bonded to a conductive surface that forms part of
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`the lead frame to attach and electrically connect the die to the lead
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`frame. Additionally, electrical connections are made between bonding
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`pads on the top surface of the die and other leads of the lead frame to
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`provide additional electrical connections to the die. The lead frame and
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`semiconductor die are then encapsulated to complete the semiconductor
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`device. The packaging device protects the semiconductor die and
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`provides electrical and mechanical connections to the die that are
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`compatible with conventional printed circuit board assembly processes.
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`Id. at 1:20-32. The bonding described in the above passage is described as “a silver
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`epoxy adhesive that cures at a relatively low temperature, typically about 120° C.”
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`Id. at 1:35-36. According to the ’486 patent, this conventional packaging technology
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`possessed insufficient packing density. Id. at 1:39-45. In other words, the final
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`packaged products were too large.
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`As an alternative to the conventional aluminum metallization, the ’486 patent
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`explains that “[r]ecently, semiconductor die having a substrate surface metallization
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`layer of a gold-tin alloy (80% Au:20% Sn approximately) have been introduced in
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`light-emitting devices.” The use of this “gold-tin eutectic” requires higher
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`temperature processing because it “has a melting point of about 280° C.” This prior
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`art technology was identified as having its own shortcomings, in that the high
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`temperature required was “incompatible with the materials of many conventional
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`packaging devices.” Id. at 1:61-63.
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`B.
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`The Purported Solution
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`The link between the prior art shortcomings and the purported invention is a
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`bit tenuous. In particular, nothing in the detailed description nor the claims limit the
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`purported invention to specific package materials. Instead, the focus of the
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`disclosure is on providing a planar substrate 110 (colored red) having four metal
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`layers regions thereon. Figures 1A and 1B (reproduced respectively top and bottom
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`below) show the substrate, the mounting pad 130 (colored green), the bonding pad
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`4
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`132 (colored green), the connecting pad 140 (colored orange) and the connecting pad
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`142 (colored orange). Ex. 1001 (’486 patent) 3:36-41. The mounting pad is used to
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`mount and electrically connect to the bottom surface of a semiconductor device (e.g.,
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`an LED). Id. at 5:10-12. The bonding pad 132 is used to electrically connect to the
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`top surface of the semiconductor device. Id. at 5:15-17. In addition, interconnecting
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`elements 120 and 122 (colored purple) are provided to electrically connect the
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`mounting pad and the bonding pad to the connecting pads 140 and 142 (colored
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`orange) on the bottom of the substrate. Id. at 3:58-67.
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`V.
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`SUMMARY OF THE RELEVANT PROSECUTION HISTORY
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`A copy of the file history as accessed from PAIR is provided as Exhibit 1002.
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`The ’486 patent as originally filed included 20 claims. All of the originally
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`filed claims were cancelled during prosecution. Original claim 1 provided:
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`1. A packaging device for semiconductor die, the packaging device
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`comprising:
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`a substantially planar substrate having opposed major surfaces;
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`a conductive mounting pad located on one of the major
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`surfaces;
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`a conductive connecting pad located on the other of the major
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`surfaces; and
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`a conductive interconnecting element extending through the
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`substrate and electrically interconnecting the mounting pad and the
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`connecting pad.
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`Id. at 249.
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`On August 23, 2004, the Examiner rejected all of the pending claims based on
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`anticipation and/or obviousness. Id. at 219-24. In particular, the Examiner rejected a
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`number of claims as anticipated based on U.S. Patent No. 5,986,885 to Wyland
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`(“Wyland”). Id. at 219. In response to the rejection, the applicants amended claim 1
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`and sought to distinguish between a “mounting pad” as recited and “first circuitry
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`metallizations 61 by flip-chip bonding” as allegedly disclosed in Wyland. Id. at 204.
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`Following a long series of rejections and amendments, the applicants
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`submitted a final amendment to application claim 22, which became patent claim 1:
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`22. (Currently amended) A semiconductor device, comprising:
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`a substantially planar substrate having opposed major surfaces;
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`an electrically conductive mounting pad located on one of the major
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`surfaces of the substrate;
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`The semiconductor device of claim 21 wherein the
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`semiconductor die comprises a light emitting diode (LED) having a
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`metallized bottom major surface that is mounted on the electrically
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`conductive mounting pad, and the metallized bottom major surface
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`comprises comprising one of an anode and a cathode of the LED;
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`a first electrically conductive connecting pad located on the
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`other of the major surfaces of the substrate; and
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`a first electrically conductive interconnecting element
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`extending through the substrate and electrically interconnecting the
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`mounting pad and the first electrically conductive connecting pad.
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`Id. at 80.
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`On April 4, 2007, the Examiner issued a Notice of Allowability. Id. at 24. In
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`the “Reasons For Allowance” attached to the Notice, the Examiner explained “[t]he
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`device structure as set forth in the claims is not taught or suggested in the prior art,
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`including more specifically the light emitting diode having metallized bottom
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`surface, mounted on a mounting pad, and having the relationship to the
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`interconnecting element and conductive connecting pad as set forth in claim 1.” Id.
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`at 25.
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`VI. CLAIM CONSTRUCTION
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`Because the ’486 patent has not expired, the Board applies the “broadest
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`reasonable construction in light of the specification.” 37 C.F.R. § 42.100(b); see also
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`Cuozzo Speed Techs. LLC v. Lee, 136 S. Ct. 2131, 2144-46 (2016). This claim
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`construction standard is different from, and broader than, that applied in district
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`court. Versata Dev. Grp., Inc. v. SAP Am., Inc., 793 F.3d 1306, 1327-28 (Fed. Cir.
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`2015).1
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`A.
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`“metallized . . . surface”
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`The term “metallized . . . surface” is not expressly defined in either the
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`specification of the ’486 patent or its prosecution history. The first use of the term in
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`the ’486 patent comes in the “Background of the Invention” section, where the
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`patent explains “[o]ne type of packaging device widely used in the industry includes
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`a metal lead frame. A metallization layer of aluminum located on the bottom surface
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`of the semiconductor die is bonded to a conductive surface that forms part of the
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`lead frame to attach and electrically connect the die to the lead frame.” Ex. 1001
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`1 Petitioner does not concede that the meaning of any claim term is as broad
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`under the Philips standard as under the broadest reasonable interpretation standard.
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`Petitioner reserves the right to argue for alternative and narrower definitions in
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`district court.
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`(’486 patent) 1:19-23 (emphasis added). The second usage also comes from the
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`Background section, stating “[r]ecently, semiconductor die having a substrate
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`surface metallization layer of a gold-tin alloy (80% Au:20% Sn approximately) have
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`been introduced in light-emitting devices.” Id. at 1:49-51 (emphasis added).
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`Similar to this description of the prior art, the Detailed Description begins
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`with the explanation that “[i]n the example shown, semiconductor die 250 embodies
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`a light-emitting diode and has anode and cathode electrodes (not shown) covering at
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`least parts of its opposed major surfaces.” Id. at 5:7-10. As the above quote suggests,
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`the patent discloses that the top and bottom surfaces comprise electrodes. It appears,
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`therefore, that the ’486 patent uses the terms electrode and metallized surface
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`somewhat interchangeably. That conclusion is further supported by the following
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`explanation:
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`The bonding pad on the top major surface of semiconductor die 250 is
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`typically part of or connected to the anode electrode of the light-
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`emitting diode. The metallization on the bottom major surface of
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`semiconductor die 250 typically constitutes the cathode electrode of
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`the light-emitting diode.
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`Id. at 5:18-22 (emphasis added); see also id. at 5:10-12 (“Semiconductor die 250 is
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`mounted on packaging device 100 with the metallization on its bottom major surface
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`attached to mounting pad 130.”).
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`Consistent with the use of the term metallized surface in the specification,
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`therefore, Petitioner asserts that the broadest reasonable construction is a metal layer
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`on at least a portion of the surface.
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`This interpretation is supported, for example, by Ex. 1004 (Modern Dictionary
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`of Electronics (7th ed. 1999)), which defines metallization in relevant part as “[a]
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`film pattern (single or multilayer) of conductive material deposited onto a substrate
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`to interconnect electronic components, or the metal film on the bonding area of a
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`substrate that becomes part of the bond and performs both electrical and mechanical
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`functions.” Id. at 467 (emphasis added); see also Ex. 1005 Microchip Fabrication
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`(4th ed. 2000) 396 (“The most common and familiar use of metal films in
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`semiconductor technology is for surface wiring. The materials, methods, and
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`processes of ‘wiring’ the components parts together is generally referred to as
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`metallization or the metallization process.”); Ex. 1006 (Plastic-Encapsulated
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`Microelectronics (1995)) 459 (“METALLIZATION: A deposited or plated thin
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`metallic film used for its protective or electrical properties.”); Ex. 1007 (Merriam
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`Webster’s Collegiate Dictionary (10th ed.)) 730 (“metallize . . . to coat, treat, or
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`combined with metal.”). All of these definitions suggest metallized surface is a
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`broad technical term and are consistent with Petitioner's proposed construction a
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`thin layer of metal on at least a portion of the surface.
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`B.
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`“the metallized top major surface comprises a first electrode . . .
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`and the metallized bottom major surface comprises a second
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`electrode”
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`The term electrode appears in claim 3 of the ’486 as follows “the metallized
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`top major surface comprises a first electrode of the LED and the metallized bottom
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`major surface comprises a second electrode of the LED.” Thus, claim 3 refers back
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`to the previously recited metallized top major surface of claim 2 and the metallized
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`bottom major surface of claim 1 for antecedent basis. More specifically, claim 3
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`further defines the previously recited structures from claims 1 and 2 to require that
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`those structures each “comprises an electrode.” As discussed in the previous
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`subsection, the broadest reasonable construction of the term metallized surface
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`means a metal layer on at least a portion of the surface. The “electrode” recitations
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`of claim 3, therefore require the previously recited metallized surfaces to comprise
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`electrodes.
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`The term “electrode” is not expressly defined in either the specification of the
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`’486 patent or its prosecution history. The first use of the term in the ’486 patent
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`comes with respect to figures 1A-1F, with the explanation that “[i]n the example
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`shown, semiconductor die 250 embodies a light-emitting diode and has anode and
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`cathode electrodes (not shown) covering at least parts of its opposed major
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`surfaces.” Ex. 1001 (’486 patent) 5:7-10 (emphasis added). Although not shown in
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`the figures, the patent explains that “[t]he bonding pad on the top major surface of
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`11
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`semiconductor die 250 is typically part of or connected to the anode electrode of the
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`light-emitting diode. The metallization on the bottom major surface of
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`semiconductor die 250 typically constitutes the cathode electrode of the light-
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`emitting diode.” Id. at 5:18-23 (emphasis added).
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`Petitioner, therefore, asserts that the broadest reasonable construction of “the
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`metallized top major surface comprises a first electrode . . . and the metallized
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`bottom major surface comprises a second electrode” means that the metallized
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`surfaces comprise electrical contacts to the LED.
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`This interpretation is supported, for example, by Ex. 1004 (Modern Dictionary
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`of Electronics (7th ed. 1999)), which defines electrode in relevant part as “[t]hat part
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`of a semiconductor device providing the electrical contact between the specified
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`region of the device and the lead to its terminal.” Id. at 239; see also Ex. 1006
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`(Plastic-Encapsulated Microelectronics (1995)) 453 (“ELECTRODES: The
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`conductor or conductor lands of an electronic device.”); Ex. 1007 (Merriam
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`Webster’s Collegiate Dictionary (10th ed.)) 730 (“electrode . . . a conductor used to
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`establish electrical contact with a nonmetallic part of a circuit”). All of these
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`definitions suggest electrode is a broad term and are consistent with Petitioner’s
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`proposed construction the metallized surfaces comprise electrical contacts to the
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`LED.
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`12
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`VII. PERSON HAVING ORDINARY SKILL IN THE ART
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`As explained in M.P.E.P. § 2141.03, a number of factors may be considered in
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`determining the proper level of skill:
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`The person of ordinary skill in the art is a hypothetical person who is
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`presumed to have known the relevant art at the time of the invention.
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`Factors that may be considered in determining the level of ordinary
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`skill in the art may include: (A) “type of problems encountered in the
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`art;” (B) “prior art solutions to those problems;” (C) “rapidity with
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`which innovations are made;” (D) “sophistication of the technology;
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`and” (E) “educational level of active workers in the field. In a given
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`case, every factor may not be present, and one or more factors may
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`predominate.”
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`A person of ordinary skill in the art at the time of the purported invention would
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`have had at least a B.S. in mechanical or electrical engineering or a related field, and
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`two years’ experience designing LED packages. Ex. 1003 (Bretschneider) ¶¶ 29-31.
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`This description is approximate, and a higher level of education or skill might make
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`up for less experience, and vice-versa. Id. For example, a M.S. in the above fields
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`and two years’ experience would suffice. Id.
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`VIII. BRIEF DESCRIPTION OF THE PRIOR ART
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`
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`A.
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`Japanese Patent Application Publication No. 2003-17754 (Rohm)
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`Japanese Patent Application Publication No. 2003-17754 (“Rohm”) is entitled
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`“Surface Mount Type Semiconductor Device.” Ex. 1008 (Rohm). Rohm, which was
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`not of record during the prosecution of the ’486 patent, was published on January 17,
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`2003, which is prior to the filing date of the ’486 patent. Rohm, therefore, is prior art
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`against the ’486 patent under pre-AIA 35 U.S.C. § 102(a).
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`As will be apparent throughout this Petition, the invention disclosed and
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`claimed in Rohm is, for all relevant purposes, indistinguishable from the purported
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`invention claimed in the ’486 patent.
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`Figure 1 of Rohm (reproduced and colored below) shows a semiconductor
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`device. The device includes a substantially planar substrate 12 (colored red) with top
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`and bottom major surfaces. Ex. 1008 (Rohm) Abstract, Claim 1, ¶13, ¶14. The top
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`surface is depicted in figure 1(B) and the bottom surface is shown in figure 2.
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`14
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`Four metal conductors are provided on the substrate 12 as shown in figure 1.
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`An electrically conductive mounting pad (die bonding electrode 18, colored green) is
`
`shown on the left side of the top major surface of substrate 12. Ex. 1008 (Rohm)
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`Abstract, Claim 1, ¶14, ¶23. An electrically conductive bonding pad (wire bonding
`
`electrode 20, also colored green) is shown on the right side of the top major surface
`
`of substrate 12. Ex. 1008 (Rohm) ¶14, Abstract, Claim 1, ¶1, ¶7, ¶9, ¶14. A pair of
`
`conductive pads (surface mount electrodes 22 and 24, colored orange) are provided
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`on the bottom major surface of the substrate 12 and are connected to the mounting
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`pad 18 and the bonding pad 20 respectively via interconnecting elements
`
`(connection electrodes 26 and 28, colored purple). Ex. 1008 (Rohm) Claim 1, ¶7,
`
`¶15, ¶19.
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`Figure 1 also shows an LED chip 30 (colored blue). A front surface electrode
`
`30a (colored violet) is shown on the top surface of LED 30 and is connected via wire
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`32 (colored yellow) to bonding pad 20. Ex. 1008 (Rohm) Claim 1, ¶7 ¶16. In
`
`addition, although not shown in figure 1, LED chip 30 has a “bottom surface
`
`electrode” on its bottom major surface that is electrically connected to the
`
`electrically conductive mounting pad. Ex. 1008 (Rohm) ¶16.
`
`B.
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`Japanese Patent Application Publication No. 2001-352102
`(Matsushita)
`
`Japanese Patent Application Publication No. 2001-352102 (“Matsushita”) is
`
`entitled “Optical Semiconductor Device.” Ex. 1009 (Matsushita). Matsushita,
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`15
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`which was not of record during the prosecution of the ’486 patent, was published on
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`December 21, 2001, more than one year prior to the filing date of the ’486 patent on
`
`June 27, 2003. Matsushita, therefore, is prior art against the ’486 patent under pre-
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`AIA 35 U.S.C. §§ 102(a) and (b).
`
`Here again, as with Rohm, Matsushita is, for all relevant purposes,
`
`indistinguishable from the purported invention claimed in the ’486 patent.
`
`Figure 2 of Matsushita (reproduced and colored below) shows a
`
`semiconductor device. The device includes a substantially planar substrate 1
`
`(colored red) with top and bottom major surfaces. Ex. 1009 (Matsushita) Abstract,
`
`Claim 1, ¶7, ¶12. The the top surface is depicted in figure 1.
`
`Four metal conductors are provided on the substrate 1 as shown in figure 2.
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`An electrically conductive mounting pad comprised of the upper portion of electrode
`
`3 (colored green) is shown on the left side of the top major surface of substrate 1.
`
`
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`16
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`Ex. 1009 (Matsushita) Abstract, Claim 1, ¶7, ¶13. An electrically conductive
`
`bonding pad (also colored green) comprised of the upper portion of electrode 2 is
`
`shown on the right side of the top major surface of substrate 1. Ex. 1009
`
`(Matsushita) Abstract, Claim 1, ¶7, ¶12. A pair of conductive pads (colored orange)
`
`are comprised respectively of the bottom portions of electrodes 2 and 3, and are
`
`provided on the bottom major surface of the substrate 1. Ex. 1009 (Matsushita)
`
`Abstract, ¶7, ¶9, ¶12. In addition, the upper and bottom portions of electrodes 2 and
`
`3 are interconnected by a pair of electrically conductive interconnect elements
`
`(colored purple). Ex. 1009 (Matsushita) Abstract, ¶7, ¶9, ¶12.
`
`C. U.S. Patent No. 5,376,580 to Kish et al. (“Kish”)
`
`U.S. Patent No. 5,376,580 (“Kish”) is entitled “Wafer Bonding of Light
`
`Emitting Diode Layers.” Ex. 1010. Kish, which was not of record during the
`
`prosecution of the ’486 patent, issued on December 27, 1994, more than one year
`
`prior to the filing date of the ’486 patent. Kish, therefore, is prior art against the ’486
`
`patent under pre-AIA 35 U.S.C. §§ 102(a), (b), and (e).
`
`
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`17
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`Kish discloses a variety of vertical LEDs in which one metal electrode is
`
`provided on the top surface and the other
`
`metal electrode is provided on the bottom
`
`surface. See, e.g., Ex. 1010 (Kish) Figs. 7,
`
`12, 14, 15; 7:48-55; 9:64-66; 10:53-55;
`
`13:30-33. In figure 14 (reproduced to the
`
`right) the metalized top and bottom surfaces are labeled 142 and 144 respectively.
`
`Id. at 7:48-55; 10:53-55; 13:30-33; see also id. at 9:64-10:1.
`
`D. U.S. Patent No. 5,523,589 to Edmond et al. (“Edmond 589”)
`
`U.S. Patent No. 5,523,589 (“Edmond 589”) is entitled “Vertical Geometry
`
`Light Emitting Diode with Group III Nitride Active Layer and Extended Lifetime.”
`
`Ex. 1011. Edmond 589, which was not of record during the prosecution of the ’486
`
`patent, issued on June 4, 1996, more than one year prior to the filing date of the ’486
`
`patent. Edmond 589, therefore, is prior art against the ’486 patent under pre-AIA 35
`
`U.S.C. §§ 102(a), (b), and (e).
`
`Edmond 589 discloses a vertical LED in which one contact is provided on the
`
`top surface and the other contact is provided on the bottom surface. Ex. 1011
`
`(Edmond 589) 5:9-12, 5:56-62; 7:67-8:5. In figure 1 (reproduced to the right) the
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`18
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`metalized top surface is labeled 30. Id. at 5:56-62 (“An ohmic contact 30 can be
`
`applied to the upper heterostructure
`
`layer 26 to complete the advantageous
`
`vertical structure of the invention.”).
`
`In addition, the metallized bottom
`
`surface comprises ohmic contract 22.
`
`Id. at 5:9-12. Edmond 589 also
`
`
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`
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`
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`discloses that the ohmic contacts “are each formed of a metal such as aluminum
`
`(Al), gold (Au), platinum (Pt), or nickel (Ni), but may be formed of other material
`
`for forming ohmic contacts as understood by those skilled in the art.”). Id. at 5:56-
`
`61.
`
`IX. PRECISE REASONS FOR THE RELIEF REQUESTED
`
`A. Ground 1: Claims 1-3 Are Rendered Obvious by Rohm alone or in
`view of Kish
`
`1. Independent Claim 1
`
`“1. A semiconductor device comprising”
`
`To the extent that the preamble is found to limit the claims, Rohm discloses
`
`“[a] semiconductor device.” Rohm discloses “a light-emitting device using an LED
`
`chip 30 in the example described above, [and] the present invention may also be
`
`applied to other light-emitting devices using semiconductor lasers or the like.” Ex.
`
`1008 (Rohm) ¶30, see also id. at Title (“Surface Mount Type Semiconductor
`
`19
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`

`

`Device”); Abstract, Claim 1, ¶1, ¶7; Ex. 1003 ¶52. “A surface mount type
`
`semiconductor light-emitting
`
`device (simply called “light-
`
`emitting device” hereinafter) 10
`
`of this example [is] illustrated
`
`in FIGS. 1 and 2.” Ex. 1008
`
`(Rohm) ¶13. Figure 1 is
`
`reproduced to the right.
`
`“[a] a substantially planar substrate having opposed major
`surfaces”
`
`Rohm discloses “an insulating substrate 12.” Ex. 1008 (Rohm) ¶13, see also
`
`id. at Abstract, Claim 1, ¶14; Ex.
`
`1003 ¶53. The substrate can be
`
`seen in figures 1 and 2. In figure
`
`1 (reproduced to the right), the
`
`planar substrate 12 (colored red)
`
`can be seen in
`
`cross-section. Ex. 1008 (Rohm) ¶17 (noting that “[t]he planar shape of the substrate
`
`12 is rectangular.”); Ex. 1003 ¶53. The planar substrate 12 has a first major surface
`
`on top, upon which the light-emitting type LED chip 30 is mounted. Ex.
`
`
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`20
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`1008 (Rohm) ¶16, ¶19; Ex. 1003 ¶53, ¶54. The planar substrate 12 also has a
`
`second major surface on the bottom, opposite the top surface. Id.
`
`“[b] an electrically conductive mounting pad located on one
`of the major surfaces of the substrate”
`
`Rohm discloses an electrically conductive mounting pad in the form of the
`
`“the die bonding electrode 18 to which the LED chip 30 is bonded.” Ex. 1008
`
`(Rohm) ¶23; see also id. at Abstract,
`
`Claim 1, ¶14; Ex. 1003 ¶54. This
`
`arrangement can be seen in figure 1
`
`(reproduced to the right), which
`
`depicts the die bonding electrode 18 (colored green), which corresponds to the
`
`claimed electrically conductive mounting pad located on the top major surface of the
`
`substrate. The mounting pad can also be
`
`seen in figure 2 (reproduced to the right). In
`
`addition, Rohm explains “[a] bottom surface
`
`electrode of this LED chip 30 and the die
`
`bonding electrode 18 are electrically
`
`connected.” Id. at ¶16; see also Ex. 1003
`
` ¶54. A person of ordinary skill would understand that the description of the
`
`structures are electrically connected indicates that the die bonding electrode 18 is
`
`
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`21
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`electrically conductive. Id. In addition, electrode 18 is electrically conductive
`
`because electrodes are electrically conductive. Id.
`
`“[c] a light emitting diode (LED) having a metallized bottom
`major surface that is mounted on the electrically conductive
`mounting pad, the metallized bottom major surface
`comprising one of an anode and a cathode of the LED”
`
`Rohm disclose