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`EVERLIGHT ELECTRONICS CO., LTD. ET AL.
`Exhibit 1009
`
`EVERLIGHT ELECTRONICS CO., LTD. ET AL.
`Exhibit 1009
`
`

`

`W2)001*352102(P2001i352102A)
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`EVERLKHTTELECTRONKXSCOgLTDQETAL.
`Exhflflt1009
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`EVERLIGHT ELECTRONICS CO., LTD. ET AL.
`Exhibit 1009
`
`

`

`5(3) 001*352102 (P2001i352102A)
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`Exhflflt1009
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`EVERLIGHT ELECTRONICS CO., LTD. ET AL.
`Exhibit 1009
`
`

`

`5(4) 001*352102 (P2001i352102A)
`
`
`
`EVERLIGHT ELECTRONICS CO., LTD. ET AL.
`Exhibit 1009
`
`EVERLIGHT ELECTRONICS CO., LTD. ET AL.
`Exhibit 1009
`
`

`

`
`
`(19) Japan Patent Office (JP)
`
`(12) Japanese Unexamined Patent
`Application Publication (A)
`
`
`(11) Japanese Unexamined Patent
`Application Publication Number
`2001-352102
`(P2001-352102A)
`(43) Publication date: December 21, 2001 (12.21.2001)
`Theme codes (reference)
`
`(51) Int. Cl.7
`
`Identification codes
`
` FI
`
`
`
`Request for examination: Not yet requested Number of claims: 1 OL (Total of 4 pages)
`
`(21) Application number
`
`
`(22) Date of application
`
`Japanese Patent Application
`2000-170140 (P2000-
`170140)
`June 7, 2000 (6.7.2000)
`
`
`
`
`
`
`
`
`
`(71) Applicant
`
`(72) Inventor
`
`000005821
`Matsushita Electric Industrial Co., Ltd.
`1006 Oaza Kadoma, Kadoma-shi, Osaka-fu
`Makoto NOZOE
`℅ Kagoshima Matsushita Electronics Co., Ltd.,
`1786-6 Aza Maedabira, Oaza Tokushige, Ijuin-
`cho, Hioki-gun, Kagoshima-ken
`100097445
`Patent Attorney Fumio IWAHASHI (and 2 others)
`F terms (reference)
`
`(74) Agent
`
`
`
`
`
`
`
`
`
`(54) (TITLE OF THE INVENTION) OPTICAL SEMICONDUCTOR DEVICE
`
`(57) (ABSTRACT)
`(PROBLEM) To provide an optical semiconductor device
`wherein burs of electrodes are not generated in a dicing
`process, the degree of bonding of a resin package is
`enhanced, and the disconnection of a wire for bonding can
`be prevented.
`(MEANS FOR SOLVING) Through-holes 1a and 1b are formed
`in two parts isolated from an outer edge of an insulating
`substrate 1, and a pair of electrodes 2 and 3 which have
`peripheral edges inside the outer edge of the substrate 1 are
`formed from the front surface side to the back surface side
`of the substrate 1 via the through-holes 1a and 1b. A
`semiconductor light-emitting element 4 is conductively
`mounted on the electrode 3 and bonded to the other
`electrode 2 with a wire 6, and a resin package 7 which is
`bonded to the entire front surface of the substrate 1 and
`seals the semiconductor light-emitting element and the wire
`6 is formed.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`EVERLIGHT ELECTRONICS CO., LTD. ET AL.
`Exhibit 1009
`
`

`

`
`
`(2)
`
`[001]-352102 (P2001-352102A)
`
`(SCOPE OF THE PATENT CLAIMS)
`(CLAIM 1) An optical semiconductor device fabricated by
`forming through-holes in two parts isolated from an outer
`edge of an insulating substrate; forming a pair of electrodes
`having peripheral edges inside the outer edge of the
`substrate from a front surface side to a back surface side of
`the substrate via the through-holes; conductively mounting
`an element on one of the pair of electrodes and bonding the
`element to the other electrode with a wire; and forming a
`resin package bonded to the entire front surface of the
`substrate and sealing the element and the wire.
`(DETAILED DESCRIPTION OF THE INVENTION)
`(0001)
`(TECHNICAL FIELD OF THE INVENTION) The present invention
`relates to an optical semiconductor device such as a surface
`mount type chip LED (light-emitting diode) or the like, for
`example, and more particularly to a high-quality optical
`semiconductor device having a strong degree of bonding
`between a substrate and a sealing resin and having no
`electrode burrs.
`(0002)
`(CONVENTIONAL TECHNOLOGY) A surface mount type chip
`LED is conventionally known as one type of optical
`semiconductor device. This chip LED is prepared by
`forming an electrode pattern on an insulating substrate,
`conductively mounting and wire-bonding a semiconductor
`light-emitting element to the electrode pattern, integrally
`adhering a resin package for sealing the device including a
`wire to the substrate, and creating each product by dicing.
`In the simple unit of each chip LED after dicing, a pair of
`electrodes is positioned on both ends of the substrate, and a
`semiconductor
`light-emitting element
`is conductively
`mounted on one electrode and bonded to the other electrode
`with a wire. Alternatively, in the case of a device having
`two electrodes on a surface on the opposite side as a
`sapphire substrate, such as a semiconductor blue light-
`emitting
`element using
`a GaN-based
`compound
`semiconductor, both of these electrodes are wire-bonded to
`the pair of electrodes on the substrate side.
`(0003) A sealing resin fulfills a role of protecting the
`semiconductor light-emitting element and the wire and has
`the function of a lens for enhancing optical distribution, and
`it often used in a form which seals not only the substrate,
`but also the electrodes.
`(0004)
`(PROBLEM TO BE SOLVED BY THE INVENTION) However,
`when an electrode pattern is formed on an insulating
`substrate and diced, an electrode is formed along the end
`face of the substrate, so downward-facing burrs tend to be
`generated on the metal electrode. Therefore, a burr-removal
`step becomes necessary after dicing, which increases the
`number of steps. In addition, even if electrode burrs are
`removed by a burr-removal step, the substrate may be
`inclined with respect to the mounting surface at the time of
`surface mounting when this removal is not sufficient which
`may also cause a decrease in mounting precision.
`(0005) Further, although a resin package using an epoxy or
`the like has a good degree of bonding with the substrate,
`the degree of bonding with respect to a metal electrode
`surface is comparatively low. Therefore, an electrode
`positioned at an end of the substrate tends to peel away
`from the resin package, and the resin package may lift up
`
`
`
`
`from the surface of the substrate. Accordingly, the bonded
`wire tends to become separated and disconnected from the
`electrode, which is a substantial cause of decreases in yield.
`(0006) Therefore, an object of the present invention is to
`provide an optical semiconductor device wherein burs of
`electrodes are not generated in a dicing process, the degree
`of bonding of a resin package is enhanced, and the
`disconnection of a wire for bonding can be prevented.
`(0007)
`INVENTION) The present
`(MEANS FOR SOLVING THE
`invention is an optical semiconductor device fabricated by
`forming through-holes in two parts isolated from an outer
`edge of an insulating substrate; forming a pair of electrodes
`having peripheral edges inside the outer edge of the
`substrate from a front surface side to a back surface side of
`the substrate via the through-holes; conductively mounting
`an element on one of the pair of electrodes and bonding the
`element to the other electrode with a wire; and forming a
`resin package bonded to the entire front surface of the
`substrate and sealing the element and the wire.
`(0008) With the present invention, it is possible to obtain
`an optical semiconductor device wherein burs of electrodes
`are not generated in a dicing process, the degree of bonding
`of a resin package is enhanced, and the disconnection of a
`wire for bonding can be prevented.
`(0009)
`(EMBODIMENT OF THE INVENTION) The invention described
`in Claim 1 is an optical semiconductor device fabricated by
`forming through-holes in two parts isolated from an outer
`edge of an insulating substrate; forming a pair of electrodes
`having peripheral edges inside the outer edge of the
`substrate from a front surface side to a back surface side of
`the substrate via the through-holes; conductively mounting
`an element on one of the pair of electrodes and bonding the
`element to the other electrode with a wire; and forming a
`resin package bonded to the entire front surface of the
`substrate and sealing the element and the wire. This has the
`effect of preventing the generation of burrs of electrodes in
`the dicing process, ensuring the stable adhesion of the resin
`package to the substrate, and preventing the rising of the
`wire.
`(0010) An embodiment of the present invention will be
`described hereinafter with reference to the drawings.
`(0011) FIG. 1 is a plan view illustrating an optical
`semiconductor device of this embodiment as an example of
`a surface mount type semiconductor light-emitting element.
`FIG. 2 is a cross-sectional view alone line X-X’ in FIG. 1,
`and FIG. 3 is a bottom view.
`(0012) In the drawings, through-holes 1a and 1b having
`circular opening cross sections are formed in two parts of
`an insulating substrate 1, and electrodes 2 and 3 are formed
`in the portions of the through-holes 1a and 1b from the
`front surface side to the rear surface side of the substrate 1.
`These electrodes 2 and 3 are patterned on the insulating
`substrate 1 and are formed having a cross-sectional shape
`passing from the front surface of the substrate 1, through
`the through-holes 1a and 1b, and reaching the rear surface.
`As illustrated in FIG. 3, the electrodes 2 and 3 have a shape
`contained in a narrower range than the outer contour of the
`substrate 1 and are formed so as to be biased slightly
`inward from the outer contour of the substrate 1.
`(0013) A semiconductor
`light-emitting element 4
`
`
`is
`
`EVERLIGHT ELECTRONICS CO., LTD. ET AL.
`Exhibit 1009
`
`

`

`
`
`(3)
`
`[001]-352102 (P2001-352102A)
`
`conductively mounted on the electrode 3 via an Ag paste 5,
`and an electrode 4a on the top surface of the semiconductor
`light-emitting element 4 is bonded to the other electrode 2
`with a wire 6. The entire surface of the substrate 1,
`including the semiconductor light-emitting element 4 and
`the wire 6, is then sealed by a resin package 7 made of an
`epoxy.
`(0014) Note that the cylindrical portions of the electrodes 2
`and 3 formed in the portions of the through-holes 1a and 1b
`are filled with a reinforcing resin 8, and a solder resist 9 for
`insulation is formed on the bottom surface of the substrate
`1. Here, the filling of the resin 8 can be performed with the
`production method described in the specification proposed
`by the present applicant and filed as Japanese Patent
`Application No. H11-357253.
`the
`(0015)
`In
`the configuration described above,
`semiconductor
`light-emitting element
`is mounted by
`mounting the electrodes 2 and 3 in alignment with a wiring
`pattern of a printed wiring board and then soldering the
`electrodes. The semiconductor light-emitting element 4
`then emits light when the electricity is turned on, and light
`emission of uniform brightness is achieved from roughly
`the entire resin package 7.
`(0016) Here, in the present invention, the electrodes 2 and 3
`are formed so as to be biased inward from the outer contour
`of the substrate 1. Therefore, when the substrate 1 is diced
`after being sealed with the sealing resin forming the resin
`package 7, the electrodes 2 and 3 are isolated from the
`dicing surface, so a shearing force does not reach the
`electrodes 2 and 3. Accordingly, burrs are not generated in
`the electrodes 2 and 3 even after dicing, which eliminates
`the need for a burr-removing process and makes it possible
`to increase the precision of mounting to a printed wiring
`board.
`(0017) In addition, the resin package 7, including the
`surfaces of the metal electrodes 2 and 3, are bonded to the
`substrate 1, but the electrodes 2 and 3 are not positioned in
`the outer edge portion of the substrate 1. Therefore, the
`degree of adhesion between the metal electrodes 2 and 3
`and the resin is relatively weak, but the degree of adhesion
`with the substrate 1 such as a glass cloth base material
`becomes strong. Accordingly, the outer edge portion of the
`resin package 7 is also firmly joined with the substrate 1 so
`that it is difficult to peel, which enables the maintenance of
`
`
`stable bonding and makes it possible to prevent wire
`disconnection due to the rising of the wire 6.
`(0018) In this way, with the present invention, there is no
`generation of burrs in the electrodes 2 and 3 in the dicing
`process, and the resin package 7 and the substrate 1 are
`stably bonded, so the bonded state of the wire 6 is
`maintained,
`and
`the
`production
`yield
`increases
`substantially.
`(0019) Note that in the embodiment described above, a
`semiconductor light-emitting element was described, but
`the device may be, of course, an optical semiconductor
`device such as a photosensor provided with a light-
`receiving or light-emitting element, for example.
`(0020)
`(EFFECT OF THE INVENTION) With the present invention,
`there is no generation of electrode burrs in the dicing
`process, so a burr-removal process may be omitted, and the
`precision of mounting on a printed wiring board or the like
`can be enhanced. In addition, since the entire outer edge of
`the substrate corresponds to the junction surface of the
`resin package, the degree of bonding of the resin package
`can be stabilized so as to prevent peeling and to prevent the
`rising of the sealed wire, which makes it possible to
`enhance production yield.
`(BRIEF DESCRIPTION OF THE DRAWINGS)
`(FIG. 1) is a plan view illustrating an embodiment of the
`optical semiconductor device of the present invention as an
`optical semiconductor light-emitting device.
`the optical
`(FIG. 2)
`is a cross-sectional view of
`semiconductor light-emitting device along line X-X’ in
`FIG. 1.
`(FIG. 3) is a bottom view of the optical semiconductor
`light-emitting device.
`(EXPLANATION OF REFERENCES)
`1
`substrate
`1a, 1b
`through-holes
`2, 3, 4a electrodes
`4
`semiconductor light-emitting element
`5 Ag paste
`6 wire
`7
`resin package
`8
`resin
`9
`solder resist
`
`
`(FIG. 1)
`
`(FIG. 2)
`
`
`
`
`
`EVERLIGHT ELECTRONICS CO., LTD. ET AL.
`Exhibit 1009
`
`

`

`
`
`(4)
`
`(FIG. 3)
`
`[001]-352102 (P2001-352102A)
`
`
`
`
`
`EVERLIGHT ELECTRONICS CO., LTD. ET AL.
`Exhibit 1009
`
`

`

`Certification of Translation
`
`Translator‘s Declaration: 12/8/17
`
`I, Brian Toth, hereby declare:
`
`That I possess advanced knowledge of the Japanese and English languages. My qualifications
`are as follows:
`
`0 Over 18 years as a Japanese—English translator. focusing primarily on technical
`documents and patents
`o Bachelor's degree in Mathematics with a minor in Physics from the University of
`Louisville
`
`I hereby certify that l translated Japanese Unexamined Patent Application Publication Number
`JP2001352102A, from Japanese to English and that. to the best of my ability, my English
`translation, attached hereto, is a true and correct translation.
`
`I further certify that I am competent in both English and Japanese to render and certify such
`translation. I understand that willful false statements and the like are punishable by a fine or
`imprisonment, or both (18 U .S.C. 1001). I declare under penalty of perjury under the laws of
`the United States of America that all statements made herein of my own knowledge are true,
`and all statements made on information and belief are believed to be true.
`
`If called upon to testify at a deposition in connection to this translation, I will make myself
`available.
`
`Brian Toth
`
`m
`
`EVERLIGHT ELECTRONICS CO., LTD. ET AL.
`Exhibit 1009
`
`EVERLIGHT ELECTRONICS CO., LTD. ET AL.
`Exhibit 1009
`
`