The *1 book in the industry — now revised & updated!
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`v.; ^ | • The #1, easy-to-read, math-free introduction to
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`semiconductor processing
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`Perfect for training, teaching, & vo-tech
`programs
`
`Updated with new cleaning techniques, packing
`technologies, & fabrication methods
`
`F O U R T H E D I T I O N
`
`Microchip
`Fabrication
`
`A P r a c t i c a l G u i d e t o
`S E M I C O N D U C T O R P R O C E S S I N G
`
`P E T E R V A N Z A N T
`
`EVERLIGHT ELECTRONICS CO., LTD. ET AL.
`Exhibit 1005
`
`
`
`H
`
`€M
`
`Ks
`
`H£^^9 m
`
`v.; ^ | • The #1, easy-to-read, math-free introduction to
`•iPi
`semiconductor processing
`K j|
`•T'i •Wn
`Perfect for training, teaching, & vo-tech
`programs
`
`Updated with new cleaning techniques, packing
`technologies, & fabrication methods
`
`F O U R T H E D I T I O N
`
`Microchip
`Fabrication
`
`A P r a c t i c a l G u i d e t o
`S E M I C O N D U C T O R P R O C E S S I N G
`
`P E T E R V A N Z A N T
`
`EVERLIGHT ELECTRONICS CO., LTD. ET AL.
`Exhibit 1005
`
`
`
`'etworks
`
`tionary
`
`orking with 13-41
`
`Second Edition
`Second Edition
`
`nunications
`
`Edition
`Second Edition
`dition
`
`aications Handbook
`
`gn
`
`Systems, Second Edition
`
`on
`
`tion on these or any other
`es please call 1-800-262-4729.
`McGraw-Hill representative.
`
`Microchip
`Fabrication
`A Practical Guide to Semiconductor Process! ng
`
`Peter Van Zant
`
`Fourth Edition
`
`McGraw-Hill
`New York San Francisco Washington, D.C. Auckland
`Bogota
`Caracas Lisbon London Madrid
`Mexico City Milan
`New Delhi San Juan Singapore
`Montreal
`Sydney Tokyo Toronto
`
`,
`
`EVERLIGHT ELECTRONICS CO., LTD. ET AL.
`Exhibit 1005
`
`
`
`Library of Congress Cataloging-in-Publication Data
`Microchip fabrication : a practical guide to semiconductor processing / Peter Van
`Van Zant, Peter,
`Zant.—4th ed.
`cm.
`P-
`Includes bibliographical references and index.
`ISBN 0-07-135636-3
`1. Semiconductors—Design and construction.
`TK7871.85.V36 2000
`621.3815'2—dc21
`
`I. Title.
`
`00-02317
`
`McGraw-Hill
`A Division of The McGraw-HiU Companies
`
`m
`
`Copyright © 2000, 1997, 1984 by The McGraw-Hill Companies, Inc. All
`rights reserved. Printed in the United States of America, Except as
`permitted under the United States Copyright Act of 1976, no pai l of
`this publication may be reproduced or distributed in any form or by any
`ineana, or stored in a data base or retrieval system, without the prior
`written permission of the publisher.
`1 2 3 4 5 6 7 8 9 0 D O C / D O C 0 9 8 7 6 5 4 3 2 1 0
`
`ISBN 0-07-135636-3
`The sponsoring editor for this book was Stephen Chapman and the
`production supervisor was Sherri Souffrance. It was set in Century
`Schoolbook by Pro-Image Corporation.
`Printed and bound by R. R. Donnelley & Sons Company.
`This book is printed on recycled, acid-free paper containing
`a minimum of 50% recycled, de-inked fiber.
`
`0
`
`Information contained in this work has been obtained by The Mc
`Inc. ("Mc-Graw-HilD from sources be-
`Graw-Hill CompanieB,
`lieved to be reliublu. However, neither McGraw-Hill nor ils au
`thors guarantee the accuracy or complet eness of any information
`published herein, and neither McGraw-Hill nor its authors shall
`be responsible for any errors, omissions, or damages arising out
`of use of this information. This work is published with the un
`derstanding that McGraw-Hill and its authors are supplying in
`formation but are not atlempting to render engineering or other
`professional services. If sudi services are required, the assistance
`of an appropriate professional should be sought.
`
`EVERLIGHT ELECTRONICS CO., LTD. ET AL.
`Exhibit 1005
`
`
`
`Chapter 13
`
`Metallization
`
`Overview
`Fabrication of circuits is divided into two major segments. First the
`active and passive parts are fabricated in and on the wafer surface.
`These is called the Front End Of the Line or FEOL. In the Back End
`of the Line (or BEOL), the metal systems necessary to connect the
`devices and different layers are added to the chip. In this chapter the
`materials, specifications, and methods used to complete the metalli
`zation segment is presented along with other uses of metals in chip
`nianufacturing. Vacuum pumps, used in CVD, evaporation, ion im
`plant, and sputtering systems are explained at the end of the chapter.
`
`g
`
`Objectives
`Upon completion of this chapter', you should be able to.
`^ ^st the requirements of a material for use as a chip surface con
`ductor.
`Draw cross sections of single and multilayer metal schemes.
`Describe the purpose and operation of a thin-film fuse.
`4- Make a list of materials used in the metallization of semiconductor
`devices. Identify their specific use(s).
`5.
`Draw and identify the parts of a vacuum evaporator,
`«• D
`escribe the principle of sputtering.
`7' Draw and identify the parts of a sputtering system.
`Describe the principle and operation of oil diffusion, turbo and cry-
`0genic high-vacuum pumps.
`
`395
`
`EVERLIGHT ELECTRONICS CO., LTD. ET AL.
`Exhibit 1005
`
`
`
`N
`
`r
`
`396
`
`Chapter Thirteen
`
`Introduction
`The most common and familiar use of metal films in semiconductor
`technology is for surface wiring. The materials, methods, and Pro
`cesses of "wiring" the component parts together is generally referred
`to as metallization or the metallization process. Metallization includes
`all of the steps in the metallization sequence described in Chapter 5
`
`Conductors-Single Level Metal
`In the MSI era metallization was relatively straight forward (Pi
`g.
`13.1), requiring only a single level metal process. Small holes, called
`contact holes or contacts, are etched through the surface layers, to the
`device/circuit component parts. Following contact masking, a thin
`layer (10,000 to 15,000 A) of the conducting metal (mostly alumin
`uni
`or aluminum alloys) was deposited by vacuum evaporation, sputter
`ing, or CVD techniques over the entire wafer. The unwanted portions
`of this layer are removed by a conventional photomasking and etch
`procedure or by lift-off. This step leaves the surface covered with thin
`lines of the metal that are called leads, metal lines, or interconnects.
`Generally a heat-treatment step, called alloying, is performed after
`metal patterning to ensure good electrical contact between the metal
`and the wafer surface.
`Regardless of the structure, a metal system must meet the following
`criteria:
`
`Wafer with
`Doped Regions
`
`Pallerning:
`Contact
`Mask
`
`• Goo
`• Goo
`• Ease
`• Goot
`• Higl
`• Corr
`• Long
`• Capa
`• Unifc
`
`Conduc
`Increasi
`face, wh
`The an
`schemes
`it is expi
`two-met
`layer for
`
`M4
`
`M3
`
`r?
`
`3.
`Layering: Conducting
`Layer
`
`Figure 13.1 Metallization sequence.
`
`Patterning: Metal
`Mask
`
`*> '3f
`
`EVERLIGHT ELECTRONICS CO., LTD. ET AL.
`Exhibit 1005
`
`
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