UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`EVERLIGHT ELECTRONICS CO. LTD
`Petitioner
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`v.
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`DOCUMENT SECURITY SYSTEMS, INC.
`Patent Owner
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`U.S. Patent No. 7,256,486
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`DECLARATION OF ERIC BRETSCHNEIDER PH.D
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`REGARDING U. S. PATENT NO. 7,256,486
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`
`
`EVERLIGHT ELECTRONICS CO. LTD
`Petitioner
`
`v.
`
`DOCUMENT SECURITY SYSTEMS, INC.
`Patent Owner
`
`U.S. Patent No. 7,256,486
`
`
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`
`
`DECLARATION OF ERIC BRETSCHNEIDER PH.D
`
`REGARDING U. S. PATENT NO. 7,256,486
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`I.
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`INTRODUCTION
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`1.
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`I, Eric Bretschneider, of 2622 Westwind Drive, Corinth, TX
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`76210 have been retained by Sughrue Mion, PLLC on behalf of Everlight
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`Electronics Co. Ltd. to analyze U.S. Patent No. 7,256,486 (“the ’486
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`patent”) as well as certain prior art references, and what a person of
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`ordinary skill in the art related to packaging for semiconductor based light
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`emitting devices would have understood at the time the earliest
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`application underlying the ’486 Patent was filed.
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`2.
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`I am being compensated at my normal consulting rate of
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`$400 per hour. My compensation is in no way contingent on the outcome
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`of this case, or on the conclusions I reach. I have no financial interest in
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`any of the above parties.
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`3.
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`I was asked to review and opine on the documents filed and
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`positions taken in IPR2018-00333 filed by Seoul Semiconductor Co. Ltd
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`et al., ("the SSC IPR"), including the Declaration of Michael Pecht Ph.D.
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`and the exhibits cited therein.
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`4.
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`This report summarizes the opinions I have formed to date.
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`In general, as set forth below, I agree with most of the analysis and
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`conclusions of Dr. Pecht.
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`
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`2
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`5.
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`For the sake of efficiency, I have incorporated parts of Dr.
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`Pecht's analysis with which I agree, into this Declaration.
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`6.
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`I reserve the right to modify my opinions, if necessary, based
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`on further review and analysis of information that I receive subsequent to
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`the filing of this report, including in response to positions taken by
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`Document Security Systems, Inc. or its experts that I have not yet seen.
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`II. MY EXPERIENCE AND QUALIFICATIONS
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`7.
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`I have over 25 years of experience with lighting and LEDs,
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`including a comprehensive background on the full range of LED
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`production technologies including MOCVD hardware/process design,
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`LED chip fabrication, optical/thermal/mechanical design of LED
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`packages, phosphor conversion, and testing/reliability of LED packages
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`and LED fixtures.
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`8.
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`I am currently the Chief Technology Officer at EB Designs
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`& Technology. In that capacity, I am (among other things) responsible
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`for the design and development of solid-state lighting technologies for
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`clients ranging from startups to fortune 100 companies.
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`9.
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`I am also current a member and Chair of the University of
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`Florida Department of Chemical Engineering Advisory Board. I was the
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`inaugural Conference Chair for LED Measurements and Standards. I am
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`
`
`3
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`
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`also a member of a number of professional societies, including SPIE,
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`Materials Research Society, Illuminating Engineering Society. Inside
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`the Illuminating Engineering Society I am one of six members of the
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`Science Advisory Panel and I am the current Chair of Subcommittee S
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`which is responsible for all test and measurement standards related to
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`solid-state lighting.
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`10. Prior to my position at EB Designs & Technology, I served
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`as the Director of Engineering at HeathCo, LLC. In that capacity, I was
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`responsible for advanced technology/product development related to
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`solid-state lighting, sensors, notifications and control products.
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`11. Prior to my position as Director of Engineering at HeathCo,
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`I was positioned at the Elec-Tech International Co., Ltd., a multi-billion
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`dollar solid-state lighting startup company headquartered in mainland
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`China. There I held the concurrent positions of Chief Engineer, ETi
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`Lighting Research Institute and VP of Research and Development, ETi
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`Solid State Lighting. In this capacity, my responsibilities included
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`developing all technology and product roadmaps for markets in North
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`America, China, Europe, and Japan.
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`12.
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`In this role, I led and trained a staff of over 100 engineers,
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`technicians and designers in the methods and procedures for designing
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`4
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`solid-state lighting products. This included determining spectral content,
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`LED package reliability, thermal management, optical design, control
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`integration and electrical drive circuits. I also had technical
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`responsibility for LED die, package and light engine design for products
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`intended for the domestic Chinese market as well as markets in Japan,
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`North America and Europe.
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`13. Between 2004 and 2008, I was positioned at Toyoda Gosei
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`North America, where I was a sales manager and was the sole technical
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`support for Toyoda Gosei LED die and packages in the Western
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`Hemisphere. My responsibilities included managing and developing
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`LED die and package sales accounts in North America and Europe.
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`14.
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`In my role as technical support for the Western
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`Hemisphere, I provided knowledge and experience necessary for
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`customers to use LED die and packages. With respect for LED die, this
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`included aiding and supporting customers with optical and thermal
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`design of LED packages as well as phosphor conversion materials and
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`techniques. For LED packages, my responsibilities included testing
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`protocols, reliability evaluation, as well as thermal and optical design of
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`LED light engines and fixtures
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`15. Between 2003 and 2004, I was positioned at Beeman
`
`
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`5
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`
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`Lighting, where I was Director of Solid State Lighting Engineering, and
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`my responsibilities included leading development of solid state lighting
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`systems and materials.
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`16. Between 1998 and 2003 I held a position at Uniroyal
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`Optoelectronics, where I was Team Leader for the Epitaxial Growth and
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`Materials Characterization areas. I later held the position of Director of
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`Intellectual Property, University Relations and Government contracts.
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`From 1999 through 2003 I had a concurrent assignment as a Senior Epi
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`Scientist. Throughout these roles I supported all sales efforts for LED
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`die and package sales.
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`17. While at Uniroyal Optoelectronics, I had primary
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`responsibility for thermal and optical design of LED die and packages.
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`A part of my responsibility in supporting sales of LED die and packages
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`included thermal and optical design of packages for LED die customers
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`and thermal and optical modeling of LED modules and fixtures for LED
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`package customers.
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`18. My interactions with customers and potential customers
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`included design work on a number of projects that would still be
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`considered technically challenging today. The included exterior lighting
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`for the US Navy DDX (Stealth Destroyer) program, a lighting module
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`6
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`for the US Air Force for use on the XSS-11 satellite, an implantable light
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`source for the Paul Allen Foundation and linear chip on board (COB)
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`lighting modules for the Boeing 737. I also worked on an internal
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`project that developed a liquid based cooling system for LEDs that could
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`dissipate more than 20 Watts of heat per square millimeter which is an
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`order of magnitude greater heat flux than what is generated by current
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`state of the art LEDs.
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`19. Further, while working with a sister company (Norlux
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`Corporation), I also helped design the “Hex” which was one of the first
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`COB LED products released and which incorporated from
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`approximately 40 to well over 100 LED chips and operated with
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`electrical power input of 1 to 5 watts. I was also responsible for reverse
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`engineering and destructive testing of internal and competitive products.
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`20.
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`I have also authored and presented more than a total of 30
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`publications, presentations, and seminars, and I am a named inventor on
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`over 30 issued patents and over 25 pending patents.
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`21.
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`I earned my BSE in Chemical Engineering from Tulane
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`University in 1989. I earned a Ph.D. in Chemical Engineering from the
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`University of Florida in 1997.
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`22. My graduate work focused on development of
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`7
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`optoelectronic devices, including novel silicon based visible light LEDs,
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`sulfide based TFELD structures and ZnSe blue LEDs. My research
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`required optical and thermal package design and test development.
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`23. Based on the above education and experience, I believe that
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`I have a detailed understanding of the state of the art during the relevant
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`period, as well as significant experience with and a substantial
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`understanding of how persons of skill in the art at that time would
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`understand the technical issues in this case.
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`24. For more details about my experience and qualifications,
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`see my CV, Ex. 1014.
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`III. DESCRIPTION OF THE RELEVANT FIELD AND THE
`RELEVANT TIMEFRAME
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`25.
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`I have carefully reviewed the ’486 Patent. For convenience,
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`all of the information that I considered in arriving at my opinions is listed
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`in Appendix A.
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`26.
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`Based on my review of these materials, I believe that the
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`relevant field for purposes of the ’486 Patent is packaging of
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`semiconductor devices (die) and in particular semiconductor based light
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`emitting diodes (LED) semiconductor devices.
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`27.
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`I believe the relevant timeframe for my analysis is
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`8
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`approximately 2003, which is the year during which the ’486 Patent
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`was originally filed.
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`28. As described above, I have extensive experience in the
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`relevant field, including experience relating to the packaging of
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`semiconductor light emitting semiconductor die. Based on my
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`experience, I have an established understanding of the relevant field in
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`the relevant timeframe.
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`IV. THE PERSON OF ORDINARY SKILL IN THE RELEVANT
`FIELD IN THE RELEVANT TIMEFRAME
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`29.
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`I have been informed that “a person of ordinary skill in the
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`relevant field” is a hypothetical person to whom an expert in the relevant
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`field could assign a routine task with reasonable confidence that the task
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`would have been successfully carried out. I have been informed that
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`evidence of the level of ordinary skill in the art can be determined based
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`on information about the field including: the types of problems
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`encountered, known solutions, the speed of innovation, sophistication,
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`and the educational level of active workers. I have considered these types
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`of information along with my own background working with students and
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`other professionals in the field to reach my conclusion.
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`30.
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`It is my opinion that the person of ordinary skill in the art at
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`the relevant would have had at least Bachelor’s Degree in mechanical,
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`9
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`chemical or electrical engineering or an equivalent field and at least two
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`years of experience in the design of LED packages. A higher level of
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`education, such as a Master’s Degree, in the above fields, could
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`substitute for work experience and additional work experience could
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`substitute for a degree.
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`31. Based on my experience, I have an understanding of the
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`capabilities of a person of ordinary skill in the relevant field. I have
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`supervised, directed, and instructed many such persons over the course
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`of my career.
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`V. OVERVIEW OF THE ’486 PATENT AND STATE OF PRACTICE
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`32. A light emitting diode (LED) is a semiconductor device (also
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`called a semiconductor die or chip) that emits light when powered. To
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`protect the fragile semiconductor device and its connections, to aid in
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`thermal management of the relatively high heat that is generated, and to
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`aid in mounting the LED to a printed circuit board (PCB) or some other
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`assembly, the LED die is packaged. The packaging of semiconductor
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`devices is well known with a history of over 60 years.
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`33. The traditional LED package consists of the LED die, which
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`is mounted on a substrate (via a die bonding electrode), and electrically
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`connected and routed around the substrate via a metal trace on one side of
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`10
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`the substrate. The top of the die is connected to another electrode on the
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`substrate via a wire bond, which in turn is routed around the substrate to
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`the bottom of the substrate. The two (ground and power)1 parts of the
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`routing trace on the bottom side of the substrate, serve as pads for surface
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`mounting to a PCB, often with solder. The package is encapsulated with
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`an optically transparent material to protect the die and the wire bond from
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`moisture and mechanical damage (see Fig below showing a traditional
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`LED package surface mounted to a PCB).
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`34. The ‘486 Patent pertains to a semiconductor package (e.g.
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`packaging device (100)) where an LED semiconductor die (250) is
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`mounted on a substrate 110 (via die bonding electrode 130), and
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`electrically connected to the bottom of the substrate by plated through
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`holes (120 and 122). One plated through hole (120) electrically connects
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`1 Like a light bulb, only an electrical power and an electrical ground connection are
`needed
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`11
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`the die to ground and the other (122) connects the die to power via a wire
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`bond (254). The package is encapsulated with an optically transparent
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`material 252, and can be surface mounted to a PCB by terminals 140 and
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`142, with solder. (See Fig 2 of the ‘486 Patent below).
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`35. A key stated goal of the ‘486 Patent is to provide a
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`semiconductor packaging device that is smaller than the traditional
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`LED package (to find an alternative to the wrap-around leads) and thus
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`is comparable in volume with the semiconductor die and that is
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`compatible with conventional printed circuit board assembly processes.
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`Ex. 1001 (’486 patent) at 1:39-48.
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`VI. UNPATENTABILITY BASED ON PRIOR ART IN THE
`PRESENT PROCEEDINGS
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`36.
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`I am informed by counsel and understand that statutory and
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`judicially created standards must be considered to determine the validity
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`of a patent claim. I have reproduced the legal standards relevant to this
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`declaration below, as provided to me by counsel as I understand them.
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`37.
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`I understand that a patent claim is invalid if it is
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`12
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`anticipated or obvious.
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`38. Anticipation: I understand that for a patent claim to be
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`“anticipated” by the prior art, each and every limitation of the claim must
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`be found, expressly or inherently, in a single prior art reference as recited
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`in the claim. I understand a claim limitation not expressly found in a prior
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`art reference is inherent if the prior art necessarily functions in accordance
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`with, or includes, the claim limitation. Mere probability that a limitation is
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`included is not sufficient to establish inherency.
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`39. Obviousness: I understand that a patent claim is not
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`patentable for obviousness under 35 U.S.C. § 103 “if the differences
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`between the subject matter sought to be patented and the prior art are such
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`that the subject matter as a whole would have been obvious at the time the
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`invention was made to a person having ordinary skill in the art to which
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`said subject matter pertains.” 35 U.S.C. § 103. I understand that
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`obviousness may be based on one reference and/or a combination of
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`references. I understand that the combination of familiar elements
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`according to known methods is likely to be obvious when it does no more
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`than yield predictable results.
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`40.
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`I understand that when a patented invention is a combination
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`of known elements, the Board must determine whether there was an
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`13
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`apparent reason to combine the known elements in the fashion claimed
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`by the patent at issue by considering the teachings of prior art references,
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`the effects of demands known to people working in the field or present in
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`the marketplace, and the background knowledge possessed by a person
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`having ordinary skill in the art.
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`41.
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`I understand that a patent claim composed of several
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`limitations is not proven obvious merely by demonstrating that each
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`limitation was independently known in the prior art. I understand that
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`identifying a reason those elements would have been combined can be
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`important because inventions in many instances rely upon building blocks
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`long since uncovered, and claimed discoveries almost of necessity will be
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`combinations of what, in some sense, is already known. I understand that
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`it is improper to use hindsight in an obviousness analysis and that a
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`patent's claims should not be used as a “roadmap.”
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`42.
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`I also understand all prior art references are to be looked at
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`from the viewpoint of a person having ordinary skill in the art at the time
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`the invention was made.
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`43.
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`I understand that obviousness analysis requires consideration
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`of: (1) the scope and content of the prior art; (2) the differences between
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`the claims and the prior art; (3) the level of ordinary skill in the pertinent
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`14
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`art; and (4) any objective indicia of non-obviousness, such as commercial
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`success, long-felt but unresolved need, failure of others, industry
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`recognition, copying, and unexpected results.
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`44.
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`I understand that in order to prove that a claimed invention
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`is not patentable for obviousness, a petitioner must (1) identify the
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`differences between the claim and particular disclosures in the prior art
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`references, singly or in combination, (2) specifically explain how the
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`prior art references could have been combined in order to arrive at the
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`subject matter of the claimed invention, and (3) specifically explain why
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`a person having ordinary skill in the art would have had reasons to so
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`combine the prior art references.
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`A. GROUND 1: CLAIMS 1-3 ARE OBVIOUS BASED ON
`JAPANESE PATENT APPLICATION PUBLICATION
`NO. 2003-17754 (“ROHM”) ALONE OR IN VIEW OF
`U.S. PATENT NO. 5,376,580 (“KISH”)
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`45.
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`Japanese Patent Application Publication No. 2003-17754
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`(“Rohm”) is entitled “Surface Mount Type Semiconductor Device” and
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`pertains to a semiconductor, light-emitting device (LED) package. In
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`Rohm, an LED chip (die) 30 is mounted on substrate 12 (via a die bonding
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`electrode 18) and electrically connected to the bottom of the substrate by
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`plated through holes (14 and 16). Ex. 1008 (“Rohm”) Abstract, Claim 1,
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`¶13, ¶14; see id. Figure 1. One plated through hole (14 or 16) electrically
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`15
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`connects the LED chip to a relatively negative voltage and the other
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`connects the LED chip to a relatively positive voltage. The package is
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`encapsulated with an optically transparent material 34, and can be surface
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`mounted to a printed circuit board (PCB) via pads 42a and 42b. (See Rohm
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`Fig 1a below). Id ¶¶ 7, 15, 19. A key stated goal of Rohm is to provide a
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`semiconductor packaging device that is smaller than the traditional LED
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`package (to find an alternative to the wrap-around leads of the prior art).
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`46. An LED chip 30 is connected by a bottom electrode (not
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`
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`pictured in Figure 1) to mounting pad 18, and by wire 32 to bonding pad
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`20. Wire 32 is connected to LED chip 30 by an electrode 30a. Ex. 1008
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`(Rohm) ¶16. The LED is connected in a vertical arrangement, whereby
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`one of the top and bottom surface is connected to a relatively negative
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`voltage via a cathode connection and the other is connected to a relatively
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`positive voltage via an anode connection.
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`47. Metallization layers are frequently and commonly used to
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`provide electrodes (electrical connections) to the types of components
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`16
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`
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`disclosed by Rohm. See also Ex. 1001 (describing the metallization layer
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`as “background” to the ’486 patent). This is true as a matter of
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`convention—a metal electrode is a natural and obvious choice for a
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`conductive element in order to provide current to an LED.
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`48. For example, U.S. Patent No. 5,376,580 (“Kish”) discloses
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`a variety of LEDs with two electrodes—one on the top surface and one
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`on the bottom. See, e.g., Ex. 1010 (Kish) Figs. 7, 12, 14, 15, 7:48-55;
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`9:64-66; 10:53-55; 13:30-33. The patent states that these are “metallized
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`electrodes for applying voltage to LEDs,” id. at 5:19-21, and goes on to
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`describe that formation (of upper and lower metal electrodes) as
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`“standard.” Id. at 7:48-55; see also id. at 9:64-66; 10:53-55; 13:30-
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`Indeed, like the ’486 patent, Kish depicts an LED with metalized layer
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`electrodes at its top (142) and bottom (144) surfaces. See, e.g., Id. at
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`Figure 14, 7:48-55; 10:53-55; 13:30-33.
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`49. Moreover, U.S. Patent 6,791,119 (“Slater”) teaches that
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`metal electrodes are advantageous in the context of LEDs because metal
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`with a reflective surface reflects light that would otherwise be lost. Ex.
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`1012 (Slater) at 18:33-67. Rather than be absorbed into a mounting pad,
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`metalized layer electrodes reflect light back in the direction the device
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`intends to direct it.
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`17
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`50. Thus, an ordinarily skilled artisan would have considered it
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`well- known, even “standard,” that metallized layers could be used as
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`conductive electrodes to provide current to LEDs.
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`1.
`CLAIM 1
`51. Claim 1 recites:
`
`
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`
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`1. A semiconductor device, comprising:
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`[a] a substantially planar substrate having opposed major surfaces;
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`[b] an electrically conductive mounting pad located on one of the
`major surfaces of the substrate;
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`[c] a light emitting diode (LED) having a metallized bottom major
`surface that is mounted on the electrically conductive mounting
`pad, the metallized bottom major surface comprising one of an
`anode and a cathode of the LED;
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`[d] a first electrically conductive connecting pad located on the other
`of the major surfaces of the substrate; and
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`[e] a first electrically conductive interconnecting element extending
`through the substrate and electrically inter-connecting the mounting
`pad and the first electrically conductive connecting pad.
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`52. The preamble of claim 1 recites “[a] semiconductor device.”
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`Rohm, too, is directed to a semiconductor device. This is disclosed in the
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`title of Rohm “Surface Mount Type Semiconductor Device” as well as in
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`Claim 1, and paragraphs 1, 6, and 7.
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`53. The first element of claim 1 recites “a substantially planar
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`substrate having opposed major surfaces.” Figure 1 of Rohm shows a
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`18
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`
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`substantially planar substrate, which is disclosed as “an insulating
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`substrate 12.” Ex. 1008 (Rohm) ¶
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`13. The substantially planar substrate 12 has opposed major surfaces on its
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`top and bottom, as “[t]he planar shape of the substrate 12 is rectangular.”
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`Ex. 1008 (Rohm) ¶17. The planar substrate is also shown in figure 1 and is
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`described, for example, in the Abstract, Claim 1, and in paragraph 14.
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`54. The second element of claim 1 recites “an electrically
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`conductive mounting pad located on one of the major surfaces of the
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`substrate.” This limitation is encompassed in Rohm, which discloses a
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`“die bonding electrode 18 to which the LED chip 30 is bonded” sitting
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`atop substrate 12. Ex. 1008 (Rohm) ¶23; see also id. at Abstract,
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`Claim 1, ¶14. In Rohm, “a bottom surface electrode of LED chip 30” is
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`electrically connected to the die bonding electrode 18. Ex. 1008¶16.
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`Thus, because there must be an electrical current from the die to the
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`ground on the circuit board, die bonding electrode 18 (indeed all
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`electrodes) must be electrically conductive.
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`55. The third element of claim 1 recites “a light emitting diode
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`(LED) having a metallized bottom major surface that is mounted on the
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`electrically conductive mounting pad, the metalized bottom major
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`surface comprising one of an anode and a cathode of the LED.” This
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`
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`19
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`
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`element is echoed in Rohm which states that “[a] top surface light-
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`emitting type LED chip 30 is placed on and die-bonded to the top surface
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`of the die bonding electrode 18. A bottom surface electrode of this LED
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`chip 30 and the die bonding electrode 18 are electrically connected.” Ex.
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`1008 (Rohm) ¶16. Though Rohm does not actually state that the
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`electrode is a metalized layer, it would have been well known and
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`obvious to a person of ordinary skill in the art to use a metalized layer for
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`that purpose. See ¶¶ 47-49 above (discussing the Kish and Slater patents
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`and describing electrodes formed from metalized layers as “standard”).
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`In other words, LED chip 30 is electrically connected to die bonding
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`electrode 18 by the electrodes on each component. In an electrical
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`connection between two electrodes, one electrode is considered
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`positively charged (this is known as the cathode) and one electrode is
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`considered negatively charged (the anode). Thus, as in claim 1 of the
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`’486 patent, the metalized bottom major surface of the LED chip 30 in
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`Rohm functions as “one of an anode and a cathode of the LED.”
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`56. The fourth element of claim 1 recites “a first electrically
`
`conductive connecting pad located on the other of the major surfaces of
`
`the substrate.” Relative to the mounting pad, which is on top of the
`
`substrate the other major surface of the substrate is the bottom. So too for
`
`
`
`20
`
`
`
`Rohm, in which the die bonding electrode 18 is on top of the substrate,
`
`and a conductive connecting pad containing an electrode—“surface
`
`mount electrode 22”—is located underneath. Ex. 1008 (Rohm) Abstract,
`
`Claim 1; id. at ¶¶ 7, 14.
`
`57. The fifth element of claim 1 recites “a first electrically
`
`conductive interconnecting element extending through the substrate and
`
`electrically interconnecting the mounting pad and the first electrically
`
`conductive connecting pad.” Rohm discloses “a first connection
`
`electrode formed inside the first through- hole so as to electrically
`
`connect the die bonding electrode and the first surface mount electrode.”
`
`Ex. 1008 (Rohm) Claim 1; id. at ¶7; see also id. at ¶¶ 12, 15. As noted
`
`above, the die bonding electrode of Rohm is the mounting pad of the ’486
`
`patent—thus the “connection electrode” of Rohm electrically
`
`interconnects the semiconductor die to the mounting pad, to the through
`
`hole, and to the electrically conductive connecting pad on the bottom
`
`major surface of the substrate. In Rohm, as is the case with the ’486
`
`patent, this electrical path will enable the electrical connection to an
`
`external device (e.g., a PCB to which the package will be soldered).
`
`CLAIM 2
`2.
`58. Claim 2 recites:
`
`
`
`
`
`21
`
`
`
`2. The semiconductor device of claim 1, further comprising:
`
`[a] an electrically conductive bonding pad located on the one of
`the major surfaces of the substrate;
`
`[b] a bonding wire extending between a metallized top major
`surface of the LED and the electrically conductive bonding pad;
`
`[c] a second electrically conductive connecting pad located on the
`other of the major surfaces of the substrate; and
`
`[d] a second electrically conductive interconnecting element
`extending through the substrate and electrically interconnecting
`the bonding pad and the second connecting pad.
`
`
`59. The first element of claim 2 recites “an electrically
`
`conductive bonding pad located on the one of the major surfaces of the
`
`substrate.” Similarly, Rohm teaches a “wire bonding electrode 20 formed
`
`on the front surface of the substrate 12.” Ex. 1008 (Rohm) ¶14. From
`
`Figure 1, it is clear that this bonding electrode sits on the same surface of
`
`the substrate as the mounting pad/die bonding electrode 18. Id. at Figure
`
`1; see also Abstract, Claim 1, ¶¶1, 7, 9, 14. Because bonding electrode
`
`20 is an electrode, it is electrically conductive; thus, it meets the
`
`limitation of this element of claim 2.
`
`60. The second element of claim 2 recites “a bonding wire
`
`extending between a metallized top major surface of the LED and the
`
`electrically conductive bonding pad.” Rohm teaches that an electrode atop
`
`“the LED chip 30 and the wire bonding electrode 20 are wire-bonded with
`
`
`
`22
`
`
`
`a wire 32.” Ex. 1008 (Rohm) ¶16. In other words, Rohm discloses a wire
`
`extending from an electrode of the LED to an electrode of the bonding
`
`pad. Though Rohm does not explicitly state that the electrode atop the
`
`LED is a metalized surface, it would almost certainly be under
`
`conventional practice and obvious to a person of ordinary skill in the art.
`
`See ¶¶47- 49 (discussing the Kish and Slater patents and describing
`
`electrodes formed from metalized layers as “standard.”).
`
`61. The third element of claim 2 recites “a second electrically
`
`conductive connecting pad located on the other of the major surfaces of
`
`the substrate.” This element is in tandem with the fourth element of claim
`
`1, which recites “a first electrically conductive connecting pad . . .” Just
`
`as Rohm taught a corresponding “surface mount electrode 22,” see ¶56,
`
`it also teaches a “surface mount electrode 24,” on the bottom of the
`
`substrate which comprises the second electrically conductive connecting
`
`pad required by the ’486 patent. Ex. 1001 at Claim 1, ¶¶7, 14.
`
`62. The fourth element of claim 2 recites “a second electrically
`
`conductive interconnecting element extending through the substrate and
`
`electrically interconnecting the bonding pad and the second connecting
`
`pad.” Just as above, see ¶57, Rohm discloses “a second connection
`
`electrode formed inside the second through-hole so as to electrically
`
`
`
`23
`
`
`
`connect the wire bonding electrode and the second surface mount
`
`electrode.” Ex. 1008 (Rohm) Claim 1; id. at ¶7.
`
`CLAIM 3
`3.
`63. Claim 3 recites:
`
`
`
`
`
`3. The semiconductor device of claim 2 wherein the metallized
`top major surface comprises a first electrode of the LED and the
`metallized bottom major surface comprises a second electrode of
`the LED.
`64. Rohm discloses an “LED chip 30” having both front and
`
`bottom surface electrodes, which are by definition electrical contacts. It
`
`would have been obvious to a person having ordinary skill that these
`
`electrodes would have been metalized surfaces. See ¶¶45-47 (discussing
`
`the Kish and Slater patents and describing electrodes formed from
`
`metalized layers as “standard.”) see also Pecht, M., R. Agarwal, P.
`
`McCluskey, T. Dishongh, S. Javadpour, and R. Mahajan, Electronic
`
`Packaging Materials and their Properties, CRC Press, Boca Raton, FL,
`
`1999 at 37, Exhibit 1015 (Electronic Packaging) (stating that metalized
`
`layers are often used to prevent the oxidation of copper electrodes.).
`
`B. GROUND 2: CLAIMS 1-3 ARE OBVIOUS BASED
`ON JAPANESE PATENT APPLICATION
`PUBLICATION NO. 2001-352102 MATSUSHITA IN
`VIEW OF U.S. PATENT NO. 5,523,589 EDMOND
`589
`Japanese Patent Application Publication No. 2001-352102
`
`65.
`
`(“Matsushita”), titled “Optical Semiconductor Device” pertains to a
`
`24
`
`
`
`semiconductor, light-emitting device (LED) package. In this patent, an
`
`LED chip (die) 4 is mounted on substrate 1 (via a die bonding electrode
`
`3) and electrically connected to the bottom of the substrate by plated
`
`through holes (16 and 10). Ex. 1009 (Matsushita) Claim 1, ¶¶7, 12. One
`
`plated through hole (16) electrically connects the ground of the diode and
`
`the other (10) connects the power via a wire bond (6). Ex. 1009
`
`(Matsushita), Abstract, Claim 1, ¶¶7, 9, 12, 13. The package is
`
`encapsulated with an optically transparent material 7, and can be surface
`
`mounted to a PCB by the terminals located at the bottom of the substrate,
`
`with solder. Ex. 1009 (Matsushita) Figure 1a, below. A key stated goal of
`
`the ‘102 Patent is to provide a semiconductor packaging device that
`
`removes the impediments of the traditional LED package (to find an
`
`alternative to the wrap-around leads).
`
`66. U.S. Patent No. 5,523,589 (“Edmond ’589”) relates to a
`
`
`
`“Vertical Geometry Light Emitting Diode with Group III Nitride Active
`
`25
`
`
`
`
`
`
`
`Layer and Extended Lifetime.” Ex. 1011 (Edmond ’589). The patent
`
`discloses an LED on which metallized layers at the top and bottom
`
`surfaces form contacts. Ex. 1011 (Edmond ’589) Figure 1, 5:9-12, 5:56-62;
`
`7:67-8:5. The metalized surfaces are “ohmic contacts,” which are “each
`
`formed of a metal such as aluminum (Al), gold (Au), platinum (Pt), or
`
`nickel, (Ni), but may be formed of other material for forming ohmic
`
`contacts as understood by those skilled in the art.” Id. at 5:56-61. The
`
`ohmic layers disclosed by Edmond ’589 are conductive.
`
`67. Ex. 1011 (Edmond ’589) is a vertical LED, and the patent
`
`discloses several advantages of its design over the prior art, including the
`
`ability to emit in the blue and ultraviolet portions of the electromagnetic
`
`spectrum; its vertical geometry; its brightness and efficiency; and its
`
`comparative electronic longevity to prior diodes (“lifetimes of greater than
`
`10,000 hours operating at a forward bias current of 50 milliamps at room
`
`temperature, and lifetimes of greater than 10,000 hours operating at a
`
`forward bias current of 30 milliamps at
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