UNITED STATES PATENT AND TRADEMARK OFFICE
`
`__________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`__________________
`
`CREE, INC.
`Petitioner
`
`
`v.
`
`DOCUMENT SECURITY SYSTEMS, INC.
`Patent Owner
`__________________
`Case No. IPR2018-01220
`U.S. Patent No. 7,256,486
`__________________
`PETITION FOR INTER PARTES REVIEW OF
`U. S. PATENT NO. 7,256,486 UNDER
`35 U.S.C. §§ 311-319 AND 37 C.F.R. § 42.100 ET SEQ.
`
`

`

`
`
`V. 
`VI. 
`
`Table of Contents 
`
`INTRODUCTION .......................................................................................... 1 
`I. 
`GROUNDS FOR STANDING (37 C.F.R. § 42.104(a)) ................................ 1 
`II. 
`III.  OVERVIEW OF THE ’486 PATENT ........................................................... 1 
`IV.  BRIEF DESCRIPTION OF THE PRIOR ART ............................................. 4 
`A. 
`JAPANESE PATENT APPLICATION PUBLICATION NO. 2001-308388
`(ISHINAGA) ............................................................................................ 4 
`U.S. PATENT NO. 5,177,593 (ABE) ....................................................... 6 
`B. 
`U.S. PATENT NO. 6,791,119 TO SLATER, JR. ET AL. (“SLATER”) ........... 8 
`C. 
`PERSON HAVING ORDINARY SKILL IN THE ART ............................ 12 
`IDENTIFICATION OF CLAIMS BEING CHALLENGED
`(§ 42.104(B)) ................................................................................................ 13 
`A. 
`37 C.F.R. § 42.104(B)(1): CLAIMS FOR WHICH INTER PARTES
`REVIEW IS REQUESTED ........................................................................ 13 
`37 C.F.R. § 42.104(B)(2): THE PRIOR ART AND SPECIFIC
`GROUNDS ON WHICH THE CHALLENGE TO THE CLAIMS IS
`BASED ................................................................................................. 14 
`37 C.F.R. § 42.104(B)(3): CLAIM CONSTRUCTION .............................. 15 
`C. 
`“METALLIZED . . . MAJOR SURFACE” ............................................................... 16 
`VII.  PRECISE REASONS FOR THE RELIEF REQUESTED .......................... 19 
`A.  GROUND 1: CLAIMS 1-4 ARE RENDERED OBVIOUS BY ISHINAGA
`IN VIEW OF SLATER ............................................................................. 19 
`1. 
`Independent Claim 1 ................................................................ 19 
`2. 
`Dependent Claim 2 .................................................................. 39 
`3. 
`Dependent Claim 3 .................................................................. 49 
`4. 
`Dependent Claim 4 .................................................................. 52 
`
`B. 
`
`
`
`

`

`
`
`B. 
`
`GROUND 2: CLAIMS 1-4 ARE RENDERED OBVIOUS BY ABE IN
`VIEW OF SLATER .................................................................................. 54 
`1. 
`Independent Claim 1 ................................................................ 54 
`2. 
`Dependent Claim 2 .................................................................. 69 
`3. 
`Dependent Claim 3 .................................................................. 78 
`4. 
`Dependent Claim 4 .................................................................. 81 
`VIII.  MANDATORY NOTICES PURSUANT TO 37 C.F.R. § 42.8(A)(1) ........ 82 
`A. 
`C.F.R. § 42.8(B)(1): REAL PARTY-IN-INTEREST ................................. 82 
`B. 
`C.F.R. § 42.8(B)(2): RELATED MATTERS ............................................ 83 
`C. 
`C.F.R. § 42.8(B)(3) AND (4): LEAD AND BACK-UP COUNSEL AND
`SERVICE INFORMATION ....................................................................... 84 
`IX.  CONCLUSION ............................................................................................. 85 
`
`
`
`CERTIFICATE OF SERVICE
`CERTIFICATE OF COMPLIANCE WITH 37 C.F. R. § 42.24
`
`
`
`ii
`
`

`

`
`
`
`
`CASES
`
`TABLE OF AUTHORITIES
`
`Page
`
`Cuozzo Speed Techs. LLC v. Lee,
`136 S. Ct. 2131 (2016) ........................................................................................ 16
`
`Document Security Systems, Inc. v. Cree, Inc.,
`No. 2:17-cv- 00309 (E.D. Tex.) .......................................................................... 83
`
`Document Security Systems, Inc. v. Cree, Inc.,
`No. 2:17-cv- 04263 (C.D. Cal.) .......................................................................... 83
`
`Document Security Systems, Inc. v. Everlight Electronics Co.,
`Ltd. et al., No. 2:17-cv-00310 (E.D. Tex.) ......................................................... 83
`
`Document Security Systems, Inc. v. Everlight Electronics Co.,
`Ltd. et al., No. 2:17-cv-04273 (C.D. Cal.) .......................................................... 83
`
`Document Security Systems, Inc. v. Lite-On, Inc.,
`No. 2:17-cv-06050 (C.D. Cal.) ........................................................................... 83
`
`Document Security Systems, Inc. v. Nichia Corporation et al.,
`No. 2:17-cv-08849 (C.D. Cal.) ........................................................................... 83
`
`Document Security Systems, Inc. v. OSRAM GmbH,
`No. 2:17-cv-05184 (C.D. Cal.) ........................................................................... 83
`
`Document Security Systems, Inc. v. Seoul Semiconductor Co. Ltd.,
`No. 2:17- cv-00308 (E.D. Tex.) .......................................................................... 83
`
`Document Security Systems, Inc. v. Seoul Semiconductor Co. Ltd.,
`No. 8:17- cv-00981 (C.D. Cal.) .......................................................................... 83
`
`
`
`

`

`
`
`In re Schreiber,
`128 F.3d 1473 (Fed. Cir. 1997) .................................................................... 53, 81
`
`Versata Dev. Grp., Inc. v. SAP Am., Inc.,
`793 F.3d 1306 (Fed. Cir. 2015) .......................................................................... 16
`
`STATUTES
`
`35 U.S.C. § 102 ............................................................................................ 4, 7, 8, 15
`
`35 U.S.C. § 103 ........................................................................................................ 15
`
`OTHER AUTHORITIES
`
`37 C.F.R. § 42.8(A)(1) ............................................................................................. 82
`
`37 C.F.R. § 42.8(b) ...................................................................................... 82, 83, 84
`
`37 C.F.R. § 42.10(b) ................................................................................................ 85
`
`37 C.F.R. § 42.24(a)(1)(i) ........................................................................................ 85
`
`37 C.F.R. § 42.100(b) .............................................................................................. 16
`
` (37 C.F.R. § 42.104(A)) ............................................................................................ 1
`
`37 C.F.R. § 42.104(B) .............................................................................................. 14
`
`37 C.F.R. § 42.104(b)(1) .......................................................................................... 14
`
`37 C.F.R. § 42.104(b)(2) .......................................................................................... 14
`
`37 C.F.R. § 42.104(b)(3) .......................................................................................... 16
`
`M.P.E.P. § 2141.03 ............................................................................................ 13, 14
`
`
`
`
`
`ii
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`

`

`
`
`
`
`
`
`PETITIONER’S EXHIBIT LIST
`Description
`U.S. Patent No. 7,256,486 (“’486 patent”)
`Prosecution History of U.S. Patent No. 7,256,486 (“Prosecution
`History”)
`Declaration of Yuji Zhao, Ph.D. (“Zhao”)
`Modern Dictionary of Electronics (7th ed. 1999)) pp. 239 and 467
`Microchip Fabrication (4th ed. 2000) p. 396
`Pecht et al. “Plastic-Encapsulated Microelectronics” (1995) pg. 459
`Meriam Webster’s Collegiate Dictionary (10th ed. 1997) pg. 730
`Japanese Patent Application Publication No. 2003-17754, English
`translation of Japanese Patent Application Publication No. 2003-
`17754 and Certification of Translation (Rohm)
`Japanese Patent Application Publication No. 2001-352102 English
`translation of Japanese Patent Application Publication No. 2001-
`352102 and Translator Declaration (Matsushita)
`U.S. Patent No. 5,376,580 (“Kish”)
`U.S. Patent No. 5,523,589 (“Edmond 589)
`U.S. Patent No. 6,791,119 (“Slater”)
`U.S. Patent No. 5,416,342 (“Edmond 342”)
`CV of Zhao
`Pecht, M., R. Agarwal, P. McCluskey, T. Dishongh, S. Javadpour,
`and R. Mahajan, Electronic Packaging Materials and their Properties,
`CRC Press, Boca Raton, FL, 1999 pg. 37 (“Electronic Packaging”)
`Japanese Patent Application Publication No. 2001-308388, English
`translation of Japanese Patent Application Publication No. 2001-
`308388 and Certification of Translation (Ishinaga)
`U.S. Patent No. 5,177,593 (“Abe”)
`
`Exhibit
`1001
`1002
`
`1003
`1004
`1005
`1006
`1007
`1008
`
`1009
`
`1010
`1011
`1012
`1013
`1014
`1015
`
`1016
`
`1017
`
`iii
`
`

`

`
`
`I.
`
`INTRODUCTION
`This Petition establishes a reasonable likelihood that at least one of claims 1-
`
`4 of US Patent No. 7,256,486 (Ex. 1001) is unpatentable. Declaratory evidence
`
`from Dr. Yuji Zhao, an expert in the technological field of light-emitting diodes
`
`(“LEDs”), including LED packaging, demonstrates why a person of ordinary skill
`
`in the art (“POSA”) would have understood that the prior art references render
`
`claims 1-4 unpatentable and why it would have been obvious to a POSA to
`
`combine references. Accordingly, Petitioner requests that the Board institute inter
`
`partes review.
`
`II. GROUNDS FOR STANDING (37 C.F.R. § 42.104(A))
`Petitioner certifies that the ’486 patent is available for inter partes review
`
`and that Petitioners are not barred or estopped from requesting an inter partes
`
`review on the grounds identified herein.
`
`III. OVERVIEW OF THE ’486 PATENT
`The ’486 patent is directed to a packaging device 100 for a light emitting
`
`diode (LED). Ex. 1001 at Abstract, 2:9-10, 2:33-43, 3:36-39; Ex. 1003, ¶41.1
`
`FIGS. 1A and 1B below show the packaging device includes a substrate 110 with
`
`two opposed major surfaces 112 (top) and 114 (bottom), a mounting pad 130 and a
`
`1 Exhibit 1003 is the Declaration of Yuji Zhao, Ph.D.
`
`
`
`1
`
`

`

`
`
`bonding pad 132 (top), two connecting pads 140 and 142 (bottom), and
`
`interconnecting elements 120 and 122 located in through holes 116 and 118,
`
`respectively. Ex. 1001 at Abstract, 2:33-43, 3:43-57. The mounting pad 130 and
`
`connecting pad 140 are electrically connected by interconnecting element 120, and
`
`the bonding pad 132 and connecting pad 142 are electrically connected by
`
`interconnecting element 122. Id. at 3:43-57. The packaging device 100 includes a
`
`semiconductor die 250 embodied as a light emitting diode (LED) that “has anode
`
`and cathode electrodes (not shown) covering at least parts of its opposed major
`
`surfaces,” the LED 250 being mounted on mounting pad 130 such that “the
`
`metallization on its bottom major surface attached to mounting pad 130.” Id. at
`
`5:7-12.2 “Bonding wire 254 extends between a bonding pad located on the top
`
`major surface of semiconductor die 250 and bonding pad 132.” Id. at 5:15-18.
`
`“Encapsulant 252 covers the semiconductor die and the part of the major surface
`
`112 of substrate 100 where mounting pad 130 and bonding pad 132 are located.”
`
`Id. at 5:12-15. See also Ex. 1003, ¶¶41-42.
`
`
`2 All emphasis is added unless stated otherwise.
`
`
`
`2
`
`

`

`
`
`
`
`
`
`Also, “The metallization on the bottom major surface of semiconductor die
`
`250 typically constitutes the cathode electrode of the light-emitting diode.” Ex.
`
`1001 at 5:20-28. Ex. 1003, ¶43. The ’486 patent admits that such metallization
`
`was “conventional” and “widely used in the industry”:
`
`Many types of conventional semiconductor device are
`composed of a semiconductor die mounted in a packaging
`device. One type of packaging device widely used in the
`industry includes a metal lead frame. A metallization layer of
`aluminum located on the bottom surface of the semiconductor
`die is bonded to a conductive surface that forms part of the lead
`
`
`
`3
`
`

`

`
`
`frame to attach and electrically connect the die to the lead
`frame.
`
`
`
`
`
`
`
`*
`
`
`
`*
`
`
`
`*
`
`Recently, semiconductor die having a substrate surface
`metallization layer of a gold-tin alloy . . . have been introduced
`in light-emitting devices.
`
`See Ex. 1001 at 1:17-27, 1:49-52; Ex. 1003, ¶44.
`
`IV. BRIEF DESCRIPTION OF THE PRIOR ART
`A.
`Japanese Patent Application Publication No. 2001-308388
`(Ishinaga)
`Japanese Patent Application Publication No. 2001-308388 (“Ishinaga”) is
`
`entitled “Chip-Type Light-Emitting Element.” Ex. 1016. Ishinaga was not of
`
`record during the prosecution. Ishinaga was published on November 2, 2001, and
`
`is prior art under pre-AIA § 102(b).
`
`FIG. 1 of Ishinaga ( below) shows a cross sectional view of a semiconductor
`
`device including an insulating substrate 1 with a top major surface 1a and a bottom
`
`major surface 1c. Ex. 1016 at Abstract, Claim 1, ¶6, ¶13. Ishinaga states:
`
`This chip-type light-emitting element has . . . a light emitter
`
`chip 3 [] mounted on an insulating substrate 1, and the light
`
`emitter chip 3 is sealed by a translucent member 8. That is, a
`
`
`
`4
`
`

`

`
`
`pair of internal electrodes 2 are formed on one surface 1a of the
`
`insulating substrate 1, and the light emitter chip 3 is die-bonded
`
`to one of the internal electrodes, while the light emitter chip and
`
`the other internal electrode 2 are electrically connected by a
`
`bonding wire 4. . . . The internal electrodes 2a are electrically
`
`connected to external electrodes 5 formed on the other surface
`
`1c of the insulating substrate 1 by a conductive material 7 filled
`
`into through-holes 6 opened in the insulating substrate 1.
`
`Id. at ¶¶13-14. Ex. 1003, ¶46.
`
`
`Top right and left internal electrodes correspond to the claimed electrically
`
`conductive mounting pad and electrically conductive bonding pad, respectively,
`
`
`
`5
`
`

`

`
`
`and the pair of bottom electrodes 5 correspond the claimed conductive pads on the
`
`bottom major surface. Ex. 1016 at Abstract, ¶¶6-8, ¶¶10-16. Right and left
`
`conductive material 7 in through holes 6 serve as the claimed interconnecting
`
`elements). Ex. 1016 at ¶8, ¶9, ¶14. The top surface of LED 3 (light emitter chip 3)
`
`is connected via wire 4 to bonding pad 2. Id. at Abstract, ¶9, ¶13, ¶15. See also
`
`Ex. 1003, ¶47.
`
`B. U.S. Patent No. 5,177,593 (Abe)
`U.S. Patent No. 5,177,593 (“Abe”) is entitled “Display Device With LEDs
`
`Having A Reduction Of The Thermal Expansion Coefficients [sic Among] The
`
`Associated Components.” Ex. 1017. Abe issued on January 5, 1993, and is prior
`
`art under pre-AIA § 102(b). Abe was found by the examiner after issuance of the
`
`Notice of Allowance and not applied in any claim rejections.
`
`FIG. 9 of Abe (below) shows a semiconductor device. The device includes a
`
`planar substrate 34 with top and bottom surfaces. Ex. 1017 at Abstract, 7:1-9,
`
`Claim 1. See also Ex. 1003, ¶49.
`
`
`
`6
`
`

`

`
`
`
`As shown in FIG. 9, the top surface of the substrate 34 has thereon an
`
`electrically conductive mounting pad (left lead interconnection 32a) and an
`
`electrically conductive bonding pad (right lead interconnection 32a). Ex. 1017 at
`
`7:2-3. A pair of conductive pads (two electrodes 32c) are provided on the bottom
`
`surface of the substrate 34. Id. at Abstract, 7:1-5. The top lead interconnections
`
`32a and bottom electrodes 32c are connected by the two portions of
`
`interconnection leads 32a disposed in through holes 32b. Id. at 7:1-5. LED 33 is
`
`mounted on the mounting pad (top left interconnection element 32a). Id. at
`
`Abstract, 4:22-24. LED 33 is electrically connected to the bonding pad by a
`
`bonding wire 36. Id. at Abstract, 4:22-27, Claim 1. See also Ex. 1003, ¶50.
`
`
`
`7
`
`

`

`
`
`C. U.S. Patent No. 6,791,119 to Slater, Jr. et al. (“Slater”)
`U.S. Patent No. 6,791,119 (“Slater”) is entitled “Light Emitting Diodes
`
`Including Modifications For Light Extraction.” Ex. 1012. Slater, which was not of
`
`record during the prosecution of the ’486 patent, was filed on January 25, 2002,
`
`and published on September 5, 2002, and is prior art under pre-AIA §§ 102(e) and
`
`102(a).
`
`Slater discloses a variety of LEDs in which one metal electrode is provided
`
`on the top surface and another metal electrode is provided on the bottom surface of
`
`the LED. See, e.g., Ex. 1012 at FIGS. 3, 16, 17A, 18; 11:12-20, 17:59-19:27,
`
`19:28-21:13, 21:59-22:38. In FIG. 16 below, light emitting diode 1600 is mounted
`
`on a mounting support 210 with silicon carbide substrate 110 is adjacent the
`
`mounting support 210, and a diode region 170 on the silicon carbide substrate 110
`
`Id. at 18:3-8. See also Ex. 1003, ¶52.
`
`
`
`8
`
`

`

`
`
`
`The metallized top surface of the LED is ohmic layer 150, and the
`
`metallized bottom surface may comprises layers contact structure 1620 made up of
`
`ohmic layer 160, reflector layer 140, barrier layer 1610, and bonding layer 230, all
`
`of which may be metal. Slater states, e.g., “The ohmic contacts 150/160
`
`preferably are a transparent layer or layers of metal, such as a thin layer of
`
`platinum . . . .” Id. at 18:36-39. “[C]ontact structure 1620 includes an ohmic
`
`region 160, a reflector 140, a barrier region 1610, and a bonding region 230.” Id.
`
`at 18:33-35. “[T]he reflector 140 can . . . reflecting metal, such as silver and/or
`
`aluminum . . . .” Id. at 18:58-60. “[T]he barrier region 1610 . . . includes between
`
`about 100 Å and about 5000 Å of nickel, nickel/vanadium and/or
`
`titanium/tungsten.” Id. at 19:4-8. “The bonding region 230 can be a metal layer
`
`
`
`9
`
`

`

`
`
`comprising, for example, gold, indium, solder, and/or braze . . . .” Id. at 19:11-13.
`
`See also Ex. 1003, ¶53.
`
`FIG. 17A of Slater below illustrates another example LED: “LEDs 1700
`
`include a transparent substrate 1310 . . . and a diode region 1320 . . . on a mounting
`
`support 210 . . ., and the silicon carbide substrate 1310 . . . .” Ex. 1012 at 19:37-
`
`45. See also Ex. 1003, ¶54.
`
`The metallized top surface of the LED may comprise layers of n-contact
`
`structure 1730, all of which are disclosed as metal. Slater states:
`
`
`
`
`
`10
`
`

`

`
`
`“[A]n n-contact structure 1730 . . . includes an ohmic/reflector
`region 1732, an adhesion region 1734, a barrier region 1736
`and a bonding region 1738. The ohmic/reflector region 1732
`[is] an n-ohmic material, such as aluminum and/or silver . . . .
`An optional adhesion region 1734 comprising . . . titanium,
`may be provided. A barrier region 1736 . . . of platinum may be
`used. Finally, a bonding region 1738 . . . of gold may be used .
`. . .
`
`Id. at 20:52-65. See also Ex. 1003, ¶55.
`
`The metallized bottom surface of the LED of FIG. 17A may comprise one or
`
`more of the layers of p-contact structure 1740, all of which are disclosed as metal:
`
`[The] p-contact structures 1740 . . . include a p-ohmic region
`1742, a reflector 1744, a barrier region 1746 and/or a bonding
`region 1748. In some embodiments, the p-ohmic region 1742
`may comprise a p-ohmic metal, such as nickel/gold, nickel
`oxide/gold . . . .” [A] a thick reflector 1744 such as silver
`and/or aluminum is on the ohmic region 1742 . . . . the flip-
`chip mounted LED can be die attached using a bonding region
`1748 that can include gold, indium, conventional epoxy
`materials, braze and/or solder with the use of appropriate
`solder and/or solder barrier regions 1746, such as nickel,
`nickel/vanadium and/or titanium tungsten.
`
`Id. at 20:7-45. See also Ex. 1003, ¶56.
`
`
`
`11
`
`

`

`
`
`Slater refers to the term “contact structure” and “electrode structure”
`
`interchangeably. See, e.g., Ex. 1012 at 21:9-16 (referring to element 1730 as both
`
`an “electrode structure 1730” and a “contact structure 1730”). Slater also notes
`
`that, in the drawings, “the thickness of layers and regions are exaggerated for
`
`clarity.” Id. at 6:59-60. See also Ex. 1003, ¶57.
`
`Slater also teaches that the metallization on the upper surface of the LED
`
`and the metallization on the lower surface of the LED may completely cover those
`
`top and bottom surfaces. See, e.g., Ex. 1012 at 20:12-16, 21:9-12, 19:57-61. See
`
`also Ex. 1003, ¶58.
`
`Slater also indicates that “ohmic contacts 150/160 preferably provide current
`
`spreading, to facilitate efficient and uniform current injection into the active region
`
`170” and that “the functionality of the transparent ohmic region and the reflector
`
`can be combined in a single ohmic and reflector region.” Ex. 1012 at 18:47-51,
`
`4:28-31. See also Ex. 1003, ¶59.
`
`V.
`
`PERSON HAVING ORDINARY SKILL IN THE ART
`As explained in M.P.E.P. § 2141.03, a number of factors may be considered
`
`in determining the proper level of skill:
`
`The person of ordinary skill in the art is a hypothetical person
`who is presumed to have known the relevant art at the time of
`
`
`
`12
`
`

`

`
`
`the invention. Factors that may be considered in determining
`the level of ordinary skill in the art may include: (A) “type of
`problems encountered in the art;” (B) “prior art solutions to
`those problems;” (C) “rapidity with which innovations are
`made;” (D) “sophistication of the technology; and” (E)
`“educational level of active workers in the field. In a given
`case, every factor may not be present, and one or more factors
`may predominate.”
`A person of ordinary skill in the art at the time of the purported invention would
`
`have had at least a B.S. in mechanical or electrical engineering or a related field,
`
`and four years’ experience designing LED packages. Ex. 1003, ¶61.3 This
`
`description is approximate. A higher level of education or skill might make up for
`
`less experience, and vice-versa. Id. For example, a M.S. in the above fields and
`
`two years’ experience would suffice. Id.
`
`VI.
`
`IDENTIFICATION OF CLAIMS BEING CHALLENGED
`(§ 42.104(B))
`A.
`37 C.F.R. § 42.104(b)(1): Claims For Which Inter Partes Review Is
`Requested
`Inter Partes review is requested for claims 1-4 of the ’486 patent.
`
`
`3 Exhibit 1003 is the declaration of Yuji Zhao, Ph.D.
`
`
`
`13
`
`

`

`
`
`
`
`
`
`
`
`B.
`
`37 C.F.R. § 42.104(b)(2): The Prior Art And Specific Grounds On
`Which The Challenge To The Claims Is Based
`Inter Partes review is requested in view of the following prior art references:
`
`Japanese Patent Application Publication No. 2001-308388 (Ex. 1016,
`
`“Ishinaga”);
`
`U.S. Patent No. 5,177,593 (Ex. 1017, “Abe”);
`
`U.S. Patent No. 6,791,119 (Ex. 1012, “Slater”).
`
`The specific statutory grounds under 35 U.S.C. §§ 102 or 103 on which the
`
`challenge to the claims is based and the references relied upon for each ground are
`
`as follows:
`
`Ground
`
`Claims
`
`1-4
`
`1-4
`
`1
`
`2
`
`
`
`Statutory Provision
`(pre-AIA)
`§ 103
`
`§ 103
`
`Prior Art
`
`Ishinaga (Ex. 1016)
`Slater (Ex. 1012)
`Abe (Ex. 1017)
`Slater (Ex. 1012)
`
`Three other Petitions have been filed against the ’486 patent: IPR2018-
`
`00333, IPR2018-01166, and IPR2018-01205 (which is a copy of IPR2018-00333
`
`filed by Petitioner Cree with a joinder motion). However, Ishinaga and Abe, the
`
`primary references asserted in the instant Petition, are not presented in the
`
`
`
`14
`
`

`

`
`
`identified grounds in the other two petitions. Moreover, Ishinaga and Abe are both
`
`prior art under § 102(b) whereas two of the three primary references of IPR2018-
`
`01166, and one of the two primary references of IPR2018-00333, are prior art
`
`under § 102(a). Clear differences exist between the art applied in the instant
`
`petition and that applied in the other petitions. Petitioner submits that, under the
`
`circumstances, it should be entitled to its own challenge to the ’486 patent claims
`
`on each of the identified grounds.
`
`C.
`37 C.F.R. § 42.104(b)(3): Claim Construction
`For an unexpired patent subject to IPR, the Board applies the “broadest
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`reasonable construction in light of the specification.” 37 C.F.R. § 42.100(b); see
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`also Cuozzo Speed Techs. LLC v. Lee, 136 S. Ct. 2131, 2144–46 (2016). This
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`standard is different from—and broader than—that applied in district court.
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`Versata Dev. Grp., Inc. v. SAP Am., Inc., 793 F.3d 1306, 1327-28 (Fed. Cir.
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`2015).4 The USPTO published a Notice of Proposed Rulemaking of May 9, 2018,
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`4 Petitioner does not concede that the meaning of any claim terms are as
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`broad under the district court standard as they are under the broadest reasonable
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`interpretation standard. Petitioner reserves the right to argue for alternative and
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`narrower definitions in district court.
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`“Changes to the Claim Construction Standard for Interpreting Claims in Trial
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`Proceedings Before the Patent Trial and Appeal Board,” Fed. Reg. Vol. 83, No. 90,
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`21221-21226. Accordingly, it appears possible that a proceeding instituted under
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`this petition may be treated under the same standard applied in federal district
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`courts and International Trade Commission (‘‘ITC’’) proceedings. However, the
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`current standard before the PTAB is “broadest reasonable interpretation” (BRI),
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`and terms are construed here under the BRI standard. Should the Board determine
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`that the terms should be construed more narrowly than suggested here, grounds of
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`patentability addressed below would still satisfy narrower constructions, as
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`explained for the specific grounds of unpatentability.
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`“metallized . . . major surface”
`The term “metallized . . . major surface” should be construed to mean a
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`metal layer on at least a portion of the major surface. The term “metallized . . .
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`major surface” is not expressly defined in either the specification of the ’486 patent
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`or its prosecution history. However, the patent uses the term in several instances.
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`For example, “A metallization layer of aluminum located on the bottom surface of
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`the semiconductor die is bonded to a conductive surface that forms part of the lead
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`frame to attach and electrically connect the die to the lead frame.” Ex. 1001 at
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`1:19-23. Also, “Recently, semiconductor die having a substrate surface
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`metallization layer of a gold-tin alloy . . . have been introduced in light-emitting
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`devices.” Id. at 1:49-51. See also Ex. 1003, ¶63.
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`The ’486 patent also states, “In the example shown, semiconductor die 250
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`embodies a light-emitting diode and has anode and cathode electrodes (not shown)
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`covering at least parts of its opposed major surfaces.” Id. at 5:7-10. As this
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`excerpt suggests, the patent discloses that the top and bottom surfaces comprise
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`electrodes, which cover at least parts of the opposed major surfaces, which are the
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`relatively larger surfaces of the substrate. It appears, therefore, that the ’486 patent
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`uses the terms electrode and metallized surface somewhat interchangeably. In that
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`regard the ’486 patent also states:
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`The bonding pad on the top major surface of semiconductor die 250 is
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`typically part of or connected to the anode electrode of the light-
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`emitting diode. The metallization on the bottom major surface of
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`semiconductor die 250 typically constitutes the cathode electrode of
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`the light-emitting diode.
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`Id. at 5:18-22; see also id. at 5:10-12 (“Semiconductor die 250 is mounted on
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`packaging device 100 with the metallization on its bottom major surface attached
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`to mounting pad 130.”). See also Ex. 1003, ¶64.
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`A POSA would have understood the term metallized to mean to have a metal
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`layer thereon, and would have understood the term metallized . . . major surface
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`read in view of the specification to mean a metal layer on at least a portion of the
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`major surface. Ex. 1003, ¶65. Accordingly, the term should be construed under
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`the broadest reasonable construction to mean a metal layer on at least a portion of
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`the major surface.
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`This interpretation is supported, for example, by Ex. 1004 (Modern
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`Dictionary of Electronics (7th ed. 1999)), which defines metallization in relevant
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`part as “[a] film pattern (single or multilayer) of conductive material deposited
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`onto a substrate to interconnect electronic components, or the metal film on the
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`bonding area of a substrate that becomes part of the bond and performs both
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`electrical and mechanical functions.” Ex. 1004 at 467; see also Ex. 1005
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`(Microchip Fabrication (4th ed. 2000)) at 396 (“The most common and familiar
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`use of metal films in semiconductor technology is for surface wiring. The
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`materials, methods, and processes of ‘wiring’ the components parts together is
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`generally referred to as metallization or the metallization process.”); Ex. 1006
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`(Plastic-Encapsulated Microelectronics (1995)) at 459 (“METALLIZATION: A
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`deposited or plated thin metallic film used for its protective or electrical
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`properties.”); Ex. 1007 (Merriam Webster’s Collegiate Dictionary (10th ed. 1997))
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`at 730 (“metallize . . . to coat, treat, or combine with a metal.”). All of these
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`definitions are consistent with the metallized surface being a layer of metal on at
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`least a portion of the major surface. Ex. 1003, ¶66.
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`VII. PRECISE REASONS FOR THE RELIEF REQUESTED
`A. Ground 1: Claims 1-4 Are Rendered Obvious by Ishinaga in View
`of Slater
`1. Independent Claim 1
`a)
`“A semiconductor device comprising”
`To the extent that the preamble is found to limit the claims, Ishinaga
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`discloses a semiconductor device as shown in FIG. 1 below. Ishinaga states, e.g.,
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`“FIG. 1 is an illustrative cross-sectional view illustrating the structure of a chip-
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`type light-emitting element of an embodiment of the present invention. This chip-
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`type light-emitting element has a structure in which a light emitter chip 3 is
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`mounted on an insulating substrate 1, and the light emitter chip 3 is sealed by a
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`translucent member 8.” Ex. 1016 at ¶13. Ishinaga discloses that “light emitter
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`chip” may be an LED. Id. at ¶2. A POSA would have understood that a light
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`emitter chip that is an LED is a semiconductor device. Ex. 1003 at ¶69.
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`b)
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`“a substantially planar substrate having opposed major
`surfaces”
`Ishinaga discloses a substantially planar substrate having opposed major
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`surfaces. As shown in annoted FIG. 1 of Ishinaga below, insulating substrate 1
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`(red) is substantially planar and has opposed major surfaces, i.e., the top surface 1a
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`and the bottom surface 1c, which are the relatively larger surfaces of the substrate.
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`Ex. 1016 at ¶13. Ishinaga states, “This chip-type light-emitting element has a
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`structure in which a light emitter chip 3 is mounted on an insulating substrate 1,
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`and the light emitter chip 3 is sealed by a translucent member 8.” Ex. 1016 at ¶13,
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`see also id. at Abstract, Claims 1, 2, 4-6, ¶¶6-12, 13-21; Ex. 1003, ¶70.
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`c)
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`“an electrically conductive mounting pad located on one of
`the major surfaces of the substrate”
`Ishinaga discloses an electrically conductive mounting pad (right internal
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`electrode 2a, colored red) on one of the major surfaces (top surface 1a) of the
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`substrate (substrate 1). Ishinaga states, e.g., “This chip-type light-emitting element
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`has a structure in which a light emitter chip 3 is mounted on an insulating substrate
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`1, and the light emitter chip 3 is sealed by a translucent member 8. That is, a pair
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`of internal electrodes 2 are formed on one surface 1a of the insulating substrate 1,
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`and the light emitter chip 3 is die-bonded to one of the internal electrodes, while
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`the light emitter chip and the other internal electrode 2 are electrically connected
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`by a bonding wire 4.” Ex. 1016 at ¶13. See also id. at Abstract, ¶¶6, 9, 13, 17-18,
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`20; Ex. 1003, ¶71.
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`The mounting pad is electrically conductive since “the internal electrodes 2
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`consist of three layers including Cu (2a), Ni (2b), and Au (2c) from the insulating
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`substrate 1 side.” Ex. 1016 at ¶14. Also, Ishinaga expressly indicates that the
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`internal electrode 2a is electrically conductive: “Using Cu, which is highly
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`conductive, as a base material yields low resistance.” Id. A POSA would
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`understand that copper (Cu), nickel (Ni), and gold (Au) are electrically conductive.
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`Ex. 1003, ¶72. Also, electrodes were well known to a POSA specifically to be
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`electrically conductive. Id. Accordingly, the electrode 2 on which LED 3 is
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`mounted serves as a mounting pad, is electrically conductive, and is located on one
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`of major surfaces (i.e., the top major surface) of the substrate. Ex. 1003, ¶72.
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`d)
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`“a ligh