`
`The #1, easy-to-read, math-free introduction to
`semiconductor processing
`
`Perfect for training, teaching, & vo-tech
`programs
`
`Updated with new cleaning techniques, packing
`technologies, & fabrication methods
`
`PETER VAN ZANT
`
`§|Eml‘|@@[fl@@8m PROCESSING
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`Cree Ex. 1005
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`Cree Ex. 1005
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`Microchip
`Fabficafion
`
`A Practical Guide to Semiconductor Processing
`
`Peter Van Zant
`
`Fourth Edition
`
`McGraw-Hill
`New York San Francisco Washington,D.C. Auckland Bogoté
`Caracas Lisbon London Madrid Mexico City Milan
`Montreal New Delhi San Juan Singapore
`Sydney Tokyo Toronto
`
`
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`Cree Ex. 1005
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`Cree Ex. 1005
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`on : a practical guide to semicond
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`uctor processing / Peter Van
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`Library of Congress Cataloging-in-Publication Data
`Van Zant, Peter.
`Microchip fabricati
`Zant.——4th ed.
`p.
`cm.
`Includes bibliographical r
`ISBN 0-07-135636-3
`Design and construction.
`1. Semiconductors—
`TK7871.85.V36 2000
`621.3815'2‘dc21
`
`eferences and index.
`
`I. Title.
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`00-02317
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`McGraw-Hill
`A Division ofTheMcGraw-Hiu Companies
`
`\
`
`The McGraw-Hill Companies, inc. All
`Copyright c 20:10, 1997, 1934 by
`United States of America. Except as
`rights reserved. Printed in the
`right Act of .1976. no pm'L of
`permitted under the United States Copy
`uted to any form or by any
`Lhis publication may be reproduced or distrib
`system. without the prior
`means. or stored in a data base or retrieval
`written permission of the publisher.
`1234567890 DOC/DOC 09876543210
`
`ISBN 0-07—135636-3
`
`The sponsoring editor for this book was Stephen Chapman and the
`production supervisor was Sherri Souffrancc. It was set in Century
`Schoolbook by Pro-Image Corporation.
`Printed and bound by R. R. Donnelley & Sons Company.
`
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`nted on recycled, acid—free paper containing
`This book is pri
`a minimum of 50% recycled, de-inked fiber.
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`thin work lies been obtained by The N10
`information contained in
`l“Mc-Graw-flill"i from sources he-
`Grow—Hill Uompnniea. Inc.
`lievud to be reliable. However, neither 'McGrnw-ifiil nor its nu-
`thorn guarantee the accuracy or completeness of any information
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`be respnnnibln for any errors, omissions, or damages arising out
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`formation but me not attempting to render engineering or other
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`Cree Ex. 1005
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`Cree Ex. 1005
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`Metallization
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`Overview
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`two major segments. First the
`Fabrication of circuits is divided into
`
`
`(:1 in and on the wafer surface.
`active and passive parts are fabricate
`
`
`These is called the Front End Of the Line or FEOL. In the Back End
`
`
`of the Line (or BEOL), the metal systems necessary to connect the
`
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`devices and different layers are added to the chip. In this chapter the
`
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`.Ilmterials, specificationS, and methods used to complete the metalli-
`
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`zation segment is presented along with other uses of metals in chip
`manufacturing. Vacuum pumps, used in CVD, evaporation, ion im-
`
`
`plant, and sputtering systems are explained at the end of the chapter.
`
` obiectives
`U
`.
`pon COmpletion of this chapter, you should be able to:
`
`
`‘
`.
`.
`.
`Llst the requirements of a material for use as a chip surface con-
`
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`ductor.
`.
`.
`D1 aw cross sections of single and multilayer metal schemes.
`
`
`' DeSCribe the purpose and operation of a thin-film fuse.
`
`
`3A
`ation of semiconductor
`Edalfe a list of materials used in the metalliz
`
`
`eVICBS. Identify their Specific use(s).
`
`
`Draw and identify the parts of a vacuum evaporator
`00.4'02_Cn
`
`
`Describe the principle of sputtering.
`
`
`Draw and identify the parts of a sputtering system.
`
`' DeSCI‘ibe the principle and operation of oil diffusion, turbo and cry-
`Ogenjc high-vacuum pumps.
`
`1.
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`2.
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`Chapter Thirteen Introduction
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`396
`
`The most common and familiar use of metal films in semiconduCtOr
`technology is for surface wiring. The materials, methods, and Dl‘o~
`ceases of "wiring” the component parts together is generally I'elbl‘red
`to as metallization or the metallization process. Metallizasttiou includsq
`all of the steps in the inetallizatlon sequence described in Chapter 5
`
`l
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`’
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`Conductors-Single Level Metal
`In the MSI era metallization was relatively straight forward (Fig
`13.1), requiring only a single level metal process. Small holes, Called
`contact holes or contacts, are etched through the surface layers. to the
`device/circuit component parts. Following contact masking, a thin
`layer (10,000 to 15,000 A) of the conducting metal (mostly aIUmimIm
`or aluminum alloys) was deposited by vacuum evaporation, sputter.
`ing, or CVD techniques over the entire wafer. The unwanted portions
`of this layer are removed by a conventional photomasking and etch
`procedure or by lift-off. This step leaves the surface covered with thin
`lines of the metal that are called leads, metal lines, or interconnects.
`Generally a heat-treatment step, called alloying, is performed afiel-
`metal patterning to ensure good electrical contact between the metal
`and the wafer surface.
`Regardless of the structure, a metal system must meet the following
`criteria:
`
`l
`I
`
`
`
`I G00
`I Gool‘
`l;
`' Eas‘.‘
`I Goor
`I Higti'
`I Corr!
`I Long-
`I Capaf:
`I Unifcl:
`l—
`
`Conduc
`Increasi
`face wh
`The, an‘
`schemes-
`it is expu':
`two-met"
`layer for,-
`
`Water with
`Doped RegIons
`
`2.
`Patterning:
`Mask
`Contact
`
` 1.
`
`3‘
`Layering: Conducting
`Layer
`
`4.
`Patternlng: Metal
`Mask
`
`Figure 13.1 Metallization sequence.
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