`Legal Department, DL429
`Intellectual Property Administration
`P. 0. Box 7599
`Loveland, Colorado 80537-0599
`
`PATENT APPLICATION
`
`ATTORNEY DOCKET NO, 79030259-1
`
`IN THE U.S. PATENT AND TRADEMARK OFFICE
`Patent Application Transmittal L tter
`
`’
`COMMISSIONER FOR PATENTS
`PO Box 1450 |
`Al xandria, VA 22313-1450
`.
`Sir:
`) Design
`(
`Transmitted herewith for filing under 37 CFR 1.53(b) is a(n): (XX) Utility
`(X) original patent application,
`() continuation-in-part application
`
`‘
`
`INVENTOR(S):
`
`Kong Weng Leeetal.
`
`,
`
`PACKAGING DEVICE FOR SEMICONDUCTOR DIE, SEMICONDUCTOR DEVICE
`INCORPORATING SAME AND METHOD OF MAKING SAME
`
`TITLE:
`
`Enclosed are:
`
`(X) The Declaration and Power of Attorney.
`
`(x ) signed
`
`(_
`
`} unsigned or partially signed
`
`aoe
`o = ¢
`- =|.
`OQ i t
`oOo S=— *
`no ar=
`=>
`
`A760 l
`
`
`(x)_8 sheets of drawings (one set) (_) Associate Power of Attorney
`
`(_) Form PTO-1449
`(
`)
`Information Disclosure Statement and Form PTO-1449
`{fee $
`)
`(
`) Priority document(s)
`
` )(Other)
`
`{
`
`(1}
`FOR
`
`CLAIMS AS FILED BY OTHER THAN A SMALL ENTITY
`(2)
`(3)
`(4)
`NUMBER FILED
`NUMBER EXTRA
`RATE
`
`(5)
`TOTALS
`
`INDEPENDENT
`CLAIMS
`ANY MULTIPLE
`
`X $84
`
`5
`
`
`
`
`
`
`
`
`permecame0 $280
`BASICFEE: Design($290.00 Utility( #750.00 [oe
`
`
` TOTAL CHARGES TO DEPOSIT ACCOUN
`
`
`
`
`this
`At any time during the pendency of
`to Deposit Account 50-1078
`750
`Charge $
`application, please charge any fees required or credit dny over payment to Deposit Account 50-1078
`pursuant to 37 CFR 1.25. Additionally please charge any fees to Deposit Account 50-1078 under 37
`CFR 1.16, 1.17,1.19, 1.20 and 1.21. A duplicate copy of this sheet is enclosed.
`
`“Express Mail" label no. EV_262 717 905 US
`
`Date of Deposit June 27, 2003
`| hereby certify that this is being deposited with the
`United States Pasta! Service “Express Mail Post
`Office to Addressee" service under 37 CFR 1.10 on
`the date indicated above and is addressed to
`Commissioner
`for
`Patents,
`PO Box
`1450,
`Alexandria, VA 22313-1450.
`
` Respectfully submitted,
`
`By
`
`lan Hardéastle
`
`By
`
`Typed Name: Linda A. limura
`
`Attorney/Agent for Applicant(s)
`Reg. No.
`34,075
`Date: June 27, 2003
`
`Telephone No.: (650) 485-3015
`
`Cree Ex. 1002
`
`Page 1
`
`Cree Ex. 1002
`
`Page 1
`
`
`
`AGILENT TECHNOLOGIES,INC.
`Legal Department, DL429
`Intellectual Property Administration
`P.O. Box 7599
`Loveland, Colorado 80537-0599
`
`.
`
`PATENT APPLICATION
`
`ATTORNEY DOCKET NO, 79030259-1
`
`IN THE U.S. PATENT AND TRADEMARK OFFICE
`Patent Application Transmittal L tter
`
`COMMISSIONER FOR PATENTS
`PO Box 1450
`Al xandria, VA 22313-1450
`Sir:
`
`Transmitted herewith for filing under 37 CFR 1.53(b} is a(n): XX) Utility
`
`) Design
`(
`(X) original patent application
`.
`.
`.
`.
`.
`(_) continuation-in-part application
`.
`
`:
`
`INVENTOR(S): Kong Weng Leeet al.
`
`,
`
`,
`
`PACKAGING DEVICE FOR SEMICONDUCTOR DIE, SEMICONDUCTOR DEVICE
`INCORPORATING SAME AND METHOD OF MAKING SAME
`
`TITLE:
`
`Enclosed are:
`
`a =.
`e = |.
`An Set
`co os}
`oo ee |
`Pw =e
`wo
`SS5
`; aa ==o0
`w
`==
`Co =
`A=
`
`(XX) The Declaration and Power of Attorney
`(x)
`_8
`‘ sheets of drawings (one set)
`(
`) Form PTO-1449
`(_
`)
`
`(x ) signed
`
`) unsigned or partially signed
`{
`) Associate Power of Attorney
`(
`Information Disclosure Statement and Form PTO-1449
`
`(
`
`) Priority documentis)
`
`( Other}
`
`(fee $
`
`)
`
`(1)
`FOR
`
`TOTAL CLAIMS
`INDEPENDENT
`CLAIMS
`
`(3)
`
`(4)
`
`(5)
`
`X$18
`
`TOTAL CHARGES TO DEPOSIT meres]§
`
`
`—_ AS FILED BY OTHER THAN A SMALL ENTITY
`
`eras|FILED NUMBEREXTRA RATE eT
`
`ANYMULTIPLEaDEPENDENT CLAIMS
`
`
`
`BASIC FEE: Design ( =}; Utility ( $750.00 }8750|$330.00
`TOTAL FILING FEB
`OTHER resp=$s
`
`
`
`to Deposit Account 50-1078.
`Charge $
`this
`At any time during the pendency of
`application, please charge any fees required or credit dny over payment to Deposit Account 50-1078
`pursuant to 37 CFR 1.25. Additionally please charge any fees to Deposit Account 50-1078 under 37
`CFR 1.16, 1.17,1.19, 1.20 and 1.21. A duplicate copy of this sheet is enclosed
`
`“Express Mail” label no. EV 262 717 905 Us
`Date of Deposit June 27, 2003
`
`| hereby certify that this is being deposited with the
`United States Posta! Service “Express Mail Post
`Office to Addressee" service under 37 CFR 1.10 on
`the date indicated above and is addressed to
`Commissioner
`for
`Patents,
`PO
`Box
`1450,
`Alexandria, VA 22313-1450.
`
`By
`
`Typed Name: Linda A. limura
`
`‘
`
`Respectfully submitted,
`
` By
`
`Attorney/Agentfor Applicant(s)
`Reg. No.
`34,075
`Date: June 27, 2003
`
`Telephone No.: (650) 485-3015
`
`Cree Ex. 1002
`
`Page 2
`
`Cree Ex. 1002
`
`Page 2
`
`
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`APPLICATION FOR PATENT
`
`Packaging Device for Semiconductor Die, Semiconductor Device Incorporating Same
`
`and Method of Making Same
`
`Inventors:
`
`Kong Weng Lee
`Kee Yean Ng
`Yew Cheong Kuan
`Cheng Why Tan
`Gin Ghee Tan
`
`Related Application
`
`[0001]
`
`- This application is related to a simultaneously-filed United States patent
`
`application serial number 10/xxx,xxx entitled Methodfor Fabricating a Packaging
`
`Device for Semiconductor Die and Semiconductor Device Incorporating Same of
`
`inventors Kong Weng Lee, Kee Yean Ng, Yew Cheong Kuan, Cheng Why Tan and
`Gin Ghee Tan, attorney docket number 70030260-1.
`.
`
`(0002)
`
`Many types of conventional semiconductor device are composed of a
`
`Backgroundofthe Invention
`
`semiconductor die mounted in a packaging device. One type of packaging device
`
`widely used in the industry includes a metal Jead frame. A metallization layerof.
`
`aluminum located on the bottom surface of the semiconductor die is bonded to a
`
`conductive surface that forms part of the lead frame to attach and electrically connect
`
`the die to the lead frame. Additionally, electrical connections are made between
`
`bonding pads on the top surface of the die and other leads of the lead frame to provide
`
`additional electrical connections to the die. The lead frame and semiconductor dic are
`
`then encapsulated to complete the semiconductor device. The packaging device
`protects the semiconductordie and provideselectrical and mechanical connectionsto
`the die that are compatible with conventional printed circuit board assembly
`
`A- 70030259
`
`2003-06-26 09:14
`
`Cree Ex. 1002
`
`Page 3
`
`Cree Ex. 1002
`
`Page 3
`
`
`
`A-70030259-1
`
`PATENT
`
`processes.
`
`[0003]
`
`In such conventional semiconductor devices, the bottom surface of the die is
`
`typically bonded to the conductive surface of the lead frame using a silver epoxy
`
`adhesive that cures at a relatively low temperature, typically about 120 °C. The curing
`
`temperature of the silver epoxy adhesive is compatible with the other materials of the
`packaging device.
`,
`The volumeof the packaging device used in such conventional semiconductor
`
`{0004]
`
`devices, i.e., the lead frame and the encapsulant, is typically many times that the
`semiconductor die. This makes such conventional semiconductor devices unsuitable
`for use in applications in which a high packing density is required. A high packing
`
`density allows miniaturization and other benefits. Therefore, what is neededis a
`
`semiconductor packaging device that is comparable in volume with the semiconductor
`
`die and that is compatible with conventional printed circuit board assembly processes.
`
`{0005]
`
`Recently, semiconductor die having a substrate surface metallization layer of a
`
`gold-tin alloy (80 % Au:20 % Sn approximately) have been introducedin light-
`
`emitting devices. Such semiconductor die typically have a substrate of sapphire,
`
`silicon carbide or a Group III-V semiconductor material, such as gallium arsenide.
`
`Semiconductor devices having substrates of the first two substrate materials have
`
`layers of Group IH-V semiconductor materials, such as gallium nitride, deposited on
`
`their substrates. The die attach process for such semiconductordie uses a gold-tin
`
`eutectic, which has a melting point of about 280 °C. Temperatures as high as about
`
`350 °C can be encounteredin the die attach process for such die. Such high
`
`temperatures are incompatible with the materials of many conventional packaging
`
`devices. Thus, what is also needed is a packaging device for semiconductordie that
`use a high-temperature die attach process.
`Manyprinted circuit assembly processes and assembly equipmentrequire the
`use of standard semiconductor device packages. Modifying such processes to use a
`
`(0006)
`
`new semiconductor device package can be expensive and can interrupt production.
`
`Therefore, what is additionally needed is a way to mount a semiconductor die that
`
`' requires a high-temperature dic attach process in-a conventional packaging device.
`
`Cree Ex. 1002
`
`Page 4
`
`Cree Ex. 1002
`
`Page 4
`
`
`
`A-70030259-1
`
`PATENT
`
`—3-
`
`[0007]
`
`The invention provides a packaging device for a semiconductordie. The
`
`Summary of the Invention
`
`packaging device includes a substrate, a mounting pad, a connecting pad and an
`interconnecting element. The substrate is substantially planar and has opposed major
`
`surfaces. The mounting pad is conductive and is located on one of the major surfaces.
`
`The connecting pad is conductive and islocated on the other of the major surfaces.
`
`The conductive interconnecting element extends through the substrate and electrically
`
`interconnects the mounting pad and the connecting pad.
`
`[0008]
`
`The packaging device has a volumethat is only a few times that of the
`
`semiconductor die and can be fabricated from materials that can withstand a high-
`
`tcmpcrature die attach process. The packaging device can be configured as the only
`packaging device of the semiconductor device. The packaging device can
`alternatively be configured as a submount for a semiconductordie that requires a
`high-temperature die attach process. The submount with attached semiconductor die
`can be handled as a conventional, albeit slightly larger, semiconductordie that is then-
`
`mounted in a conventional packaging device, such as a lead-frame based packaging
`
`device, using a conventional semiconductor device assembly process, including
`
`conventional temperatures.
`
`[0009]
`
`:
`
`_The invention also provides a semiconductor device that includes a substrate, -
`
`a mounting pad, a connecting pad, an interconnecting element and a semiconductor
`die. The substrate is substantially planar and has opposedmajor surfaces. The
`
`mounting padis conductive andis located on one of the major surfaces. The
`
`connecting pad is conductive and is located on the other of the major surfaces. The
`
`conductive interconnecting element extends through the substrate and electrically
`
`interconnects the mounting pad and the connecting pad. The semiconductordie is
`
`affixed to the mounting pad.
`
`[0010]
`
`The semiconductor device as just described can be mounted in a conventional
`
`packaging device as described above. Alternatively, the semiconductor device may
`additionally include a bonding pad, an additional connecting pad, an additional
`interconnecting element and a bonding wire. The bonding pad is conductive andis
`
`located on the one of the major surfaces. The additional connecting pad is conductive
`
`and is located on the other of the major surfaces. The additional interconnecting
`
`Cree Ex. 1002
`
`Page 5
`
`Cree Ex. 1002
`
`Page 5
`
`
`
`A-70030259-I
`
`PATENT|
`
`4.
`
`element is conductive and extends through the substrate and electrically interconnects
`
`the bonding pad and the additional connecting pad. The bonding wire extends
`
`between the semiconductor die and the bonding pad. Such a semiconductor device
`constitutes a stand-alone semiconductor device that has a low profile and that can be
`used in high packing density applications. The semiconductor device may additionally
`
`include an encapsulant that encapsulates the semiconductor die and at Icast a portion
`
`of the major surface of the substrate on which the mounting padis located.
`
`fOO11}
`
`-
`
`Brief Description of the Drawings
`Figures 1A, 1B, LC, 1D, 1E and 1F are respectively an isometric view, a side
`
`view, a front view, a top vicw, a bottom view and a cross-sectional view ofa first
`embodiment of a packaging device in accordance with the invention. The cross-
`sectional view of Figure 1F is along the section line 1F-1F in Figure 1D.
`
`Figures 2A, 2B, 2C, 2D, 2E and 2F are respectively an isometric view, a side
`
`view, a front view, a top view, a bottom view anda cross-sectional view ofa first
`
`embodiment of a semiconductor device in accordance with the invention. The cross-
`
`sectional view of Figure 2F is along the section line 2F-2F in Figure 2D.
`
`Figures 3A, 3B, 3C, 3D, 3E and 3F are respectively an isometric view, a side
`
`view, a front view, a top view, a bottom view and a cross-sectional view of a second
`embodimentof a packaging device in accordance with the invention. The cross-
`sectional view of Figure 3F is along the section line 3F-3F in Figure 3D.
`
`.
`
`Figures 4A, 4B, 4C, 4D, 4E and 4Fare respectively an isometric view, a side
`
`view, a front view, a top view, a bottom view and a cross-sectional view of a sccond
`
`embodimentof a semiconductor device in accordance with the invention. The cross-
`
`sectional view of Figure 4F is along the section line 4F-4F in Figure 4D.
`
`Figures SA-5C are side viewsillustrating a method in accordance with the
`
`invention for fabricating a packaging device for a semiconductordie.
`.
`Figure 5D is a side viewillustrating an optional additional process that may be
`
`included in the methodillustrated in Figures 5A-5C.
`
`Figures 6A-6D are side viewsillustrating a method in accordance with the
`
`invention for fabricating a semiconductor device.
`
`Cree Ex. 1002
`
`Page 6
`
`Cree Ex. 1002
`
`Page 6
`
`
`
`A-70030259-1
`
`PATENT
`
`5_
`
`[0012}
`
`Figures 1A-1F are schematic diagramsillustrating a first exemplary
`
`Detailed Description of the Invention
`
`embodiment 100 of a packaging device for a semiconductor die in accordance with
`the invention. Packaging device 100-is composed of a substrate 110, interconnecting
`elements 120 and 122, a mounting pad 130, a bonding pad 132 and connecting pads
`140 and 142 (Figure LE).
`
`[0013]
`
`Substrate 110 is substantially planar, has opposed major surfaces 112 and 114
`
`‘and defines through holes 116 and 118 that extend through the substrate between
`
`major surfaces 112 and 114. Interconnecting element 120is electrically conductive
`
`and is located in through hole 116. Interconnecting element 122 is electrically
`
`conductive andis located in through hole 118. Mounting pad 130 and bonding pad
`
`132 are electrically conductive, are separate from one another and are located on the
`
`portions of the major surface 112 of substrate 110 in which through holes 116 and 118
`
`are respectively located. Connecting pads 140 and 142 are electrically conductive, are
`
`separate from one another andare located on the portions of the major surface 114 of
`substrate 1{0 in which through holes 116 and 118 are respectively located.
`
`[0014]
`
`Mounting pad 130 and connecting pad 140areelectrically connected to
`
`opposite ends of interconnecting element 120. Thus, interconnecting element 120
`
`extending through substrate 110 in through hole 116 electrically connects mounting:
`
`pad 130 to connecting pad 140. Bonding pad 132 and connecting pad 142 are
`electrically connected to opposite ends of interconnecting element 122. Thus,
`
`interconnecting element 122 extending through substrate 110 in through hole 118
`
`electrically connects bonding pad 132 to connecting pad 142.
`
`[0015]
`
`The material of substrate 110 is a thermally-conductive ceramic such as
`
`aluminaor beryllia. In an embodiment, the material of the substrate was Kyocera®
`
`Type A440 ceramic sold by Kyocera Corp., of Kyoto, Japan. Typical dimensions of
`
`the substrate are in the range from about 0.5 mm square to about 2 mm square.
`Rectangular configurations are also possible. Alternative substrate materialsinclude
`semiconductors, such as silicon, and epoxy laminates, such as those used in printed-
`
`circuit boards. Other materials that have a high thermal conductivity and a low
`
`electrical conductivity can be used instead of those exemplified above. The coefficient
`
`of thermal cxpansion of the substrate material relative to that of the semiconductor die
`
`Cree Ex. 1002
`
`Page 7
`
`Cree Ex. 1002
`
`Page 7
`
`
`
`A-70030259-1
`
`PATENT
`
`-6-
`
`to be mounted on packaging device 100 should also be considered in choosing the
`
`substrate material.
`
`(0016]
`
`Aswill be described in more detail below, substrate 110 is part of a wafer (not
`
`shown) from which typically several hundred packaging devices 100 are fabricated by
`batch processing. After fabrication of the packaging devices, the waferis singulated
`into individual packaging devices. Alternatively, the packaging devices maybeleft in.
`
`wafer form after fabrication. In this case, singulation is not performed until after at
`
`least a die attach process has been performed to attach a semiconductordie to each
`
`mounting pad 130 on the wafer. In some embodiments, wafer-scale wire bonding,
`
`encapsulation and testing are also performed prior to singulation. Full electrical
`
`testing, including light output testing, may be performed on the wafer.
`
`[0017]
`
`The material of interconnecting elements 120, 122 is metal or another
`
`electrically-conductive material. {In an embodiment, the material of the
`
`interconnecting elementsis tungsten, but any electrically-conductive material capable
`
`of forming a low-resistance electrical connection with the pads,i-e., mounting pad
`
`130, bonding pad {32 and connecting pads 140, 142, and capable of withstanding the
`
`temperature of the die-attach process may be used. As noted above, packaging device
`
`100 may be subject to a temperature as high as about 350 °C when a gold-tin eutectic
`
`is used to attach a semiconductor die to the mounting pad 130 of the packaging
`device. Interconnecting elements 120, 122 maybe located relative to mounting pad
`
`130 and bonding pad 132, respectively, elsewhere than the centers shown. Moreover,
`
`more than one interconnecting element may be located within either or both of the
`
`mounting pad and the bonding pad.
`
`[0018]
`
`The material of pads 130, 132, 140, 142 is metal or anotherelectrically-
`
`conductive material. Important considerations in selecting the material of the pads are
`
`adhesion to substrate 110, an ability to form a durable, low-resistance electrical
`
`connection with interconnecting elements 120 and 122 and an ability to withstand the
`
`temperature of the die attach process. In an embodiment,the structure of the padsis a
`
`seed layer of tungsten covered with layer of nickel about 1.2 um to about 8.9 um
`
`thick that is in turn covered with a layer of gold about 0.75 um thick. Other metals,
`
`alloys, conductive materials and multi-layer structures of such materials can be used.
`
`[0019]
`
`Packaging device 100 is used to package a semiconductor die. A
`
`Cree Ex. 1002
`
`Page 8
`
`Cree Ex. 1002
`
`Page 8
`
`
`
`A-70030259-1
`
`PATENT
`
`_7-
`
`semiconductor device in which a semiconductor die is packaged using packaging
`
`device 100 described above will be described next.
`
`[0020]
`
`Figures 2A-2F are schematic diagramsillustrating an exemplary embodiment
`
`200 of a semiconductor device in accordance with the invention. Semiconductor
`device 200 incorporates packaging device 100 in accordance with the invention.
`Elements of semiconductor device 200 that correspond to elements of packaging
`
`device 100 described above with reference to Figures 1A-1F are indicated using the
`
`[0021]
`
`same reference numerals and will not be described again in detail.
`Semiconductor device 200 is composed of packaging device 100 described
`above with referenceto Fi gures 1A-1F, a semiconductor die 250, encapsulant 252 and
`
`a bonding wire 254. In the example shown, semiconductor die 250 embodiesa light-
`
`emitting diode and has anode and cathode electrodes (not shown) covering at least
`
`parts of its opposed major surfaces. Semiconductor die 250 is mounted on packaging:
`
`device 100 with the metallizationon its bottom major surface attached to mounting
`
`pad 130. Encapsulant 252 covers the semiconductordie and the part of the major
`
`surface 112 of substrate LOO where mounting pad 130 and bonding pad 132 are
`
`located. Bonding wire 254 extends between a bonding pad located on the top major
`
`[0022]
`
`surface of semiconductor die 250 and bonding pad 132.
`The bonding pad on the top major surface of semiconductor die 250 is
`typically part of or connected to the anode electrode of the light-emitting diode. The
`
`metallization on the bottom major surface of semiconductor die 250 typically
`constitutes the cathode electrode of the light-emitting diode. Thus, the anode electrode
`of semiconductor die 250is electrically connected to connecting pad 142 by bonding
`wire 254, bonding pad 132 and interconnecting clement 122, and the cathode |
`electrode of semiconductor die 250 is electrically connected to connecting pad 140 by
`
`mounting pad 130 and interconnecting element 120.
`Encapsulant 252 has a thickness greater than the maximum height of bonding
`
`[0023]
`
`wire 254 above major surface 112. In the example shown, the encapsulantis
`
`transparent to enable semiconductor device 200 to cmit the light generated by
`
`semiconductor die 250.
`
`[0024]
`
`Semiconductor die 250 is composed of one or more layers (not shown) of any
`
`semiconductor material composed of elements from GroupsII, II, IV, V and VI of
`
`Cree Ex. 1002
`
`Page 9
`
`Cree Ex. 1002
`
`Page 9
`
`
`
`A-70030259-1
`
`PATENT
`
`_8-
`
`the periodic table in binary, ternary, quaternary or other form. Semiconductor die 250
`may additionally include a non-semiconductor substrate material, such as sapphire,
`metal electrode materials and dielectric insulating materials, as is known in the art.
`Tn an embodiment of the above-described example in which semiconductor die
`
`[0025]
`
`250 embodiesa light-emitting diode, semiconductor die 250 is composed of a
`
`substrate of silicon carbide that supports one or more layers of (indium) gallium
`
`nitride. Such a light-emitting diode generateslight in a wavelength range extending
`
`from ultra-violet to green. The bottom major surface (not shown) of the substrate
`
`remote from the layers of (indium) gallium nitride is coated with a metallization layer
`of a gold-tin alloy. A gold-tin eutectic attaches the semiconductordie to mounting pad
`130, as described above, to provide a mechanical and electrical connection between
`
`the semiconductor die and the mounting pad.
`
`[0026]
`
`The material of bonding wire 254 is gold. A process knownin the art as low-
`
`[0027]
`
`[0028]
`
`loop wire bonding is used to connect the bonding wire between the anodeelectrode of
`
`semiconductor die 250 and bonding pad 132. Using low-loop wire bonding minimizes.
`
`the maximum heightof the bonding wire above.substrate 110, and, therefore, reduces
`
`the overall height of semiconductor device 200. Other processes for providing an
`electrical connection between a bonding pad on a semiconductordie and a bonding
`pad on a packaging device are knownin the art and may be used instead, especially in
`applications in whichdevice height is a less important consideration.
`The material of encapsulant 252 is clear epoxy. Alternative encapsulant
`
`materials include silicone. Embodiments of semiconductor device 200 that neither
`emit nor detect light can use an opaque encapsulant.
`In the example of semiconductor device 200 described above, semiconductor
`die 250 is embodied as a light-emitting diode. Semiconductor die 250 may
`
`alternatively embody another type of diode without modification to packaging device
`100. Versions of packaging device 100 may be used to package semiconductordie
`
`other than those that embody such electrical components as diodes that have only two
`electrodes. Versions of packaging device 100 may be used to package semiconductor
`
`die that embody suchelectronic circuit elements as transistors and integrated circuits
`“that have more than two electrodes. Such versions of packaging device 100 have a
`number of bonding pads, interconnecting elements and connecting pads
`
`Cree Ex. 1002
`
`Page 10
`
`Cree Ex. 1002
`
`Page 10
`
`
`
`A-70030259-1
`
`_9_
`
`PATENT |
`
`corresponding to the number of bonding pads located on the top major surface of the
`
`semiconductor die. For example, a version of packaging device 100 for packaging a
`
`semiconductor die that embodies a transistor having collector, base and emitter
`
`electrodes, and in which the substrate metallization provides the collector electrode,
`
`has two bonding pads, two interconnecting elements and two connecting pads. Wire
`
`bonds connect the emitter bonding pad on the semiconductor die to one of the
`
`bonding pads on the packaging device and the base bonding pad on the semiconductor
`
`die to the other of the bonding pads on the packaging device.
`
`[0029]
`
`The connecting pads, e.g., connecting pads 140 and 142, of embodiments of
`
`packaging device 100 having multiple connecting pads maybe arranged to conform -
`
`with an industry standard pad layoutto facilitate printed circuit layout. In such —
`embodiments, the interconnecting clements may be offset from the centers of the
`respective mounting pads, bonding pads and connecting pads to allow the connecting
`
`pad layout to conform with such a standard pad layout. In some embodiments, onc or
`
`more of the mounting pad, bonding pads and connecting pads may havea shape that
`
`differs from the regular shapesillustrated. Some irregular shapes include two main
`
`regions electrically connected by a narrow track. For example, an irregularly-shaped
`
`bonding pad includes a region to which the bonding wire is attached, a region
`
`connected to the interconnecting element and a narrow track interconnecting the two
`
`regions.
`Someversions of packaging device may accommodate two or more
`
`[0030]
`
`semiconductor die. In such versions, mounting pad 130 is sized large enough to
`
`accommodate the two or more semiconductor dic. Additionally, such versions include
`
`sufficient bonding pads, interconnecting elements and connecting pads to make the
`
`required numberofelectrical connections to the semiconductor die. Alternatively, the
`
`packaging device may include twoor more mounting pads. The mounting pads may
`
`be electrically connected to one another and thence to a common interconnecting
`
`element and connecting pad. Alternatively, each mounting pad maybeelectrically
`
`connected to a corresponding connecting pad by a respective interconnecting element.
`
`[0031]
`
`Semiconductor device 200 is used by mounting it on a printed circuit board or
`
`other substrate using conventional surface-mount techniqucs or other techniques
`
`knownin the art. Semiconductor device 200 is placed on a surface of the printed
`
`Cree Ex. 1002
`
`Page 11
`
`Cree Ex. 1002
`
`Page 11
`
`
`
`A-70030259-1
`
`PATENT
`
`—~10-
`
`circuit board with connecting pads 140 and 142 aligned with respective pads on the
`
`printed circuit board. The printed circuit board 1s then passed across a solder wave to
`
`form a solder joint between connecting pads 140 and 142 and the respective pads on
`
`the printed circuit board. Alternatively, semiconductor device 200 maybe affixed to a
`
`printed circuit board by a process knownasinfra-red reflow soldering in which a
`
`pattern of solder is applied to the printed circuit board using a stencil, semiconductor
`
`device 200 and, optionally, other components are loaded onto the printed circuit board
`and the printed circuit board assembly is irradiated with infra-red light to heat and
`
`reflow the solder. Other processes for attaching electronic components to printed
`
`circuit boards are knownin the art and may alternatively be used. Packaging device
`100 and semiconductor device 200 mayadditionally include adhesive regions on the
`major surface 114 of substrate 110 external to connecting pads 140 and 142 to hold
`
`the semiconductor device in place on the printed circuit board during soldering.
`
`(0032)
`
`In semiconductor device 200, packaging device 100 and encapsulant 252
`
`collectively have a volumethat is only about 15 times the volume of semiconductor
`
`die 250. Thus, packaging device 100 is well-suited for use in high packing density
`
`applications. Moreover, packaging device 100 is fabricated from materials capableof
`
`withstanding the high temperaturcs involved in a dic attach process that uses a gold-
`
`tin eutectic. Accordingly, packaging device 100 is well suited for packaging
`semiconductor die, such as the die of certain light-emitting devices, that require a die
`
`attach processthat uses a gold-tin eutectic.
`
`[0033]
`
`As noted above, many printed circuit board assembly processes are designed
`to use standard device packages, but many standard device packages are incapable of
`withstanding the high temperatures involved in a die attach process that uses a gold-
`
`tin eutectic. Figures 3A-3F are schematic drawings showing a second embodiment
`
`300 of a packaging device in accordance with the invention. Packaging device 300
`
`takes the form of a submountthat enables semiconductordie that are mounted using a
`
`gold-tin eutectic or other high-temperature die attach process to be mounted in
`
`conventional semiconductor device packagesthat are incapable of withstanding such
`
`high temperatures. Moreover, packaging device 300 with a semiconductor die
`
`mounted thereon can be mounted in a conventional semiconductor device package as
`
`if it were a conventional semiconductordie. This allows conventional die attach, wire
`
`Cree Ex. 1002
`
`Page 12
`
`Cree Ex. 1002
`
`Page 12
`
`
`
`A-70030259-1
`
`:
`
`PATENT
`
`_ll-
`
`bond and encapsulation processes to be used to assemble the final semiconductor
`
`device that incorporates the submount.
`
`[0034]
`
`Figures 3A-3F are schematic diagramsillustrating a second exemplary
`embodiment300 of a packaging device for a semiconductor die in accordance with
`
`the invention. Packaging device 300 takes the form of a submountfor a
`
`semiconductor die. Packaging device 300 is composedof a substrate 310, an
`
`interconnecting element 320, a mounting pad 330 and a connecting pad 340 (Figure
`3E).
`.
`
`[0035]
`
`Substrate 310 is substantially planar, has opposed major surfaces 312 and 314
`
`and defines a through hole 316 that extends through the substrate between major
`
`surfaces 312 and 314. Interconnecting element 320is electrically conductive and1s
`
`located in through hole 316. Mounting pad 330is electrically conductive andis
`located on a portion of the major surface 312 of substrate 310 in which through hole
`316 is located. Alternatively, mounting pad 330 may cover major surface 312.
`Connecting pad 340iselectrically conductive and is located on a portion of the major
`surface 314 of the substrate in which through hole 316 is located. Alternatively,
`connecting pad 340 may cover major surface 314.
`
`[0036].
`
`Mounting pad 330 and connccting pad 340 are electrically connected to
`
`opposite ends of interconnecting element 320. Thus, interconnecting element 320
`
`extending through the substrate in through hole 316 electrically connects mounting:
`
`pad 330 to connecting pad 340.
`
`[0037]
`
`Materials and other details of substrate 310, interconnecting element 320,
`
`mounting pad 330 and connecting pad 340 are the same as those of substrate 110,
`
`interconnecting element 120, mounting pad 130 and connecting pad 140,respectively,
`
`of packaging device 100 described above with reference to Figures | A-1F and will
`
`_
`
`[0038]
`
`therefore not be described again here.
`A semiconductor device in which a semiconductor die is packaged using
`packaging device 300 described above will be described next.
`
`[0039]
`
`Figures 4A-4F are schematic diagramsillustrating an exemplary embodiment
`
`400 of a semiconductordevice in accordance with the invention. Semiconductor
`
`device 400 incorporates packaging device 300 in accordance with the invention.
`
`Elements of semiconductor device 400 that correspond to elements of semiconductor
`
`Cree Ex. 1002
`
`Page 13
`
`Cree Ex. 1002
`
`Page 13
`
`
`
`A-70030259-1
`
`PATENT
`
`—|2-
`
`device 200 described above with reference to Figures 2A-2Fand of packaging device
`300 described above with reference to Figures 3A-3F are indicated using the same
`
`0040]
`
`reference numerals and will not be described again in detail.
`Semiconductor device 400 is composed of a semiconductor die 250 mounted
`on packaging device 300 described above with reference to Figures 3A-3F.In the
`
`example shown, semiconductor die 250 embodies a light-emitting diode and has
`
`anode and cathodeelectrodes (not shown) coveringat least parts of its opposed major
`
`surfaces. Specifically, semiconductordie 250 is mounted on packaging device 300
`with the metallization on its bottom major surface attached to mounting pad 330. The
`
`metallization on the bottom major surface of semiconductor die 250 typically
`constitutes the cathode electrode of the light-emitting diode. Thus, the cathode
`electrode of semiconductor die 250 is electrically connected to connecting pad 340 by
`mounting pad 330 and interconnecting element 320. The top major surfaceof
`semiconductor die 250 typically includes a bonding pad that is typically part of or
`
`connected to the anode electrode ofthe ligh