(12) United States Patent
`Bhat et al.
`
`111111
`
`1111111111111111111111111111111111111111111111111111111111111
`US006885035B2
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 6,885,035 B2
`Apr. 26, 2005
`
`(54) MULTI-CHIP SEMICONDUCTOR LED
`ASSEMBLY
`
`(75)
`
`Inventors: Jerome C. Bhat, San Jose, CA (US);
`Daniel A. Steigerwald, Cupertino, CA
`(US); Reena Khare, Sunnyvale, CA
`(US)
`
`(73) Assignee: Lumileds Lighting U.S., LLC, San
`Jose, CA (US)
`
`( *) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 09/859,154
`
`(22) Filed:
`
`May 15,2001
`
`(65)
`
`Prior Publication Data
`
`US 2001/0032985 A1 Oct. 25, 2001
`
`Related U.S. Application Data
`
`(63)
`
`(51)
`(52)
`
`(58)
`
`(56)
`
`Continuation-in-part of application No. 09/469,657, filed on
`Dec. 22, 1999, now Pat. No. 6,486,499.
`
`Int. Cl? .......................... HOlL 27/15; HOlL 29/20
`U.S. Cl. ............................. 257/99; 257/79; 257/81;
`257/88; 257/103
`Field of Search ............................... 257/79-82, 84,
`257/85, 88, 99, 103
`
`References Cited
`
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`
`Reed .......................... 257/735
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`............... 257/88
`Craford et a!.
`Myers ........................ 313/500
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`Malissin et a!.
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`......... 315/158
`............... 363/89
`Bullock et a!.
`Wychulis .................... 315/151
`Hunt eta!. ................... 257/98
`Manabe eta!. ............. 257/431
`
`DE
`DE
`EP
`EP
`EP
`EP
`EP
`EP
`EP
`EP
`EP
`GB
`GB
`JP
`JP
`JP
`JP
`JP
`
`FOREIGN PATENT DOCUMENTS
`
`197 56856 A1
`199 21 987 A1
`0 550 963 A1
`0 702414 A2
`0 772 249 A2
`0 772 249 A3
`0921577 A1
`0 926 744 A2
`926 744 A3
`1 020 935 A2
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`2301934
`2 343 994
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`7235624
`11 150 297
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`
`12/1997
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`6/1999
`6/1999
`5!2000
`7/2000
`8/2000
`12/1996
`5!2000
`11/1993
`9/1995
`6/1999
`7/1999
`10/1999
`
`........... H01L/33/00
`
`........... H01L/33/00
`........... H01L/33/00
`........... H01L/33/00
`........... H01L/33/00
`
`........... H01L/33/00
`
`........... H01L/23/48
`
`........... H01L/33/00
`
`OTHER PUBLICATIONS
`
`Roger Maxwell, "LED or Lamp Flasher: Minimum parts
`counting Designed for 3V battery operation", http:/www.ee(cid:173)
`.washington.edu/ circuit_archive/ circuits.
`
`(Continued)
`
`Primary Examiner-Nathan J. Flynn
`Assistant Examiner-Johannes Mandt
`(74) Attorney, Agent, or Firm-Patent Law Group LLP
`
`(57)
`
`ABSTRACT
`
`A light emitting device includes several LEDs, mounted on
`a shared submount, and coupled to circuitry formed on the
`submount. The LEDs can be of the III-Nitride type. The
`architecture of the LEDs can be either inverted, or non(cid:173)
`inverted. Inverted LEDs offer improved light generation.
`The LEDs may emit light of the same wavelength or
`different wavelengths. The circuitry can couple the LEDs in
`a combination of series and parallel, and can be switchable
`between various configurations. Other circuitry can include
`photosensitive devices for feedback and control of the
`intensity of the emitted light, or an oscillator, strobing the
`LEDs.
`
`36 Claims, 34 Drawing Sheets
`
`Nichia Exhibit 1011
`Page 1
`
`

`

`US 6,885,035 B2
`Page 2
`
`U.S. PATENT DOCUMENTS
`
`5,410,159 A
`5,461,425 A
`5,475,241 A
`5,557,115 A
`5,563,422 A
`5,621,225 A *
`5,744,829 A
`5,862,167 A
`5,886,401 A
`5,914,501 A
`5,955,747 A *
`5,998,232 A
`6,016,038 A
`RE36,747 E
`6,081,540 A
`6,091,085 A
`6,121,127 A
`6,133,589 A
`6,150,774 A
`6,169,294 B1
`6,333,522 B1 *
`6,384,429 B1 *
`
`4/1995
`10/1995
`* 12/1995
`9/1996
`10/1996
`4/1997
`4/1998
`1!1999
`3/1999
`6/1999
`9/1999
`12/1999
`1!2000
`6/2000
`6/2000
`7/2000
`9/2000
`10/2000
`11/2000
`1!2001
`12/2001
`5!2002
`
`Sugawara eta!. ............ 257/13
`Fowler eta!. .............. 348/294
`Harrah et a!. ................. 257/99
`Shakuda ...................... 257/81
`Nakamura eta!. ............ 257/13
`Shieh et a!.
`.................. 257/81
`Murasato eta!. ............. 257/94
`Sassa et a!. ................... 372/45
`Liu ............................ 257/678
`Antle eta!. ................... 257/99
`Ogihara eta!. ............... 257/88
`Maruska .. .. ... ... ... ... ... .. . 438/46
`Mueller et a!.
`............. 315/291
`Manabe eta!. ............. 257/431
`Nakatsu ....................... 372/45
`Lester .. ... .. ... ... ... ... ... .. . 257/98
`Shibata et a!. .............. 438/604
`Krames eta!. ............. 257/103
`Mueller et a!.
`............. 315/291
`Biing-Jye eta!. ............. 257/79
`Inoue et a!.
`.................. 257/99
`Ogihara eta!. ............... 257/88
`
`01HER PUBLICATIONS
`
`G. J. Sun and K. H. Chae, "Properties of 2,3-butanedione
`and 1-phenyl-1,2-propanedione As New Photosensitizers
`For Visible Light Cured Dental Resin Composites", Poly(cid:173)
`mer, vol. 41, pp. 6205-6212 (2000).
`Evans et al., "Edge-Emitting Quantum Well Heterostructure
`Laser Diodes with Auxiliary Native-Oxide Vertical Cavity
`Confinement," Applied Physics Letters, 67(1995) Nov. 20,
`No. 21, pp. 3168-3170.
`
`Han, H. et al.: "Electroplated Solder Joints for Optoelec(cid:173)
`tronic Applications" Electronic Components & Technology,
`1996, pp. 963-966, XP000646645.
`"Barrier Layer in the metallisation of Semiconductor Diode
`Lasers" Research Disclosure, Kenneth Mason Publications,
`Hampshire, 1994, No. 360, p. 179, XP000446545, ISSN:
`0374-4353.
`Krames et al., "High-Power Truncated-Inverted-Pyramid
`(AlxGal-x) O.SinO.SP/GaP Light-Emitting Diodes Exhibit(cid:173)
`ing>50% External Quantum Efficiency", Applied Physics
`Letter, vol. 75, No. 16, Oct. 18, 1999, pp. 2365-2367.
`Mensz, P.M. et al.: "InxGa1_xN/AlYGa1_YN violet light emit(cid:173)
`ting diodes with reflective p-contacts for high single sided
`light extraction" Electronics Letters, GB, lEE Stevenage,
`vol. 33, No. 24, Nov. 20, 1997, pp. 2066-2068,
`XP000734311, ISSN: 0013-5194.
`Tan, Q. et al.: "Soldering technology for Optoelectronic
`Packaging" Electronic Components & Technology, 1996,
`pp. 26-36, XP000646646.
`Sugawara, H. et al, "Emission Properties of InGaAIP, Vis(cid:173)
`ible Light-Emitting Diodes Employing a Multiquatum-Well
`Active Layer", Jpn. J. Appl. Phys., vol. 33 (1994) Pt. 1, No.
`10, Oct. 1994, pp. 5784-5787.
`Chang, S. J., et al, "AlGainP multiquantum well light-emit(cid:173)
`ting diodes", lEE Proc.-Optoelectron, vol. 144, No.6, Dec.
`1997, pp. 405-409.
`Benisty, H., "Impact of Planar Microcavity Effects on Light
`Extraction-Part 1: Basic Concepts and Analytical Trends",
`lEE Journal of Quantum Electronics, vol. 34, No. 9, Sep.
`1998, pp. 1612-1631.
`* cited by examiner
`
`Nichia Exhibit 1011
`Page 2
`
`

`

`U.S. Patent
`
`Apr. 26, 2005
`
`Sheet 1 of 34
`
`US 6,885,035 B2
`
`I
`
`CD
`:;::)
`tn
`
`(.!)
`
`z
`~
`
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`I
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`a.
`
`Nichia Exhibit 1011
`Page 3
`
`

`

`N
`~
`(It
`~
`b
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`00
`00
`-..a-..
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`>
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`d •
`
`PRIOR ART
`FIG.2
`n ELECTRODE
`
`SiC {CONDUCTING) SUBSTRATE
`
`BUFFER LAYER
`CONDUCTIVE
`
`~~N=~ l J ) 1 ['1 lJ 1') I j I J: I f I ( I )'I ('I lJ 1J I) I J:i"f I f I )'I ('I j') 1'1 I j I J: I :r I I: I f I )'I ~
`
`SEMI-TRANSPARENT
`
`NiAu
`
`p bon~-pad
`
`REGION
`ACTIVE
`
`Nichia Exhibit 1011
`Page 4
`
`

`

`U.S. Patent
`
`Apr. 26, 2005
`
`Sheet 3 of 34
`
`US 6,885,035 B2
`
`3.0
`
`-~
`< 2.5
`
`L.&.J
`e::::
`e:::: 2.0
`:::::>
`c..>
`0
`
`SERIES
`RESISTANCE (0)
`----0.5
`--A-1.0
`--.-2.0
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`
`~ 1.5
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`EC
`:::E 1.0
`:::::)
`::::1!:
`~
`
`0.5 -+---------T-------------.-----...J
`5
`15
`25
`35
`JUNCTION-TO-AMBIENT THERMAL RESISTANCE {°C/W)
`FIG.3
`
`Nichia Exhibit 1011
`Page 5
`
`

`

`U.S. Patent
`
`Apr. 26, 2005
`
`Sheet 4 of 34
`
`US 6,885,035 B2
`
`~~
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`
`

`

`U.S. Patent
`
`Apr. 26, 2005
`
`Sheet 5 of 34
`
`US 6,885,035 B2
`
`:z
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`
`

`

`U.S. Patent
`
`Apr. 26, 2005
`
`Sheet 6 of 34
`
`US 6,885,035 B2
`
`jSEE 6b
`
`I
`
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`
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`
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`FIG.6(a)
`
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`
`Nichia Exhibit 1011
`Page 8
`
`

`

`U.S. Patent
`
`Apr. 26, 2005
`
`Sheet 7 of 34
`
`US 6,885,035 B2
`
`Nichia Exhibit 1011
`Page 9
`
`

`

`U.S. Patent
`
`Apr. 26, 2005
`
`Sheet 8 of 34
`
`US 6,885,035 B2
`
`11
`
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`
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`
`Nichia Exhibit 1011
`Page 10
`
`

`

`U.S. Patent
`
`Apr. 26, 2005
`
`Sheet 9 of 34
`
`US 6,885,035 B2
`
`41
`
`22
`
`FIG.8
`
`Nichia Exhibit 1011
`Page 11
`
`

`

`U.S. Patent
`
`Apr. 26, 2005
`
`Sheet 10 of 34
`
`US 6,885,035 B2
`
`22
`
`FIG.9
`
`Nichia Exhibit 1011
`Page 12
`
`

`

`U.S. Patent
`
`Apr. 26, 2005
`
`Sheet 11 of 34
`
`US 6,885,035 B2
`
`I
`
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`
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`
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`
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`
`Nichia Exhibit 1011
`Page 13
`
`

`

`U.S. Patent
`
`Apr. 26, 2005
`
`Sheet 12 of 34
`
`US 6,885,035 B2
`
`Nichia Exhibit 1011
`Page 14
`
`

`

`U.S. Patent
`
`Apr. 26,2005
`
`Sheet 13 of 34
`
`US 6,885,035 B2
`
`FIG.11(a)
`
`41
`
`FIG.11 (b)
`
`Nichia Exhibit 1011
`Page 15
`
`

`

`U.S. Patent
`
`Apr. 26, 2005
`
`Sheet 14 of 34
`
`US 6,885,035 B2
`
`20
`
`10
`
`11
`
`LED CHIP
`FIG.12A
`
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`
`22
`
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`
`Nichia Exhibit 1011
`Page 16
`
`

`

`U.S. Patent
`
`Apr. 26, 2005
`
`Sheet 15 of 34
`
`US 6,885,035 B2
`
`SAPPHIRE
`
`FIG.13(a)
`
`SAPPHIRE
`
`ROUGHENED
`SURFACE
`
`FIG.13(b)
`
`FIG.13(c)
`
`Nichia Exhibit 1011
`Page 17
`
`

`

`U.S. Patent
`
`Apr. 26, 2005
`
`Sheet 16 of 34
`
`US 6,885,035 B2
`
`GaN/SiC vs GaN/SAPPHIRE INVERTED LEOs
`• 100 p.m SiC
`• 300 p.m SiC
`.. 500 p.m SiC
`
`------ 1 00 p.m SAPPHIRE
`
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`
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`c
`w
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`
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`
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`SiC ABSORPTION COEFFICIENT (em -1)
`FIG.14
`
`5
`
`Nichia Exhibit 1011
`Page 18
`
`

`

`U.S. Patent
`
`Apr. 26, 2005
`
`Sheet 17 of 34
`
`US 6,885,035 B2
`
`•
`(.!) -
`
`Nichia Exhibit 1011
`Page 19
`
`

`

`U.S. Patent
`
`Apr. 26, 2005
`
`Sheet 18 of 34
`
`US 6,885,035 B2
`
`RECTANGULAR
`
`CIRCUlAR
`
`FIG.16
`
`Nichia Exhibit 1011
`Page 20
`
`

`

`U.S. Patent
`
`Apr. 26, 2005
`
`Sheet 19 of 34
`
`US 6,885,035 B2
`
`-
`
`Nichia Exhibit 1011
`Page 21
`
`

`

`U.S. Patent
`
`Apr. 26, 2005
`
`Sheet 20 of 34
`
`US 6,885,035 B2
`
`FIG.17(b)
`
`Nichia Exhibit 1011
`Page 22
`
`

`

`U.S. Patent
`
`Apr. 26, 2005
`
`Sheet 21 of 34
`
`US 6,885,035 B2
`
`FIG.18
`
`Nichia Exhibit 1011
`Page 23
`
`

`

`U.S. Patent
`
`Apr. 26, 2005
`
`Sheet 22 of 34
`
`US 6,885,035 B2
`
`DEPOSIT Ill- ~ _ 91
`NITRIDE LAYER I
`
`-
`
`APPLY
`92 \.. APPLY ~-----~ INTERMETAL .....r 93
`CONTACTS
`DIELECTRIC
`
`APPLY SHEET v- 94
`REFLECTOR
`
`L - - - - - - - - - t APPL~=RIER v-gs
`
`97
`
`APPLY
`96 v SOLDERABLE ._ _
`METALS
`
`PATTERN
`______. SOLOERABLE
`METALS
`
`APPLY
`DIELECTRIC ~ 98
`
`PATIERN
`DIELECTRIC ~ 99
`
`FIG.19
`
`Nichia Exhibit 1011
`Page 24
`
`

`

`U.S. Patent
`
`Apr. 26, 2005
`
`Sheet 23 of 34
`
`US 6,885,035 B2
`
`APPLY SOLDER
`TO SUBMOUNT ~100
`WAFER
`
`APPLY SOLDER
`, _ . 1 05
`TO LED CHIP r-'
`
`1
`
`FORM JOINT BETWEEN ._,.-- 1 O 1
`LED AND SUBMOUNT
`
`DISPENSE UNDERFILL
`BETWEEN LED DIE ~ 102
`AND SUBMOUNT
`
`.--D-IC-E -SU_._B-MO_U_NT--.,_.r- 1 03
`WAFER
`
`~--------------~
`
`104
`
`ATTACH SUBMOUNT
`TO PACKAGE
`
`IF STEP 105
`
`106
`~
`FORM JOINT BETWEEN
`LED CHIP AND SUBMOUNT
`
`DONE
`
`107 -v DISPENSE UNDERFlLL BETWEEN
`LED CHIP AND SUBMOUNT
`
`DONE
`
`FIG.20
`
`Nichia Exhibit 1011
`Page 25
`
`

`

`U.S. Patent
`
`Apr. 26, 2005
`
`Sheet 24 of 34
`
`US 6,885,035 B2
`
`co
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`
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`
`Nichia Exhibit 1011
`Page 26
`
`

`

`U.S. Patent
`
`Apr. 26, 2005
`
`Sheet 25 of 34
`
`US 6,885,035 B2
`
`0
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`Nichia Exhibit 1011
`Page 27
`
`

`

`U.S. Patent
`
`Apr. 26, 2005
`
`Sheet 26 of 34
`
`US 6,885,035 B2
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`Nichia Exhibit 1011
`Page 28
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`

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`U.S. Patent
`
`Apr. 26, 2005
`
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`US 6,885,035 B2
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`Apr. 26, 2005
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`Sheet 28 of 34
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`US 6,885,035 B2
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`U.S. Patent
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`Apr. 26, 2005
`
`Sheet 29 of 34
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`US 6,885,035 B2
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`Nichia Exhibit 1011
`Page 31
`
`

`

`U.S. Patent
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`Apr. 26,2005
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`US 6,885,035 B2
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`Page 32
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`U.S. Patent
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`Apr. 26, 2005
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`Sheet 31 of 34
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`US 6,885,035 B2
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`

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`U.S. Patent
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`Apr. 26, 2005
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`Sheet 32 of 34
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`US 6,885,035 B2
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`Nichia Exhibit 1011
`Page 34
`
`

`

`U.S. Patent
`
`Apr. 26, 2005
`
`Sheet 33 of 34
`
`US 6,885,035 B2
`
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`
`Nichia Exhibit 1011
`Page 35
`
`

`

`U.S. Patent
`
`Apr. 26, 2005
`
`Sheet 34 of 34
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`US 6,885,035 B2
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`Nichia Exhibit 1011
`Page 36
`
`

`

`US 6,885,035 B2
`
`1
`MULTI-CHIP SEMICONDUCTOR LED
`ASSEMBLY
`
`CROSS REFERENCE TO RELATED U.S.
`APPLICATIONS
`
`5
`
`This application is a Continuation-In-Part of U.S. appli(cid:173)
`cation Ser. No. 09/469,657, filed Dec. 22, 1999 now U.S.
`Pat. No. 6,486,499, entitled "III-Nitride Light-Emiting
`Device With Increased Light Generating Capability", by
`Michael R. Krames, DanielA Steigerwald, FredA Kish Jr., 10
`Pradeep Rajkomar, Jonathan J. Wierer Jr., and Tun S. Tan,
`incorporated herein by reference.
`
`BACKGROUND
`
`2
`considerations, such as in applications where LED devices
`are integrated with other circuit elements, for example, on
`circuit boards. Higher densities are also advantageous to
`construct high power applications. Higher densities allow
`the creation of smaller LED assemblies, which resemble
`more closely an ideal point source of light; thus, the sec(cid:173)
`ondary optics, manipulating the emitted light, are simpler
`and cheaper to produce.
`
`SUMMARY
`
`35
`
`1. Field of Invention
`The present invention relates to semiconductor light emit(cid:173)
`ting devices, and more particularly, to multiple light emitting
`devices mounted on a shared submount.
`2. Discussion of Related Art
`It is known to control light emitting diodes (LEDs) to, for
`example, generate various colors, control on/off timing, or
`control brightness levels. In devices, which include LEDs
`with the three primary colors-red (R), green (G), blue
`(B)-varying the current of the three LEDs enables the 25
`generation of almost any color in the visible spectrum.
`Therefore, they are prime candidates to be used in, for
`example, color displays. Furthermore, of particular interest
`are devices capable of generating white light (consisting of
`R, G, and B components) because of their potential for 30
`replacing conventional light sources, such as light bulbs.
`Related progress includes the following works. Mueller et
`al in U.S. Pat. Nos. 6,016,038 and 6,150,774 disclose a pulse
`width modulated current control for an LED lighting
`assembly, where each current-controlled unit is uniquely
`addressable and capable of receiving illumination color
`information on a computer network. The LEDs are con(cid:173)
`trolled by a microprocessor to alter the brightness or the
`color of the generated light, for example by using pulse
`width modulated signals. This LED assembly is therefore
`capable of providing complex, predesigned patterns of light.
`However, the LEDs are packaged individually, and the
`driving logic is positioned separately from the LEDs, result(cid:173)
`ing in spatially extensive structures.
`Mizutani et al. in Japanese patent JP7235624 disclose an
`LED lamp, wherein a package is formed of transparent resin,
`and the electrodes of an inverted LED device are bonded
`directly on the conducting pathways, leading outside the
`package. However this approach relies on the creation of 50
`several individual wire bonds, and thus does not eliminate
`the number one source of failure of LED systems, the
`breakdown of the wire bonds.
`Finally, Liu et al. in U.S. Pat. No. 5,886,401 disclose an
`LED interconnection package, wherein the LED is situated 55
`on a substantially transparent substrate, having a contact
`surface with contact pads; a polymer film overlying the
`contact surface and having via openings; a substantially
`transparent support surrounding the LED and the substrate;
`and metallization overlying the polymer film and extending 60
`through the via openings for interconnecting the contact
`pads. An array of the disclosed LEDs mounted on a shared
`submount is then described. However, a switch circuit for
`controlling the LEDs is positioned outside the LED package,
`once again resulting in spatially extensive structures.
`There are areas where marked improvement is desired. A
`higher density LED architecture is desired for space
`
`40
`
`45
`
`In accordance with the present invention several LEDs are
`mounted on a shared submount and connected by circuitry
`on the submount. The submount is preferably silicon, having
`metal traces and possibly logic circuitry formed directly
`15 on/in the submount by integrated circuit fabrication tech(cid:173)
`niques.
`Some embodiments of the invention utilize compound
`semiconductor LEDs produced from column III elements of
`the periodic table, such as Al, Ga, or In and column V
`20 elements, such as Nor P. All the contact pads are on the same
`side of these devices. This inverted architecture is often
`called flip-chip design. The device is mounted on a sub(cid:173)
`mount by, for example, soldering the contact pads to cir(cid:173)
`cuitry formed in the submount. In this architecture, the
`transparent substrates of the LED devices are directed away
`from the submount, enabling the unobstructed escape of the
`generated light through the substrate. Some embodiments
`may have the substrate removed. These inverted designs
`make possible enhanced light extraction compared to the
`standard wire-bond design. Connecting the LEDs to metallic
`traces on the shared submount reduces the number one cause
`of failure of circuitry: the breakdown of the wire bonds.
`In some embodiments, the circuitry on the submount
`connects the LEDs in parallel, in series, or in a combination
`of parallel and series. Connecting LEDs in series offers an
`improved utility, because typical operating voltages for an
`AlinGaN LED are in the 2.4--4 V regime, whereas, in many
`applications the driving circuitry operates at a different
`voltage. For example, in an automobile, a 12 V battery is
`driving the circuit. Constructing a device, which connects 3
`or 4 LEDs in series, operates all LEDs in the required
`voltage range, while driven by the standard 12 V automobile
`battery.
`Some embodiments may include a switch, which is
`capable of switching the coupling of the LEDs between
`series and parallel. The utility of this architecture is that a
`change of the circuitry can adjust the device to operating at
`different input voltages.
`Some embodiments include LEDs on the same submount
`emitting a variety of wavelengths. Embodiments including
`LEDs of the three primary colors-red, green, blue-are
`capable of emitting white light, with possible applications of
`replacing regular incandescent light bulbs. Such color LEDs
`may also be used in color displays. Embodiments including
`LEDs capable of emitting, for example, ultraviolet and blue
`light with wavelengths of 420 nanometers and 470 nanom(cid:173)
`eters find useful application in dentistry, where they are used
`to cure certain materials used for fillings.
`In some embodiments the circuitry formed in the sub-
`mount includes a diode, operated in the reverse direction to
`the LED. This architecture offers good Transient Voltage
`Suppression (TVS) and thus defense against Electrostatic
`Discharge (ESD), a leading cause of circuit failure for
`65 III-nitride materials.
`In some embodiments, the submount includes a photo(cid:173)
`sensitive device that receives a portion of the emitted light
`
`Nichia Exhibit 1011
`Page 37
`
`

`

`US 6,885,035 B2
`
`3
`and a control unit. The photosensitive device measures the
`intensity of the emitted light. If the intensity is found to
`deviate from a nominal value, the control unit adjusts the
`current to the LEDs. This embodiment addresses the prob(cid:173)
`lem that LEDs exhibit a marked decline in intensity of the 5
`emitted light with time, leading, for example, to an undes(cid:173)
`ired shift of chromaticity in color display applications, or
`falling out of the prescribed intensity range in, for example,
`traffic light applications.
`
`BRIEF DESCRIPTION OF DRAWINGS
`
`10
`
`4
`FIG. 26 illustrates circuitry including LEDs, further
`involving switches.
`FIGS. 27a through 27d illustrate circuitry including
`power shunting diodes.
`FIGS. 28a and 28b illustrate circuitry involving a photo(cid:173)
`sensitive diode and a control unit.
`FIG. 29 illustrates a method of controlling the intensity of
`the emitted light.
`FIG. 30 illustrates circuitry involving a current distributor
`and a control unit.
`
`DETAILED DESCRIPTION OF THE
`EMBODIMENT
`
`15
`
`First, a detailed description of an inverted III-Nitride LED
`and a submount for one or more LEDs is provided, which
`corresponds to the disclosure in the parent application. In the
`second part of this application additional embodiments are
`20 described in detail, utilizing several inverted III-V LEDs
`mounted on a shared submount.
`
`FIG. 1 shows a prior art III-nitride light emitting device
`with a sapphire substrate.
`FIG. 2 shows another prior art III-nitride light emitting
`device with a SiC substrate.
`FIG. 3 shows maximum forward current as a function of
`the junction-to-ambient thermal resistance.
`FIG. 4 shows LED extraction efficiency as a function of
`p-electrode absorption.
`FIG. 5 shows light trapped in a prior art light-emitting
`device.
`FIGS. 6a-b illustrate the plan and cross-sectional views
`of an LED, mounted on a submount, respectively.
`FIG. 7 illustrates the plan view of an LED, mounted on a 25
`submount.
`FIG. 8 illustrates the plan view of an LED, mounted on a
`submount.
`FIG. 9 illustrates the plan view of an LED, mounted on a 30
`submount.
`FIGS. lOa-b illustrate the plan and cross-sectional views
`of an LED, mounted on a submount, respectively.
`FIGS. lla-b illustrate cross-sectional views of the
`embodiment shown in FIGS. lOa-b.
`FIGS. 12a-b illustrate the plan views of an LED and
`submount, respectively.
`FIGS. 13a--c illustrate alternate embodiments and the
`corresponding paths of light.
`FIG. 14 shows extraction efficiency of GaN/SiC inverted
`LEDs as a function of the SiC absorption coefficient.
`FIG. 15 illustrates an embodiment having an inverted
`pyramid for the superstrate.
`FIG. 16 illustrates alternate embodiments for the sub- 45
`mount.
`FIGS. 17a-b illustrate multiple series-interconnected
`light emitting structures. FIG. 17a shows a plan view of the
`structure. FIG. 17b shows the corresponding schematic
`diagram.
`FIG. 18 illustrates multiple series-interconnected light
`emitting structures connected to a submount.
`FIG. 19 illustrates a flowchart for manufacturing the
`III-nitride LED.
`FIG. 20 illustrates a flowchart for attaching the III-nitride 55
`LED to a submount.
`FIG. 21 illustrates a plurality of LEDs, mounted on a
`shared submount, coupled to circuitry.
`FIG. 22 illustrates a side view of inverted LEDs, mounted
`on a shared submount.
`FIG. 23 illustrates a side view of inverted LEDs and
`standard LEDs, mounted on a shared submount.
`FIGS. 24a, 24b and 24c illustrate different circuitry
`connecting LEDs according to the present invention.
`FIG. 25 illustrates circuitry including groups of same
`wavelength LEDs.
`
`The Inverted III-Nitride LED
`
`One fundamental limiting condition of LED operation is
`maximum junction temperature. The maximum junction
`temperature, Tfmax' is the temperature of the p-n junction
`region at which breakdown or failure occurs in some part of
`the LED or its housing. This breakdown often occurs as the
`glass transition temperature of an encapsulating epoxy or
`lens is approached, causing loss of transparency and even-
`tual melting of these materials. With such a limit established,
`ll.T1, the temperature rise from ambient to Tfmax' may be
`expressed as (assuming power conversion efficiency
`35 <<100% which is true for present-day III-nitride devices),
`
`(1)
`
`where Ta is the ambient temperature, Imax is the maximum
`operating current, and V1 is the forward voltage at that
`current, and E>1_a is the thermal resistance from the p-n
`junction to ambient. Inserting a simplified expression for Yp
`and re-writing yields
`
`where V0 is the turn-on voltage (approximately the III(cid:173)
`nitride semiconductor bandgap voltage) and Rs is the elec(cid:173)
`trical series resistance of the device. Solving for Imax yields
`
`(2)
`
`(3)
`
`40
`
`50
`
`Equation 3 is plotted in FIG. 3 for the case of V0 =2.5 V
`(corresponding to an energy bandgap of wavelength, A.-500
`nm) and Tfmax=130o C. for varying values of Rs and E>1_a·
`The range of values of these parameters is consistent with
`die dimensions of -1 mm2 and with systems that are well
`designed for heat removal. The rank in importance between
`Rs and E>1_a is determined by what portion of the graph in
`FIG. 3 is governing the application. However, in most cases
`60 in FIG. 3, a -5° C./W reduction in thermal resistance more
`efficiently increases Imax (and thus light output) than a -0.5
`Q drop in series resistance. Because series resistance derives
`from finite contact resistances and practical doping levels, it
`is difficult to reduce to arbitrarily low levels. Thus, it is clear
`65 that thermal resistance is a significant lever arm for increas(cid:173)
`ing Imax and that it must be minimized to maximize light
`generating capability.
`
`Nichia Exhibit 1011
`Page 38
`
`

`

`(5) 10
`where llint is the internal quantum efficiency and cext is the
`light extraction efficiency of the LED. Thus, with a fixed
`active region efficiency ( ll;nt), maximum light generating
`capability is obtained by maximizing extraction efficiency.
`Since both series resistance and thermal resistance of the
`LED die are inversely proportional to junction area, it is
`desirable to increase the die size to increase Imax· Scaling up
`the die geometry arbitrarily runs into practical limitations of
`primary and secondary optics sizes and power dissipation
`capability of the LED package within a lighting system.
`Instead, the die size should be chosen to make efficient use
`of the allowable power dissipation provided by the LED
`package. In typical systems, junction-to-ambient thermal
`resistances are approximately -60° C./W, as described in
`Hofler et.al., Electronics Letters 34, 1 (1998). A quick
`calculation puts an upper limit on the power dissipation of
`the LED package. Assuming an ambient temperature of 40°
`C. and a Tjmax of 130° C., the maximum input power is (130
`-40)/60=1. The maximum input power may be written
`
`30
`
`(6)
`
`5
`With Imax fixed by the limitation on junction temperature,
`the maximum light generating capability is described in
`Equation 4:
`
`US 6,885,035 B2
`
`6
`FIG. 4 shows LED extraction efficiency vs. p-electrode
`absorption for an inverted die design in comparison with the
`conventional (epitaxy-side up) device. The extraction effi-
`ciencies plotted in FIG. 4 are determined by optical ray-trace
`4
`) 5 modeling of LED die structures (1x1 mm2
`) and include
`(
`where Lmax is the maximum light output in Watts and 11 is
`measured optical properties of all the LED materials. All of
`the slope efficiency of the LED in W/A. The slope efficiency
`the inverted devices that were modeled employ sapphire
`is proportional to the external quantum efficiency, such that
`superstrates, while the conventional devices (not inverted)
`use sapphire substrates. The p-electrode absorption (x-axis)
`is defined as the percent of light absorbed per pass assuming
`illumination from an isotropic point source of light within
`the III-nitride epi layers adjacent to the p-electrode at the
`wavelength of interest. The p electrode is the dominant
`factor for light extraction because it extends almost com-
`15 pletely across the active area to provide uniform current
`injection into the p-n junction. Furthermore, the refractive
`index difference between the sapphire (n-1.8) and the III(cid:173)
`nitride epitaxial layers (n-2.4) results in a large portion of
`the light generated from the active region being totally-
`20 internally-reflected at the sapphire/III-nitride interface. The
`amount of light trapped in this waveguide is -cos((1.8/2.4t
`1 )=66% of the total generated light, for isotropic emission
`from the active region. This light is trapped and guided
`laterally along the device towards the sides of the die, as
`25 illustrated in FIG. 5. While FIG. 5 shows a conventional
`(epitaxy-up) structure, the wave guiding effect is present
`whether the die is epitaxy-up or inverted. However, because
`of absorption by the p-electrode, most of the waveguided
`light is lost before escaping the device. For this reason,
`extraction efficiency is very sensitive to p-electrode absorp(cid:173)
`tion as shown by the data plotted in FIG. 4. This is especially
`significant in large-area, e.g. >400x400 ,um 2
`, die since the
`number of passes at the p-electrode before escape is very
`large. The n electrode is also an optical loss mechanism, but
`35 is less significant because it covers less device area.
`The ray-trace modeling results shown in FIG. 4 suggest
`that inverted die designs having Ni and/or Au electrodes
`provide extraction efficiencies from 38 to 47% (A.=505 nm).
`Conventional epitaxy-side-up devices with semi-transparent
`40 NiAu electrodes have an extraction efficiency of 43%.
`Hence, a Ni and/or Au p electrode in an inverted device does
`not provide significantly improved extraction efficiency
`relative to the conventional design. For an Ag p-electrode,
`however, the inverted die exhibits a -1.7x gain in extraction
`45 efficiency over the conventional device. As shown explicitly
`in FIG. 4, to provide increased light extraction beyond a
`prior art device, the p electrode absorption in an inverted
`device should be less than 35%. Preferably, the p electrode
`absorption is less than 25%. While FIG. 4 is plotted for the
`50 case of 505 nm, the trend in extraction efficiency vs.
`p-electrode absorption is true regardless of wavelength. It is
`also important to point out that, while reflectivity is a prime
`consideration, so also is contact resistance. Poor contact
`resistance in the p electrode can result in a device with
`55 excessively high series resistance and thus reduced light
`generation capability as described by Equation 3. For 350x
`350 ,um 2 devices, a typical series resistance is -30 Q,
`corresponding to a device resistivity on the order of 4x10- 2
`Qcm2
`. The p contact resistivity should be much less than this
`60 to minimize its contribution to the