(19) HABERET CP)
`
`(12) ZS Be oe aT RR (A)
`
`(11) RPMSSS
`445842001 —352102
`(P2001 —352102A)
`(43)43B0 HF 32eR134F12A 21 (2001. 12. 21)
`
`
`
`(1) Int.cl.’
`HO1L 33/00
`23/28
`
`wal
`
`FI
`HO1L 33/00
`23/28
`
`F-TI-}* (Be)
`4M109
`5F041
`
`N
`D
`
`Som AiR HORROR OL (2 4 B)
`
`
`
`
`(21) HES
`
`#2000 —170140( P2000— 170140)
`
`(22) HBA
`
`ERRI2°F 6 A 7 A (2000. 6.7)
`
`(54) GEIOZPs) ea
`
`24)
`(57)【要約】
`CB) SY YATLRICSITHESMONY ORE
`【課題】 ダイシング工程においても電極のバリの発生
`De < BieNy 7 -YORSESBAlCLCTRYT 4 Y
`がなく樹脂パッケージの接合度を強固にしてボンディン
`TAIT VOMBEMIETE SKEBARECHKTS
`グ用ワイヤの断線を防止できる光半導体装置を提供する
`ae,
`こと。
`(RFR) MBHORR 1 ODS SRNE 2 Fi
`【解決手段】 絶縁性の基板１の外郭縁から離れた２箇
`PrcAJb—-mM—-Jb 1a, 1 belt, CHSEO0OAZ))—mh
`所にスルーホール１ａ，１ｂを開け、これらのスルーホ
`—Jbia, 1bD&7TULTHK 1 ORMFDS RMAITH
`ール１ａ，１ｂを介して基板１の表面側から裏面側に掛
`TCHR 1 ODBBKE I ARICABERO-TOSH
`けて基板１の外郭縁より内側に周縁を持つ一対の電極
`2, 3&%mML, BM3 OLC¢BARAAT 4 EB
`２，３を形成し、電極３の上に半導体発光素子４を導通
`BRT Sc cBlc+BAKART 4 ShAOSM 2 ic7
`搭載するとともに半導体発光素子４を他方の電極２にワ
`A{VECKYTFIYIL, FICE 1 ORHMOSHICH
`イヤ６でボンディングし、更に基板１の表面の全体に接
`AXN+tBREXAFRVI V 6 SHIELD SHES
`合され半導体発光素子及びワイヤ６を封止する樹脂パッ
`F-L7 EMTS.
`ケージ７を形成する。
`
`(71) HERA 000005821
`PSPeRSE
`ARAMATMA 10GBa
`(72) 32H BR aK
`BUABIA A BaRGHRGENTAeA
`1786HHO6 BABATETRASHA
`(74) RELA 100097445
`FHL a MEE 2%)
`FA—A(Bs) 4109 AAO] BAOS CA2Z1 DBIG GA0I
`BFO41 AAZS AA43 DAO? DAIS DA2O
`
`DA35 DASS DA43 DCOS DCO4
`
`DC23
`
`
`
`Nichia Exhibit 1006
`Page1
`
`Nichia Exhibit 1006
`Page 1
`
`

`

`1
`
`C HeatiaKOSH )
`【特許請求の範囲】
`(HRI 1) AaHEORROSAD SBNie 2 AT
`【請求項１】 絶縁性の基板の外郭縁から離れた２箇所
`CAJIL—-M—-JLERIF, CNHSEOAID—-K—-JLETULT
`にスルーホールを開け、これらのスルーホールを介して
`Blacest OARAD S FeRUCENT T BTSSbSDR
`前記基板の表面側から裏面側に掛けて前記基板の外郭縁
`LIN ARICAREHO-NOSMERRL, BG—MO
`より内側に周縁を持つ一対の電極を形成し、前記一対の
`BSROLICATEBBART SCCBCHMAATE HA
`電極の上に素子を導通搭載するとともに前記素子を他方
`OBMCIVORY TAIL, BicaHceROR
`の電極にワイヤでボンディングし、更に前記基板の表面
`OFAICHAS NAATRUMI VEILS Si
`の全体に接合され前記素子及び前記ワイヤを封止する樹
`KENyS-YeRMLicceRAcTSKteaR
`脂パッケージを形成したことを特徴とする光半導体装
`sg,
`置。
`( SER OFANSREA
`【発明の詳細な説明】
`(0001)
`【０００１】
`(HORS SRAGH ) AAS, KCASRHER
`【発明の属する技術分野】本発明は、たとえば表面実装
`HOF YTLED (HXSTA-E) SOXEBARE
`型のチップＬＥＤ（発光ダイオード）等の光半導体装置
`CR, RICE CHIPORBEDS < LADEE
`に係り、特に基板と封止樹脂の接着度が強くしかも電極
`NU OBNSREAOX+SAREICHT S.
`バリのない高品質の光半導体装置に関する。
`(0002)
`【０００２】
`(ROK) HHBAREOVCVIELTRHRRE
`【従来の技術】光半導体装置のひとつとして表面実装型
`OFYTFLEDMERDSHMSENTWS, COFYTL
`のチップＬＥＤが従来から知られている。このチップＬ
`EDld, @tORic BONY -VYeRmRlCtSK
`ＥＤは、絶縁性の基板に電極パターンを形成して半導体
`FKHKALEEONY-—Y LICBBRRT SC CBICIUL
`発光素子を電極パターン上に導通搭載するとともにワイ
`VRYUT IVIL, D4-V7 ESA CHE CHILG SHE
`ヤボンディングし、ワイヤを含んで樹脂で封止する樹脂
`Nv -YeBmic-BickelL, FSHyyYTickoT
`パッケージを基板に一体に接着し、ダイシングによって
`1S IORRELEBOTHS, SIYYTEnke
`１個ずつの製品としたものである。ダイシングされた後
`OFYTFTLEDOM(AS, SROMMIC-THOEBM
`のチップＬＥＤの単体は、基板の両端に一対の電極が位
`BL. —AO#BO Lic+BAKARTSESERRLT
`置し、一方の電極の上に半導体発光素子を導通搭載して
`thADEBEDTIVCRUT1YITSD. GaN
`他方の電極とワイヤでボンディングするか、ＧａＮ系化
`BYW+BREAA LESBELOLEARAATOLS
`合物半導体を利用した青色発光の半導体発光素子のよう
`CUI 74 VERERMEOMIC— DOBREHIOSO
`にサファイア基板と反対側の面に二つの電極を持つもの
`TIToNSE OMAOZEMESRAO-WHOZBICITV
`ではこれらの両方の電極が基板側の一対の電極にワイヤ
`RYT 1 YVTENS,
`ボンディングされる。
`(0003) SIFGHRISEBARAALTRUITVER
`【０００３】封止樹脂は半導体発光素子及びワイヤを保
`9 SRA CHEAXHERLASHSLOOLY AOMES
`護する役目と配光性を向上させるためのレンズの機能を
`HOtEOTC, SRE CTEA< EHESHTHILG SHE
`持つもので、基板だけでなく電極を含めて封止する形態
`DtbOUZASNTAS,
`のものが多用されている。
`(0004)
`【０００４】
`(HAMRRLKS ED SRE) CCAM, MeHOR
`【発明が解決しようとする課題】ところが、絶縁性の基
`MICS -VEBMLCSI YY IT SER, Bh
`板に電極パターンを形成してダイシングするとき、基板
`OmMAICAl CERAM ENSZOC, ZEBORMBICE
`の端面に沿って電極が形成されるので、金属の電極に下
`AZONUMHRELPIL, COKOA, SIYY TOR
`向きのバリが発生しやすい。このため、ダイシングの後
`CIANNU MU TEABE ERD TERMBA Sc ee
`にはバリ取り工程が必要となり工程数が増えることにな
`6 Ke NUMRULTEC ko CSI ERELTHE
`る。また、バリ取り工程によって電極バリを除去しても
`EOREUTHCA ECRMERORICERMA
`その除去が十分でないと表面実装の際に基板が実装面に
`WLCBNECKECRI, ZRBC LTLES,
`対して傾いた状態となり、実装精度も低下してしまう。
`(0005) Km, TKR+Y SRR LEMENYT—
`【０００５】また、エポキシ等を利用した樹脂パッケー
`Vid, BSRCORABILRHCHStO00O, FBORHH
`ジは、基板との接合度は良好であるものの、金属の電極
`RAICMSHARIR. COKO, BRO
`表面に対する接合度は比較的弱い。このため、基板の端
`BicLTNSBmeCBiRNy 7 -YCORARRL
`部に位置している電極と樹脂パッケージとの間が剥離し
`PO <, BEB y 7 -YRRRORAMNSITLES
`やすく、樹脂パッケージが基板の表面から浮いてしまう
`Céensgs, TOKO, RYT IYTENTWINSITV
`ことがある。このため、ボンディングされているワイヤ
`
`(2)
`
`10
`10
`
`20
`20
`
`30
`30
`
`40
`40
`
`50
`50
`
`AA2001-352102
` 特開２００１−３５２１０２
`2
`DSBS MNCHRLPT <<. SRVPOAC GR
`が電極から外れて断線しやすく、歩留り低下の大きな原
`Acwz4,
`因となる。
`(O006) tc, BHR, SIYYTLEICSI
`【０００６】そこで、本発明は、ダイシング工程におい
`THERON OREM < BIB 7 -YORABE
`ても電極のバリの発生がなく樹脂パッケージの接合度を
`MEIC LCRY TS 4 YTAOI1 VOMREMIETES
`強固にしてボンディング用のワイヤの断線を防止できる
`HEBARSSRHISCCEANCTS,
`光半導体装置を提供することを目的とする。
`(0007)
`【０００７】
`(REEMAT SLOOFR) AFL, MRHORR
`【課題を解決するための手段】本発明は、絶縁性の基板
`OSS5 Brie 2 BAICAIL-mM—JLEB, on
`の外郭縁から離れた２箇所にスルーホールを開け、これ
`SOAIV-K—JVEN L CHcERORAADS BHEl
`らのスルーホールを介して前記基板の表面側から裏面側
`CENT THHEEROAMSE KI ARICTRREH ONO
`に掛けて前記基板の外郭縁より内側に周縁を持つ一対の
`BGA, ii—-WOEMOLICATFeERBRRT
`電極を形成し、前記一対の電極の上に素子を導通搭載す
`SCcsilcMeATeHAOSMICI(VORYT1yY
`るとともに前記素子を他方の電極にワイヤでボンディン
`TL, SicaRORAOLSAICHA S NAATR
`グし、更に前記基板の表面の全体に接合され前記素子及
`Unie 1 VEHILS SHINY -VeRmblEce
`び前記ワイヤを封止する樹脂パッケージを形成したこと
`eA LTS,
`を特徴とする。
`(0008) ARR kHI, SPYYTLEICHIT
`【０００８】本発明によれば、ダイシング工程において
`BRONUOREMG <BR 7 -YORABES
`も電極のバリの発生がなく樹脂パッケージの接合度を強
`Alc LUCKY T 4 YTHOIUT VOMMBEMILTE SH
`固にしてボンディング用のワイヤの断線を防止できる光
`FEARRESSSTCEMNTES,
`半導体装置を得ることができる。
`(0009)
`【０００９】
`( SERORMON) FRIE 1 CaCRORARIS, ABATE
`【発明の実施の形態】請求項１に記載の発明は、絶縁性
`DERMOID 5S Brie 2 HAI AIL—-M—JLaR
`の基板の外郭縁から離れた２箇所にスルーホールを開
`It, THEOAIL—M—-JILENL THERORMAD
`け、これらのスルーホールを介して前記基板の表面側か
`5 RABICHER ONDBKEIANBICABEH
`ら裏面側に掛けて前記基板の外郭縁より内側に周縁を持
`DI-NOEMEAL. Mic-TOEMOLICATES
`つ一対の電極を形成し、前記一対の電極の上に素子を導
`BRR SC cCBicHeATehAOSBIC IT VCR
`通搭載するとともに前記素子を他方の電極にワイヤでボ
`YI* VIL, BicaAeeRORAOSACHAS Nal
`ンディングし、更に前記基板の表面の全体に接合され前
`LATROBE VEILS SHEN YT -VaB
`記素子及び前記ワイヤを封止する樹脂パッケージを形成
`LECCRHACTSHEBARECTH), SIYYT
`したことを特徴とする光半導体装置であり、ダイシング
`LEITCH SERONVUOREMANEECBICaRICM
`工程における電極のバリの発生がないとともに基板に対
`S SEN Y 7 -YORELKEHBRUII VORHEE
`する樹脂パッケージの安定した接着及びワイヤの浮き上
`PBI EHIET S CUISHEREBTS.,
`がりを防止するという作用を有する。
`(OO10) UK, BERORHOREEMHICEI
`【００１０】以下、本発明の実施の形態を図面に基づい
`THEIRS 3.
`て説明する。
`(0011) 21 dARHOREICSI SKEBARE
`【００１１】図１は本実施の形態における光半導体装置
`CH7 CRARRE O+BREARECLEMERTE
`であって表面実装型の半導体発光装置とした例を示す平
`HM. B26 10X-xX MICKSRee, B3lse
`面図、図２は図１のＸ−Ｘ’線による断面図、図３は底
`HNtHS.
`面図である。
`(0012) MIcCSiT, MRHEORMR 10 2 BPTICA
`【００１２】図において、絶縁性の基板１の２箇所に円
`WEOMMOAIL—-M—Jbia, 1behlt, cnhso
`形開口断面のスルーホール１ａ，１ｂを開け、これらの
`Alb-hK—Jb1ia,
`1 bRAICHER 1 ORMADS RH
`スルーホール１ａ，１ｂ部分に基板１の表面側から裏面
`PITH THM 2 , IMBRENTINIS, CHS5OEt
`側に掛けて電極２，３が形成されている。これらの電極
`2 , (dAORR 1 ICMLONG -VBRRENKES
`２，３は絶縁性の基板１に対してパターン形成されたも
`OC, BR1IORMDSAIV—-M—-Ib1a,
`1 b&b
`ので、基板１の表面からスルーホール１ａ，１ｂを貫通
`LCURMICZSMABKE LTBMENKEOCTHS,
`して裏面に至る断面形状として形成されたものである。
`BiMh2 , 31d. M3CmRTKDIC. BiK1 OMMKIK
`電極２，３は、図３に示すように、基板１の外郭より狭
`LISAICSENSBKCH), BK 1OMADSYLA
`い範囲に含まれる形状であり、基板１の外郭から少し内
`fC > CHALE NTS,
`側に偏って形成されている。
`(0013) BM30LbicltAgN-AFSERULT#E
`【００１３】電極３の上にはＡｇペースト５を介して半
`
`Nichia Exhibit 1006
`Page 2
`
`Nichia Exhibit 1006
`Page 2
`
`

`

`AA2001-352102
` 特開２００１−３５２１０２
`4
`
`* SS,
`＊
`きる。
`(0018) COSC. AKA SIYYILE
`【００１８】このように、本発明では、ダイシング工程
`COHM2 , 3O0NUOKEMNO<, BERN YT-Y7
`での電極２，３のバリの発生がなく、樹脂パッケージ７
`thm 1 cCMRERASHSOCITVEORYT TY
`と基板１とが安定接合されるのでワイヤ６のボンディン
`THEOREMRN, RESRIMBRICHLTS.
`グ状態の保全が図れ、製造歩留りが格段に向上する。
`(0019) @5, VLORMORET+BRHEX
`【００１９】なお、以上の実施の形態では、半導体発光
`Bl DU CHHLEM, KCAIRKCHRKLATER
`装置について説明したが、たとえば受光と発光素子を備
`A574 KRY VSOXFBARE CHP THHNCE
`えるフォトセンサ等の光半導体装置であってもよいこと
`[SLiCHS.
`は無論である。
`(0020)
`【００２０】
`(SOM) AHAT. SIYYTLEICSVSE
`【発明の効果】本発明では、ダイシング工程における電
`BONUOKERAWUOTNURUOLHEER<K TEM
`極のバリの発生がないのでバリ取りの工程を省くことが
`CHSECEBICTIUY FERSORRKEEEOST
`できるとともにプリント基板等への実装精度を高めるこ
`tMteS, Ke, BROMMBOSASHINYT—
`とができる。また、基板の外郭縁の全体を樹脂パッケー
`YORAMCTSO, BiNy 7 -YORBEERE
`ジの接合面とするので、樹脂パッケージの接合度を安定
`St CHEMIE CA SCEBICHIEFLEDT VORE
`させて剥離を防止できるとともに封止したワイヤの浮き
`EAUEMIETE, RESRIeHbetsckeMte
`上がりを防止でき、製造歩留りを向上させることができ
`3d.
`る。
`(moOms wail)
`【図面の簡単な説明】
`(31) ARROX+SAREORHOWRCH OCH
`【図１】本発明の光半導体装置の実施の形態であって半
`BAKKER CLEARSFH
`導体発光装置とした例を示す平面図
`(2) 8M10X-X RMickSo*BAKLRROMA
`【図２】図１のＸ−Ｘ’線による半導体発光装置の断面
`
`(3)
`
`3
`BRELAT 4 MERAH, HBRKRAHATIOL‘£
`導体発光素子４が導通搭載され、半導体発光素子４の上
`HOEH4 acthAOEM2 cOMe07V6Ick oT
`面の電極４ａと他方の電極２との間をワイヤ６によって
`RYF 4 YAFLTNS, ELT, BK 1 SKhORAlS,
`ボンディングしている。そして、基板１全体の表面は、
`HEARLAF 4 RVI V6 EBOTINAVICKS
`半導体発光素子４及びワイヤ６を含めてエポキシによる
`BBY 7 -Y7 IcCko THIESNTUGS,
`樹脂パッケージ７によって封止されている。
`(0014) @8, AM—-M—Ib1 a, 1 ORBICHA
`【００１４】なお、スルーホール１ａ，１ｂ部分に形成
`SNSBB2 , 3OARMAIC ISHOEE 8 AIA
`される電極２，３の円筒部分には補強用の樹脂８が充填
`ah, Bik 1 OMICItBROKOOVYIDY-LYAbF
`され、基板１の底面には絶縁のためのソルダーレジスト
`OMBMENTIIS, GH. HS OFA, KCAL
`９が形成されている。なお、樹脂８の充填は、たとえば
`ABBAOSL, HBA 11 -3572538eL
`本願出願人が提案し、特願平１１−３５７２５３号とし
`THRE Lic HAMS IciceHORISAAlCko TTBS Te
`て出願した明細書に記載の製造方法によって行なうこと
`MCES,
`ができる。
`(0015) DEOMMICHIIT, BMH2 , 3a7UY
`【００１５】以上の構成において、電極２，３をプリン
`bE OMBNY-—VicCabt CHR S¢CeBic
`ト配線基板の配線パターンに合わせて搭載するとともに
`FAUT Sc el ko CHBARAREERSN
`半田付けすることによって半導体発光装置は実装され
`6 CLC, BBC ko CEBARART 4 DK L,
`る。そして、通電によって半導体発光素子４が発光し、
`Hay 7-7 OESADS RGREORAMG
`樹脂パッケージ７のほぼ全体から一様な輝度の発光が得
`5néd,
`られる。
`(O016) cot BHRICHSIUTS, BH2 , 3lk
`【００１６】ここで、本発明においては、電極２，３は
`BR 1 OMBKIEBANAICHHO THRENTIS, CO
`基板１の外郭よりも内側に偏って形成されている。この
`KoBIENYT—L7 AMS SHITCE 1 be
`ため樹脂パッケージ７を形成する封止樹脂で基板１上を
`HILEBICSI YY TIF SCR, BH2 , 317y
`封止した後にダイシングするとき、電極２，３はダイシ
`YIBDSENTWNSOC, CHSO0RM2 , 3 icity
`ング面から離れているので、これらの電極２，３には剪
`MORI, Lieto, Bi2 , 3cltrryy7
`断が及ばない。したがって、電極２，３にはダイシング
`BCENUMBEFSTEMA<. NUREOLEMA
`後でもバリが発生することがなく、バリ除去の工程が不
`BteoeccticF7uUyY beak LAORRKEES
`要となるとともにプリント配線基板上への実装精度を高
`HScEMTES,
`めることができる。
`(0017) Ke, BiENyT-Y 7 (SEROEH 2 ,
`【００１７】また、樹脂パッケージ７は金属の電極２，
`3ORMEAOTERIOLICHSSNSM BRIO
`３の表面を含めて基板１の上に接合されるが、基板１の
`MerCitBw2 , SUBLET, COED,
`外縁部分には電極２，３は位置していない。このため、
`SROEM2 , 3 CHHORARISIRHELID, HS
`金属の電極２，３と樹脂の接着度は比較的弱いが、ガラ
`ZAABMSORM 1 COMBE BS, Litto
`ス布基材等の基板１との接着度は強くなる。したがっ
`CT. BIEN YT —-L7 OBBEAD TER 1 CRE
`て、樹脂パッケージ７の外縁部分も含めて基板１に強固
`cHAShH, MRLIC< CBD, RELKHRAMHHS
`に接合され、剥離しにくくなり、安定した接合が維持さ
`NECECBICIT VE ORELMVITH SHREMIET*
`＊
`れるとともにワイヤ６の浮き上がりによる断線も防止で
`
`10
`10
`
`20
`20
`
`30
`30
`
`(1)
`【図１】
`
`
`
`x (
`図 【
`
`23) +SA4#XREORAN
`図３】半導体発光装置の底面図
`(5S O80)
`【符号の説明】
`1 Bk
`１ 基板
`1a,1b AJb-R—-IL
`１ａ，１ｂ スルーホール
`2,3,4a ih
`２，３，４ａ 電極
`FERRARA
`４ 半導体発光素子
`AgnX-Azk
`５ Ａｇペースト
`I4v
`６ ワイヤ
`HRN 7 -D
`７ 樹脂パッケージ
`ASHE
`８ 樹脂
`YIVS-LYAF
`９ ソルダーレジスト
`
`woonnAWU
`
`【図２】
`
`
`
`Nichia Exhibit 1006
`Page 3
`
`Nichia Exhibit 1006
`Page 3
`
`

`

`(4)
`
`AA2001-352102
` 特開２００１−３５２１０２
`
`【図３】
`
`
`
`Nichia Exhibit 1006
`Page 4
`
`Nichia Exhibit 1006
`Page 4
`
`

`

`(19) Japan Patent Office (JP)
`
`(12) Japanese Unexamined Patent
`Application Publication (A)
`
`(51) Int. Cl.7
`
`Identification codes
`
`F1
`
`(11) Japanese Unexamined Patent
`Application Publication Number 2001-352102
`(P2001-352102A))
`(43) Publication Date: December 21, 2001
`(2001.12.21)
`
`Theme Codes (Reference)
`
`
`
`
`
`
`Request for Examination: Not yet requested Number of Claims: 1 OL (Total of 4 pages)
`(71) Applicant 000005821
`(21) Application Number Japan Patent Application 2000-170140
`
`
`
`Matsushita Electric Industrial Co., Ltd.
`(P2000-170140)
`
`
`1006 Oaza Kadoma, Kadoma-shi,
`
`
`
`
`Osaka-fu Japan
`(22) Date of Application June 7, 2000 (2000.6.7)
`(72) Inventor Makoto Nozoe
`
`
`c/o Kagoshima Matsushita Electronics Co., Ltd.
`
`
`1786-6 Aza Maedaira, Oaza
`
`
`Tokushige, Ijuin-cho, Hioki-gun,
`
`
`Kagoshima-ken Japan
` (74) Agent
`100097445
`
`
`Patent Attorney Fumio Iwahashi (and 2 others)
`F terms (reference)
`
`
`
`
`
`
`
`
`
`
`
`
` (54) [Title of the Invention] Optical Semiconductor Device
`
`(57) [Abstract]
`[Problem] To provide an optical semiconductor device wherein a burr
`is not generated on the electrodes in the dicing step, the bonding level
`of resin package is reinforced, and breakage of the bonding wire can
`be prevented.
`[Means for Solving the Problem] Through holes 1a and 1b are opened
`in two places away from outer edge of insulating substrate 1, one pair
`of electrodes 2 and 3 are formed which have peripheral edge inside the
`outer edge of substrate 1 from the surface side of the substrate 1 to the
`back side via these through holes 1a and 1b, a semiconductor light
`emitting element 4 is conductively mounted on the electrode 3 as well
`as the semiconductor light emitting element 4 is bonded to the other
`electrode 2 by a wire 6 and further a resin package 7 which is bonded
`to the entire surface of substrate 1 and seals the semiconductor light
`emitting element and wire 6 is formed.
`
`
`
`
`
`
`
`Nichia Exhibit 1006
`Page 5
`
`

`

`(2)
`
`Japanese Unexamined Patent Application Publication Number 2001-352102
`
`package is strengthened, and disconnection of the bonding wire
`can be prevented.
`[0007]
`[Means of Solving the Problem] This invention is characterized
`with opening two through holes away from the outer edge of an
`insulating substrate, forming one pair of electrodes having
`peripheral edges inside the outer edge of the substrate from the
`surface side of the substrate to the back side via these through
`holes, conductively mounting an element on one of the pair of
`electrodes as well as bonding the element to the other electrode
`with a wire and further forming a resin package which is bonded
`to the entire surface of the substrate and seals the element and the
`wire.
`[0008] According to this invention, an optical semiconductor
`device can be obtained wherein a burr on the electrode is not
`generated, even in a dicing process, the bonding level of resin
`package is strengthened, and prevention of disconnection of the
`bonding wire.
`[0009] [Embodiment of the Invention] The invention described in
`Claim 1 is an optical semiconductor device characterized with
`opening two through holes away from the outer edge of an
`insulating substrate, forming one pair of electrodes having
`peripheral edges inside the outer edge of the substrate from the
`surface side of the substrate to the back side via these through
`holes, conductively mounting an element on one of the pair of
`electrodes as well as bonding the element to another electrode by
`a wire and further forming a resin package which is bonded to the
`entire surface of the substrate and seals the element and the wire,
`and has the function of not generating a burr on the electrode
`during the dicing process, stabilizing of the adhesive of resin
`package with the substrate and preventing the uplifting of the
`wire.
`[0010] An embodiment of this invention is described hereafter
`based on the drawings.
`[0011] Fig. 1 is an optical semiconductor device of this
`embodiment and a plane view showing an example of a surface
`mount type semiconductor light emitting device, Fig. 2 is a cross
`sectional view with the X – X’ line in Fig. 1 and Fig. 3 is a
`bottom view.
` [0012] In the drawings, through holes 1a and 1b with a circular
`opening cross section are opened in two places in the insulating
`substrate 1, and electrodes 2 and 3 are formed on these through
`holes 1a and 1b from the surface side to the back side of substrate
`1. These electrodes 2 and 3 are formed in a pattern against
`insulating substrate 1 and are formed in cross section shape from
`the surface of substrate 1, penetrating the through holes 1a and 1b
`to the back. The electrodes 2 and 3 are in a shape that includes a
`range narrower than the outer edge of substrate 1 and are formed
`biased slightly toward inside the outer edge of substrate 1, as
`shown in Fig. 3.
` [0013] A semiconductor light emitting element 4 is conductively
`mounted on electrode 3 with Ag paste 5 and the electrode 4a on
`the top side of the semiconductor light emitting element 4 and the
`other electrode 2 are bonded by a wire 6. And the surface of
`entire substrate 1 is encapsulated with resin package 7 with epoxy,
`including the semiconductor light emitting element 4 and the wire
`6.
`[0014] Meantime, the cylindrical parts of electrodes 2 and 3
`formed in the through holes 1a and 1b are filled by resin 8 for
`reinforcement and a solder resist 9 is formed on the bottom of
`substrate 1 for insulation. Meantime, filling with resin 8 can be
`3
`
`1
`
`[Scope of Patent Claims]
`[Claim 1] An optical semiconductor device characterized in that
`opening two through holes away from outer edge of an insulating
`substrate, forming one pair of electrodes having their peripheral
`edges inside the outer edge of the substrate, from the surface side
`of the substrate to the back side via these through holes,
`conductively mounting an element to one of the pair of electrodes
`as well as bonding the element to another electrode by a wire and
`further forming a resin package which is bonded to the entire
`surface of the substrate and which seals the element and the wire.
`[Detailed Description of the Invention]
`[0001] [Field of the Invention] This invention is related to an
`optical semiconductor device, for example, a surface mount type
`chip LED (light emitting diode), etc., and especially relates to a
`high quality optical semiconductor device with a strong bonding
`level of the sealing resin and substrate, furthermore without
`electrode burrs.
`[0002] [Conventional Technology] A surface mount type chip
`LED is known as one of optical semiconductor device. This chip
`LED is a product wherein an electrode pattern is formed on an
`insulating substrate, a semiconductor light emitting element is
`conductively mounted on the electrode pattern as well as a wire is
`bonded, a resin package for sealing by resin, including wire is
`adhered to the substrate integrally and it becomes an individual
`product by dicing. A chip LED unit after dicing has one pair of
`electrodes placed on both ends of the substrate and either a
`semiconductor light emitting element is conductively mounted on
`one of electrodes and the other electrode is bonded by wire, or in
`the case of having two electrodes on the side opposite a sapphire
`substrate for a semiconductor light emitting element emitting blue
`light using a GaN based compound semiconductor, both of these
`electrodes are bonded by wire to one pair of electrodes on the
`substrate side.
`[0003] An encapsulating resin has role of protecting the
`semiconductor light emitting element and wire and a function as a
`lens to improve optical distribution, and a type that encapsulates
`not only the substrate but also includes the electrodes is used
`often.
`[0004] [Problems to be Resolved by the Invention] However,
`when dicing after forming an electrode pattern on the insulating
`substrate, a burr facing downward is likely to be generated on the
`metal electrode because the electrode is formed along the end
`surface of the substrate. For this reason, a deburring step is
`needed after dicing, which results in an increase in the steps. Also,
`even though the burr of the electrode is eliminated with the
`deburring step, if the elimination is not sufficient, the substrate
`will have an angle in relation to the mounted surface when
`surface mounting and mounting accuracy will also be decreased.
`[0005] Also, a resin package using epoxy, etc. has a good
`bonding level with the substrate, however, the bonding level with
`the metal electrode surface is relatively weak. As a result, the area
`between the electrode located at the end of the substrate and the
`resin package is likely to be exfoliated and the resin package may
`detach from the surface of substrate. For this reason, the bonded
`wire separates from the electrode and is likely to become
`disconnected, resulting in a major reason for reduction in yield.
`[0006] Therefore, this invention has a purpose of providing an
`optical semiconductor device wherein a burr on the electrode is
`not generated, even in a dicing process, the bonding level of resin
`
`
`
`
` 2
`
`Nichia Exhibit 1006
`Page 6
`
`

`

`(3)
`done by the production technique proposed by this applicant and
`described in the specification filed as Japanese Patent Application
`No. 1999-357253.
`[0015] In the structure mentioned above, a semiconductor light
`emitting device is implemented by mounting as well as soldering
`the electrodes 2 and 3 in conformity with the wiring pattern of the
`printed circuit board. And, the semiconductor light emitting
`element 4 emits light by the passage of electricity, and uniform
`luminance can be obtained from almost the entire resin package 7.
`[0016] Here, in this invention, the electrodes 2 and 3 are formed
`biased toward the inside of the outer edge of substrate 1. As a
`result, when dicing after sealing on the substrate 1 with the
`sealing resin forming the resin package 7, shearing doesn’t reach
`the electrodes 2 and 3 because these electrodes 2 and 3 are away
`from the dicing side. Therefore, a burr isn’t generated on the
`electrodes 2 and 3 even after dicing, a deburring process is not
`needed and implementation accuracy on the printed circuit board
`can be increased.
`[0017] Also, the resin package 7 is joined to the substrate 1,
`including the surface of metal electrodes 2 and 3 but the
`electrodes 2 and 3 are not located on the outer edge of substrate 1.
`For this reason, the adhesive level with the metal electrodes 2 and
`3 and the resin is relatively weak, but the adhesive level with the
`substrate 1 such as glass fabric board material, etc. is stronger.
`Therefore, it is solidly joined to the substrate 1 including the outer
`edge part of the resin package 7, which creates a joining that is
`stable and hard to separate, as well as preventing a disconnection
`due to uplifting of the wire 6.
`[0018] In this way, with this invention, there is no generation of
`burrs on the electrodes 2 and 3 in the dicing process, the resin
`package 7 and the substrate 1 are stably joined so the bonding
`state of the wire 6 is maintained and the production yield is
`improved substantially.
`
`
`[Fig. 1]
`
`Japanese Unexamined Patent Application Publication Number 2001-352102
`4
`[0019] Meantime, the embodiment above is described regarding a
`semiconductor light emitting element, but this can be of course an
`optical semiconductor device with, for example, a photosensor
`with light receiving and light emitting elements.
`[0020]
`[Effects of Invention] In this invention, a deburring process can
`be omitted because there is no burr generation on the electrode in
`the dicing process as well as the implementation accuracy on a
`printed circuit board can be increased. Also, exfoliation can be
`prevented by stabilizing the bonding level of the resin package
`because the entire outer edge of the substrate is a bonding surface
`of the resin package, separation of the bonding wire can be
`prevented, and the production yield can be improved.
`[Brief Explanation of Drawings]
`[Fig. 1] A plane view showing an example of a semiconductor
`light emitting device wherein it is an embodiment of an optical
`semiconductor device in this invention
`[Fig. 2] A cross sectional view of a semiconductor light emitting
`device with the X - X’ line in Fig. 1
`[Fig. 3] A bottom view of a semiconductor light emitting device
`[Description of the Reference Numerals]
`1 Substrate
`1a, 1b Through holes
`2, 3, 4a Electrodes
`4 Semiconductor light emitting element
`5 Ag paste
`6 Wire
`7 Resin package
`8 Resin
`9 Solder resist
`
`
`
`[Fig. 2]
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Nichia Exhibit 1006
`Page 7
`
`

`

`(4)
`
`Japanese Unexamined Patent Application Publication Number 2001-352102
`
`[Fig. 3]
`
`
`
`Nichia Exhibit 1006
`Page 8
`
`

`

`Translator’s Declaration
`
`I, Jeff Bunderson, hereby declare:
`
`That I possess advanced knowledgeof the Japanese and English languages. My qualifications are
`as follows:
`
`* Worked asa freelance translator for 18 years
`
`* BA in Japanese from Brigham Young University
`
`* 4.5 years working for Intel in Japan in Planning and Marketing
`
`* 3.5 years working for NEC Electronicsas a Field Sales Engineer
`
`The attached translationis, to the best of my knowledge andbelief, a true and accuratetranslation
`from Japanese to English ofthe patent publication titled “3° (4Hf (Optical Semiconductor
`Device) - JPA_2001-352102 (Matsushita).
`I understand that willful false statement and the like
`are punishable by fine or imprisonment, or both (18 U.S.C. 1001) and may jeopardize the validity
`of the application or any patent issuing thereon.
`I declare under penalty of perjury that all
`statements made herein of my own knowledgeare true andall statements made on information
`andbelief are believed to be true.
`
`Date: May 29, 2018
`
`
`
`Byuinderson
`
`
`
`Nichia Exhibit 1006
`Page 9
`
`Nichia Exhibit 1006
`Page 9
`
`