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`
`USOOS87034UA
`
`United States Patent
`Ohsawa
`
`[19]
`
`[11] Patent Number:
`
`5,370,340
`
`[45] Date of Patent:
`
`Feb. 9, 1999
`
`[S4] MULTIPLEXER
`
`[75]
`
`Inventor: TakashiOhsawa,Yokohama,_lapan
`
`[73] Assignee: Kabushiki Kaisha Toshiba, Kawasaki,
`Japan
`
`[2|] Appl. No: 889,441
`
`[22
`
`Filed:
`
`Jul. 8, 1997
`
`Related US. Application Data
`
`[(12] Division of Ser. No. 703.036, Dec. 10, 19.06, Pat. No.
`5,701,095, which is a continuation ofSer. No. 393,076, Feb.
`2.3, 1995, abandoned.
`
`[30]
`
`Foreign Application Priority Data
`
`Felt. 25, 1994
`
`[JP]
`
`Japan ................................. 6—028593
`
`Int. Cl? ....................................................... GllC 7100
`[51]
`[52] U.S. Cl.
`...................... 365189.02; 3635201; 365203
`[58]
`Field of Search ............................... 3651189112, 201,
`365203, 189.05, 190
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`4,280,212
`4,645,944
`
`......................... 327.1410
`7,!1081 Ransom et al.
`2ft 987 Uya ......................................... 327.3410
`
`363189.02
`llr'1989 Wyland
`4,882,709
`.365i’18€}.02
`12.31989 Frederick
`4,888,739
`4f1991 Feldbuumer at at.
`..... 307i243
`5,012,126
`
`.....
`3531mm
`1131993 Mills el al.
`5,262,990
`5it995 Hastie et a1.
`.
`.. 32711408
`5,418,480
`
`. 365.-'189,t.12
`311996 I-‘cng
`5.491347
`
`. 365189.02
`3,1181% Marchioro
`5,502,633
`365,-‘189JIZ
`[(151996 Rutlas
`5,510,320
`FOREIGN PATENT DOCUMENTS
`
`(I 593 152
`t] 615 251
`
`4,11994 European Pat. OH. .
`931994
`European Fat. 00'. .
`
`Primary examiner—tan ’1‘. Nguyen
`Airtime}; Agent, or Firm—Banner & Witcoi’f, Ltd.
`
`[57]
`
`ABSTRACT
`
`A semiconductor integrated circuit device has a data select-
`ing circuit connected to a first power supply terminal, a
`precharge circuit, connected to a second power supply
`terminal. for receiving a precharge signai, and a wiring line
`connected to a common connection point between the data
`selecting circuit and the precharge circuit. The data selecting
`circuit
`includes at
`least
`two,
`i.e.,
`lirsl and second data
`transmission circuits. A first
`input data signal and a tirst
`selecting signal are supplied to the lirst data transmission
`circuit. A second input data signal and a second selecting
`Signai are supplied to the second data transmission circuit.
`
`25 Claims, 27 Drawing Sheets
`
`ADDRESS
`
`A
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`
`INTEL 1219
`
`

`

`US. Patent
`
`Feb. 9, 1999
`
`Sheet 1 01'27
`
`5,870,340
`
`
`
`F l G.
`
`1
`
`(PRIOR ART)
`
`
`
`F l G.
`
`2 (PRIOR ART)
`
`

`

`US. Patent
`
`Feb. 9, 1999
`
`Sheet 2 of 27
`
`5,870,340
`
`
`
`
`DATA SELECTING CIRCUIT
`
`100
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`SIGNAL
`
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`PRECHARGE
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`'
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`FIG.
`
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`
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`

`

`US. Patent
`
`Feb. 9, 1999
`
`Sheet 3 01'27
`
`5,870,340
`
`®-—- PRECHARGE PERIOD
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`

`

`US. Patent
`
`Feb. 9, 1999
`
`Sheet 4 of 27
`
`5,870,340
`
`
`
`
`7
`FIG.
`(PRIOR ART)
`
`

`

`US. Patent
`
`Feb. 9, 1999
`
`Sheet 5 01'27
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`5,870,340
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`US. Patent
`
`Feb. 9, 1999
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`US. Patent
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`Feb. 9, 1999
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`5,870,340
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`US. Patent
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`Feb. 9, 1999
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`US. Patent
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`Feb. 9, 1999
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`5,870,340
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`US. Patent
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`Feb. 9, 1999
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`Sheet 19 M27
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`5,870,340
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`US. Patent
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`Feb. 9, 1999
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`Sheet 20 0f 27
`
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`Feb. 9, 1999
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`US. Patent
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`Feb. 9, 1999
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`Sheet 26 0f27
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`5,870,340
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`5,870,340
`
`1
`MULTIPLEXER
`
`This application is a divisional of application Ser. No.
`08363336, filed Dec. 10, 1996 now US. Pat. No. 5,701,
`095, which is a continuation of application Ser. No. 08893,
`076, filed Feb. 23, 1995, now abandoned.
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`The present invention relates to a semiconductor inte-
`grated circuit device and, more particularly, to a semicon-
`ductor integrated circuit device in which a plurality of signal
`lines are integrated into a single signal line.
`2. Description of the Related Art
`Currently, multiplexers are used as semiconductor inte-
`grated circuit devices in which a plurality of signal lines are
`integrated into a single signal line.
`In the multiplexer, a
`signal line is selected from the plurality of signal lines, and
`the selected signal line is electrically connected to the single
`signal line.
`As a multiplexer consisting of a CMOS transistor circuit,
`a transfer gate type multiplexer as shown in FIG. 1, or a
`clocked inverter type multiplexer as shown in FIG. 2 has
`been considered. In either type multiplexer, from selecting
`signals a, Ba, L), Bl}, g, Bc, d, and Ed (the prefix “B"
`represents an inverted signal), data corresponding to a signal
`of high level is selected and transmitted to a common node
`X serving as an output terminal. Note that signals A to D are
`input data signals, and a signal 0 is an output data signal.
`In the multiplexer shown in FIG. 1 or 2, however, if the
`nu mber of to—be»selected data is large, parasitic capacitances
`such as a junction capacitance and a gate capacitance added
`to the common node X increase. For this reason, a high
`speed data selecting operation to select and output the input
`data may be impaired.
`SUMMARY 0F '11 IE INVENTION
`
`It is the first object of the present invention to provide a
`semiconductor integrated circuit device capable of operating
`at a high speed even when the number of to-be-selected data
`is large.
`It is the second object of the present invention to provide
`a semiconductor integrated circuit device which achieves the
`first object and prevents an erroneous Operation caused by
`noise.
`
`It is the third object of the present invention to provide a
`semiconductor memory device which uses the above semi-
`conductor integrated circuit device to operate at a high
`speed.
`It is the fourth object of the present invention to provide
`a semiconductor memory device which uses the above
`semiconductor integrated circuit device to simplify a test
`circuit.
`
`In order to achieve the first object, according to the
`present invention, there is provided a semiconductor intev
`grated circuit device having a data selecting circuit con-
`nected to a first power supply terminal, a precharge circuit,
`connected to a second power supply terminal, for receiving
`a precharge signal, and a wiring line connected to a common
`connection point between the data selecting circuit and the
`precharge circuit. The data selecting circuit includes at least
`two, i.e., first and second data transmission circuits. A first
`input data signal and a first selecting signal are supplied to
`the first data transmission circuit. A second input data signal
`and a second selecting signal are supplied to the second data
`transmission circuit.
`
`10
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`tances added to the common node of the semiconductor
`integrated circuit device with the above arrangement are
`present only at a connection point between the first data
`transmission circuit and the common node. a connection
`point between the second data transmission circuit and the
`common node, and a connection point between the pre—
`charge circuit and the common node. Therefore, the parasitic
`capacitances added to the common node are decreased to
`allow the high-speed operation of the semiconductor inte-
`grated circuit device.
`In order to achieve the second object, according to the
`present invention, there is provided a semiconductor inte-
`grated circuit device in which a potential fixing circuit for
`fixing the potential of a common node at a predetermined
`potential is connected to the common node.
`In the semiconductor integrated circuit device with the
`above arrangement, the potential of the common node is set
`at
`21 Floating level during a certain period from the OFF
`timing of the precharge circuit to the ON timing of the data
`transmission circuit. When the potential fixing circuit
`is
`connected to the common node, the potential of the common
`node can be fixed at a predetermined potential while the
`potential of the common node is at a floating level.
`Therefore, the semiconductor integrated circuit device can
`prevent an erroneous operation caused by noise.
`In order to achieve the third object, the semiconductor
`integrated circuit device which achieves the first or second
`object is used as the data multiplex circuit of a semicon-
`ductor memory device.
`In the semiconductor memory device with this
`arrangement, the parasitic capacitances of the data multiplex
`circuit are decreased. Therefore, the semiconductor memory
`device operates at a high speed.
`In order to achieve the fourth object, in addition to a
`normal mode in which an input data signal is selected in
`accordance with a selecting signal, a test mode in which all
`input data signals are selected in accordance with a selecting
`signal
`is provided. The semiconductor integrated circuit
`device which achieves the first or second object can perform
`an OR operation by simultaneously transmitting all the input
`data signals to the common node. By using the 0R operation
`function, correctlerroneous data is determined.
`In the semiconductor memory device with the above
`arrangement, the multiplex circuit can be used as the OR
`operation circuit of the test circuit, thereby simplifying the
`test circuit.
`
`Additional objects and advantages of the invention will be
`set forth in the description which follows, and in part will be
`obvious from the description, or may be learned by practice
`of the invention. The objects and advantages of the invention
`may be realized and obtained by means of the instrumen‘
`talities and combinations particularly pointed out
`in the
`appended claims.
`BRIEF DESCRIPTION OF TI IE DRAWINGS
`
`The accompanying drawings, which are incorporated in
`and constitute a part of the specification, illustrate presently
`preferred embodiments of the invention and, together with
`the general description given above and the detailed descrip-
`tion of the preferred embodiments given below, serve to
`explain the principles of the invention.
`FIG. 1 is a circuit diagram of a conventional multiplexer;
`FIG. 2 is a circuit diagram of another conventional
`multiplexer;
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`FIG. 3 is a block diagram of a semiconductor integrated
`circuit device according to the first embodiment of the
`present invention;
`FIG. 4 is a circuit diagram of the semiconductor inte—
`grated device according to the first embodiment of the
`present invention;
`FIG. 5 is a chart showing the operating waveforms of the
`semiconductor integrated circuit device according to the first
`embodiment of the present invention;
`FIG. 6 is a view showing the parasitic capacitances of the
`semiconductor integrated circuit device according to the first
`embodiment of the present invention;
`FIG. 7 is a view showing the parasitic capacitances of the
`conventional multiplexer shown in FIG. 1;
`FIG. 8 is a view showing the parasitic capacitances of the
`conventional multiplexer shown in FIG. 2;
`FIG. 9 is a block diagram of a DRAM according to the
`second embodiment of the present invention;
`FIG. II] is a block diagram ol'a 16 Mhil-cell array shown
`in FIG. 9;
`FIG. 11 is a block diagram of a 256 kbit—cell array shown
`in FIG. 10;
`FIG. 12 is a circuit diagram of a DO buffer shown in FIG.
`10;
`FIG. 13 is a chart showing the operating waveforms of the
`DO buffer shown in FIG. 12;
`FIG. 14 is a block diagram of a read multiplexer & write
`multiplexer shown in FIG. 9;
`FIG. 15 is a circuit diagram of a multiplex signal gener-
`ating circuit shown in FIG. 14;
`FIG. 16 is a block diagram of the read multiplexer shown
`in FIG. 14;
`FIG. 17 is a circuit diagram of the multiplex circuit of a
`first multiplex stage shown in FIG. 16;
`FIG. 18 is a circuit diagram of the multiplex circuit of a
`second multiplex stage shown in FIG. 16;
`FIG. 19 is a block diagram of the read multiplexer of a
`DRAM capable of changing the number of output bits;
`FIG. 20 is a circuit diagram of a switch circuit shown in
`FIG. 19;
`FIGS. 21 and 22 are charts showing the operating wave-
`forms of the read multiplexer shown in FIG. 16;
`FIG. 23 is a circuit diagram of a test circuit shown in FIG.
`
`9;
`
`FIG. 24 is a circuit diagram of a selecting circuit shown
`in FIG. 9;
`FIGS. 25 and 26 are circuit diagrams schematically show—
`ing the multiplex circuit shown in FIG. 17;
`FIG. 27 is a block diagram of the write multiplexer shown
`in FIG. 14;
`FIG. 28 is a circuit diagram of a selecting circuit shown
`in FIG. 27;
`FIG. 29 is a block diagram of a DRAM according to the
`third embodiment of the present invention;
`FIG. 30 is a block diagram ofa 16 Mbit-cell array shown
`in FIG. 29;
`FIG. 31 is a circuit diagram of the multiplex circuit of a
`first multiplex stage provided to the DRAM according to the
`third embodiment of the present invention;
`FIG. 32 is a circuit diagram of the multiplex circuit of a
`second multiplex stage provided to the DRAM according to
`the third embodiment of the present invention;
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`FIG. 33 is a circuit diagram of a semiconductor integrated
`circuit device according to the fourth embodiment of the
`present invention;
`FIG. 34 is a circuit diagram of a selecting circuit shown
`in FIG. 33;
`FIG. 35 is a circuit diagram of a semiconductor integrated
`circuit device according to the fifth embodiment of the
`present invention;
`FIG. 36 is a circuit diagram of a semiconductor integrated
`circuit device according to the sixth embodiment of the
`present invention;
`FIG. 37 is a chart showing the operating waveforms of the
`semiconductor integrated circuit device according to the
`sixth embodiment of the present invention; and
`FIG. 38 is a circuit diagram of a semiconductor integrated
`circuit device according to the seventh embodiment of the
`present invention.
`
`DETAILED DESCRIPTION OF T] IE
`PREFERRED EMBODIMENTS
`
`The present invention will be described below in accor-
`dance with prefcrrcd embodiments. The same reference
`numerals and symbols denote the same elements throughout
`the drawings, and a detailed description thereof will be
`omitted.
`
`FIG. 3 is a block diagram of a semiconductor integrated
`circuit device according to the first embodiment of the
`present invention. FIG. 4 is a circuit diagram of the semi—
`conductor integrated circuit device according to the first
`embodiment.
`
`As shown in FIG. 3, the integrated circuit device accord-
`ing to this embodiment includes a data selecting circuit 100
`and a prechargc circuit 200., both of which are connected in
`series between a high potential power supply terminal VDD
`and a ground terminal GND. A wiring line 1 is arranged
`between the circuits 100 and 200. The wiring line 1 is
`connected to a common node X between the circuits 100 and
`200. The common node X serves as an output terminal of the
`integrated circuit device according to this embodiment. An
`output data signal BO is output from the output terminal
`(common node X). Note that a prefix “B“ of the output
`signal B0 represents that the level of an input data signal is
`inverted and output. Additionally, in this specification, the
`prefix “B" is defined to represent that the level of an input
`signal
`is inverted and output, as described above, or the
`signal itself is a negative logic. In the drawings, the prefix
`"B“ is represented by "-” (bar).
`As shown in FIG. 4, the data selecting circuit 190 includes
`a plurality of PMOS series circuits 102. The plurality of
`PMOS series circuits 102 are connected in parallel between
`the terminal VDD and the common node X. Each of the
`I’MOS series circuits 1le includes a p—channel MOSFET (to
`be referred to as a PMOS hereinafter) 2 and a PMOS 3,
`which are connected in series with each other. The PMOS 2
`connected to the terminal VDD is a transistor for receiving
`an input signal while the PMOS3 connected to the common
`node X is a transistor for receiving a data selecting signal.
`The intcgrated circuit device according to this embodi—
`ment has four sets of PMOS series circuits 102 (102-1 to
`1024). The I’MOS series circuit [021 includes a PMOS 21
`and a I’MOS 3—1. The remaining PMOS series circuits 102—2
`to 102-4 respectively include PM 083. 2-2 and 3-2, PMUSs
`2-3 and 3-3, and PMOSs 2-4 and 3-4. Input data signals A
`to D are supplied to the gates of the PMOSs 2-1 to 2-4.
`respectively. The PMOSs 2-1 to 2-4 are turned on when the
`
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`potentials of the data signalsA to D go to low level. On the
`other hand, selecting signals Ba to Ed are supplied to the
`gates of the PMOSs 3-1 to 3-4, respectively. The PMOSs 3-1
`to 3—4 are turned on when the potentials of the selecting
`signals Ba to Ed go to low level.
`The precharge circuit 200 includes one n—channel MOS~
`FET (to be referred to as an NMOS hereinafter) 4 connected
`in series between the terminal GND and the common node
`X. The NMOS 4 is a transistor for receiving a precharge
`signal, and a precharge signal PRCII is supplied to the gate
`of the NMOS 4.
`
`One of important functions of the NMOS 4 is to set the
`initial state of the potential level of the output signal B0 in
`response to the precharge signal. Another function is to
`control activationr'inactivation of the integrated circuit
`device itself shown in FIG. 1 or 2 in response to the
`precharge signal.
`The NMOS 4 is turned on while the signal PRCII is at
`high level and charges the common node X to the ground
`potential. At this time, the initial state of the potential level
`ofthe output signal 80 is set at the ground potential. At the
`same time, the common node X is charged to the ground
`potential so that
`the integrated circuit device itself is set
`inactive. More specifically, even when the data signal and
`the data selecting signal are supplied to the data selecting
`circuit 100, the potential of the common node X is substan-
`tially equal to the ground potential.
`On the other hand, the NMOS 4 is turned off while the
`signal PRCl-l
`is at low level. At this time, the integrated
`circuit device itself shown in FIG. 3 is activated. and the
`common node X is charged to a predetermined potential by
`a current output from the PMOS series circuits 102.
`The basic operation of the integrated circuit device shown
`in F] GS. 3 and 4 will be described below.
`
`FIG. 5 is a chart ofthe operating waveforms showing the
`operation of the integrated circuit device according to the
`first embodiment of the present invention.
`In the integrated circuit device shown in FIGS. 3 and 4,
`the data signalsA to D corresponding to the selecting signals
`Ba to Bd of low level are transmitted to the common node
`X. That is, the precharge signal PRCH is set at high level
`first, and the common node X is fixed at low level (ground
`potential) (Tl). Thereafter, the precharge signal PRCH is set
`at low level ('12), and the common node X is set at a floating
`level (T3). One of the selecting signals Ba to Ed is set at low
`level. In this case, assume that the signal Ba is set at low
`level (T4). At
`this time, depending on whether the data
`signal A of high level goes to low level or not,
`it
`is
`determined whether the common node X is charged to high
`level or kept at
`low level (low floating level
`in this
`embodiment). In FIG. 5, the data signalef high level goes
`to low level (T5). Therefore, the common node X is charged
`to high level (T6).
`The precharge levels. of the data signals A to D of the
`integrated circuit device shown in FIGS. 3 and 4 are high
`(high-level precharge type).
`In such an integrated circuit
`device of a high-level precharge type, the input data signal
`is transmitted to the common node X depending on whether
`the potential level of the input data signal goes to low or not.
`If another data signal is to be output after one data signal
`is output, the selecting signal Ba is set at high level (’l‘ll).
`Thereafter, the precharge signal PRCH is set at high level
`(1‘12), and the common node X is charged to low level
`(ground potential) (T13). With this operation, the integrated
`circuit device is restored from the active period to the
`precharge period. When the above operation is performed
`
`6
`for the remaining selecting signals Bl) to Ed, the data signals
`B to D can be transmitted to the common node X.
`
`As described above, the integrated circuit device accord-
`ing to the first embodiment of the present invention can act
`as a multiplexer. This is because only one data signal line is
`selected from the plurality of data signal
`lines, and the
`selected data signal line can be electrically connected to the
`wiring line 1.
`FIG. 6 is a view showing parasitic capacitances added to
`the common node X of the integrated circuit device shown
`in FIGS. 3 and 4. Similarly, FIG.
`’7
`is a view showing
`parasitic capacitances added to the common node X of the
`multiplexer shown in FIG. 1, and FIG. 8 is a view showing
`parasitic capacitances added to the common node X of the
`multiplexer shown in FIG. 2.
`As shown in FIG. 6, the integrated circuit device shown
`in FIGS. 3 and 4 has only five parasitic capacitances, and
`particularly, p-n junction capacitances PN-J added to the
`common node X,
`i.e., four junction capacitances at
`the
`drains of the PMOSs 3‘1 to 3—4 whose gates receive the
`selecting signals Ba to Ed, and one junction capacitance at
`the drain of the NMOS 4 whose gate receives the precharge
`signal PRCI—I.
`the multiplexer
`To the contrary, as shown in FIG. 7,
`shown in FIG. 1 has eight p-n junction capacitances PN-J
`added to the common node X, i.e., four junction capaci-
`tances at the drains of the PMOSs of the CMOS transfer gate
`circuits, and four junction capacitances at the drains of the
`NMOSs.
`
`As shown in FIG. 8, the multiplexer shown in FIG. 2 has
`eight p-n junction capacitances PN-J added to the common
`node X, i.e., four junction capacitances at the drains of the
`PMOSs of the (IMOS clocked inverter circuits, and four
`junction capacitances at the drains of the NMOSs.
`Therefore, the integrated circuit device shown in FIGS. 3
`and 4 can act as a multiplexer and also operate at a high
`speed because the parasitic capacitances are largely
`decreased as compared to the multiplexers shown in FIGS.
`1 and 2.
`
`In addition, the data signals A to I) of high level (in a
`precharge state) go to low level. For this reason, when these
`signals are set at a level lower than the power supply voltage
`VDD only by the absolute value of a threshold voltage Vth
`of the PMOS, the l’MOSs 2 (2-1 to 2-4) are turned on to
`transmit the data signals to the common node X. Therefore,
`the data signals A to D can be quickly transmitted to the
`common node X.
`
`Because ol~ these advantages, the integrated circuit device
`shown in FIGS. 3 and 4 operates at a high speed as compared
`to the multiplexers shown in FIGS. 1 and 2.
`The basic arrangement and operation have been described
`above.
`
`The second embodiment of the present invention will be
`described below.
`
`The second embodiment is a detailed application example
`of the present
`invention,
`in which an integrated circuit
`device according to the present invention is used as the data
`multiplex circuit of a dynamic RAM (DRAM).
`FIG. 9 is a block diagram schematically showing a
`DRAM according to the second embodiment of the present
`invention. FIG. 10 is a block diagram showing one of 16
`Mbit-cel] arrays shown in FIG. 9 in more detail. FIG. 11 is
`a block diagram showing one of 256 kbit-cell arrays shown
`in FIG. 10 in more detail. FIG. 12 is a circuit diagram
`showing one of DO bulfers shown in FIG. 10 in more detail.
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`The DRAM shown in FIG. 9 is a 64 Mbit DRAM.
`
`As shown in FIG. 9, the 64 Mbit DRAM includes four 1.6
`Mbit-cell arrays A to D.
`As shown in FIG. 10. a row decoder is arranged at the
`center of each 16 Mbit-cell array. Thirteen pairs of row
`addresses AOR to A12R and BAOR to BA12R are supplied
`to the row decoder. Acolumn decoder is arranged at one end
`of the 16 Mbit-cell array. Eight pairs of column addresses
`All(.‘ to A7C and BAOC to I3A7C are supplied to the column
`decoder. The 16 Mbit-cell array also includes 64 256 kbil-
`cell arrays.
`As shown in FIG. 11, bit line pair precharge circuits (PC),
`sense amplifiers {SA}, and DO gates (DOG) are arranged on
`both the sides of a 256 kbit—cell array (ARY). Each bit line
`pair precharge circuit (PC) eqttalizes the potential difference
`between the bit line pairs (the bit line pair includes a bit line
`BI. and an inverted bit line BBL) and precharges the bit line
`pairs. After the bit line pairs are precharged, a data signal is
`read out from a memory cell (CELL). At this time, a small
`potential dilTerence is generated between the bit line pairs.
`The sense amplifier (SA) amplifies this small potential
`difference. The DO gate (DOG) transmits the data signal
`amplified by the sense amplifier (SA) to a data line pair (the
`DO line pair includes a DO line DO and an inverted DO line
`BDQ) on the basis of a signal CSL. The signal CSL is a
`signal for selecting a column of the memory cell array,
`which is output from the column decoder.
`in the DRAM
`according to this embodiment,
`four data line pairs are
`arranged on each side of the 256 kbiteell array (ARY).
`In the DRAM according to this embodiment,
`the data
`signal amplified by the sense amplifier (SA) is supplied to
`[our DO bulIers (DOB) shown in FIG. 11. The data signal
`received by the DO bulIcrs ( DOB) is further amplified by the
`DO bulfers (DOB). The data signal amplified by the DO
`buffers (DOB) is supplied to a readlwrite data line pair (the
`readtwrite data line pair includes a readfwritc data line RWD
`and an inverted readlwrite data line BRWD).
`As shown in FIG. 12, the DO buffer (DOB) includes a DO
`line equalizer 300 for equalizing a potential difference
`between the pair ofDO lines(DO, BDO), a transfer gate 302
`for transferring a data signal from the pair of DO lines to a
`pair of internal DO lines (DOI, BDOI), an internal DO line
`equalizer 304 for equalizing a potential difference between
`the pair of internal DO lines, a sense amplifier 306 for
`amplifying a potential difference between the pair of internal
`DO lines, and an RWD line pair driving circuit 308 for
`driving a pair of readiwrite data lines (RWD, BRWD) based
`on data in the internal DO line pair.
`An RWD line equalizer 310 for equalizing a potential
`ditl’erence between the pair of readfwrite data lines is con-
`nected between the read/“write data line RWD and the
`inverted readtWrite data line BRWD.
`
`'l‘he DO line equalizer 300 includes a PMOS 321 con—
`nected in series between the high potential power source
`terminal VDD and the line DO, a I’MOS 3.22 connected in
`series between the power source terminal VDD and the line
`BDO, and a PMOS 323 connected in series between the
`lines [)0 and BBQ. The gates of the PMOSs 321, 322 and
`323 are connected to a line through which a DO line
`equalizing signal CEO is supplied.
`The transfer gate 302 includes a PMOS 324 connected in
`series between the lines DO and DOI and a PMOS 325
`connected in series between the lines BDQ and BBQ]. The
`gates of the PMOSs 324 and 325 are connected to a line
`through which a signal LATCl-l, which is an inversion of an
`inverted latch signal BI..ATCH, is supplied.
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`The internal DO line equalizer 304 includes a PMOS 326
`connected in series between the power source terminal VDD
`and the line DO], a PMOS 32‘? con nected in series between
`the power source terminal VDD and the line BDQI, and a
`PMOS 328 connected in series between the lines D01 and
`BDOl. The gates of the PMOSs 326, 32’? and 328 are
`connected to a line through which the DO line equalizing
`signal CEO is supplied.
`The sense amplifier 306 includes a PMOS 329 connected
`in series between the power source terminal VDD and the
`line D01,
`:1 PMOS 330 connected in series between the
`power source terminal VDD and the line BDQI, an NMOS
`331 connected in series between the line DO] and the line
`through which the inverted latch signal BLATCH is
`supplied. and an NMOS 332 connector] in series between the
`line BDOI and the line through which the inverted latch
`signal BLAI