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`I
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`

`

`
`
`DECEMBER 2007
`
`VOLUME 42
`
`NUMBER 12
`
`IJSCBC
`
`(ISSN 0018-9200)
`
`1SPECIAL ISSUE ON THE 2007 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC)
`__
`
`Introduction to the Special Issue on the 2007 IEEE International Solid—State Circuits Conference .........................
`................................................................... J. Sevenhans, J. T. Stom'ck, M. Miller, and J. E. D. Hurwitz
`
`2635
`
`
`
`IA Wide-Bandwidth 24 GHz ISM Band Fractional-N PLL With Adaptive Phase Noise Cancellation ......................
`.................................................................................... A. Swaminathan K. J. Wang, and I. Galton
`
`2639
`
`A Micropower Interface ASIC for a Capacitive 3-Axis Micro—Accelerometer ................................................
`........................... M. Paavola, M. Ka'ma'ra'inen, J. A M. Ja'rvinen, M. Saukoski M Laiho, andK. A. I. Halonen
`A 2 W CMOS Hybrid Switching Amplitude Modulator for EDGE Polar Transmitters ......................................
`'
`......................................................................................... T.-W.Kwak,.-.MCLee, andG-HCho
`A Zero--Crossing——Based 8-bit 200 MS/s Pipelined ADC ............................................. L. Brooks and H. S. Lee
`A 10-bit 205-MS/s 1.0-mm2 90-nm CMOS Pipeline ADC for Flat Panel Display Applications ............................
`................................................................................. S.- C. Lee, Y-D. Jean J. -K. Kwon, and]. Kim
`.‘A 56 mW Continuous-Time Quadrature Cascaded EA Modulator With 77 dB DR in a Near Zero-IF 20 MHz Band ....
`..................................................... L. J. Breems, R. Rutten, R. H. M. van Veldhoven, and G. van der Weide
`A Single-Inductor Switching DC—DC Converter With Five Outputs and Ordered Power-Distributive Control ............
`2706
`................................................... H. -PLe,C. -S. Chae, K. -C.Lee S. -W.Wang,G H. Cho, andG. -H. Cho
`
`
`2651
`
`2666
`2677
`
`2688
`
`2696
`
`WIRELINE
`
`.J. -C. Chien and L. -H. Lu
`40-Gb/s High-Gain Distributed Amplifiers With Cascaded Gain Stages1n 0.18-11m CMOS.
`.A 40—44 Gb/s 3X Oversampling CMOS CDR/l: l6 DEMUX .................................................... N. Nedovic,
`N. Tzartzanis, H. Tamura F. M. Rotella, M. Wiklund, Y. Mizutam', Y. Okam'wa T. Kuroda, J. Ogawa, and W W. Walker
`A Fully Integrated 4 x 10-Gb/s DWDM Optoelectronic Transceiver Implemented1n a Standard 0.13 11111 CMOS SOI
`. Technology .................... A. Naraszmha, B.Anal111', Y. Liang, T. J. Sleboda S. Abdalla, E. Balmater, S. Gloeckner,
`D Guckenberger M. Harnson, R. G. M. P. Koumans, D. Kucharski, A. Mekis, S. ersaidi, D. Song, and T. Pinguet
`
`
`2715
`
`2726
`
`2736
`
`IEEE
`
`iii
`
`

`

`A 14—mW 6.25—Gb/s Transceiver in 90—nm CMOS ..............................................................................
`....................................... J. Poulton, R. Palmer, A. M. Fuller; T. Greer, J. Eyles, W. J. Dally, and M. Horowitz
`A Self-Calibrated On-Chip Phase-Noise Measurement Circuit With —75 dBc SinglenTone Sensitivity at 100 kHz Offset
`.
`.
`.
`.......................................................................................... W. Khalil, B. Bakkaloglu, and S. Kiaei
`
`WIRELESS AND RF
`
`A Blocker Filtering Technique for SAW-Less Wireless Receivers .................................................. H. Darabi
`A Multimode Transmitter in 0.13 lle CMOS Using Direct—Digital RF Modulator ...........................................
`....................................................... P. Eloranta, P. Seppinen, S. Kallioinen, T. Saarela, and A. Pc‘irssinen
`A Single—Chip Dual—Band CDMA2000 Transceiver in 0.13 pm CMOS .......................................................
`................................... J. Zipper, C. Stdgei; G. Hueber; R. Vazny, W. Schelmbauer; B. Adler, and R. Hagelauer
`A Fully Integrated MIMO Multiband Direct Conversion CMOS Transceiver for WLAN Applications (802.11n) .........
`............ A. Behzad, K. A. Carter, H.-M. Chien, S. Wu, M.-A. Pan, C. P. Lee, Q. Li, J. C. Leete, S. An, M. S. Kappes,
`Z. Zhou, D. Ojo, L. Zhang, A. Zolfaghari, J. Castanada, H. Darabi, B. Yeung, A. Rofougaran, M. Rofougaran,
`J. Trachewsky, T Moorti, R. Gaikwad, A. Bagchi, J. S. Hammerschmidt, J. Pattin, J. J. Rael, and B. Marholev
`SiP Tuner With Integrated LC Tracking Filter for Both Cable and Terrestrial TV Reception ................................
`J. R. Tourret, S. Amiot, M. Bernard, M. Bouhamame, C. Caron, 0. Crand, G. Denise, V. Fillatre, T. Kervaon, M. Kristen,
`L. L0 Coco, F Mercier; J. M. Paris, F. Pichon, S. Prouet, V. Rambeau, S. Robert, J. van Sinderen, and 0. Susplugas
`A 900 MHz UHF RFID Reader Transceiver IC ..................................................................................
`....................................... S. Chin, I. Kipnis, M. Loyer, J. Rapp, D. Westberg, J. Johansson, and P. Johansson
`An Integrated Ultra-Wideband Timed Array Receiver in 0.13 nm CMOS Using a Path-Sharing True Time Delay
`Architecture ......................................................................... T.-S. Chu, J. Roderick, and H. Hashemi
`A 2.5 nJ/bit 0.65 V Pulsed UWB Receiver in 90 nm CMOS ............................. F. S. Lee and A. P. Chandrakasan
`A 0.65-t0-1.4 nJ/Burst 3-to-10 GHZ UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a ...........................
`.................................... J. Ryckaert, G. Van der Plas, V. De Heyn, C. Desset, B. Van Poucke, and J. Craninckx
`A Magnetically Tuned Quadrature Oscillator ............ G. Cusmai, M. Repossi, G. Albasini, A. Mazzanti, and F. Svelta
`A 23-to-29 GHz Transconductor—Tuned VCO MMIC in 0.13 am CMOS ......................... K. Kwok and J. R. Long
`Heterodyne Phase Locking: A Technique for High—Speed Frequency Division ................................... B. Razavi
`Millimeter-Wave Devices and Circuit Blocks up to 104 GHz in 90 nm CMOS ...............................................
`........................................................................ B. Heydari, M. Bohsali, E. Adabi, and A. M. Niknejad
`
`2809
`
`2822
`
`2834
`2851
`
`2860
`2870
`2878
`2887
`
`2893
`
`IMAGING, MEMS, MEDICAL, AND DISPLAYS
`
`2904;
`
`A Continuous-Grain Silicon—System LCD With Optical Input Function ........................................................
`.............................................................................. C. J. Brown, H. Kato, K. Maeda, and B. Hadwen
`IO-bit Driver IC Using 3-bit DAC Embedded Operational Amplifier for Spatial Optical Modulators (SOMs) .............
`.................................................................... J.-S. Kang, J. -H. Kim, S.-Y. Kim, J.-Y. Song, 0.-K. Kwon,
`Y.-J. Lee, B.-H. Kim, C.-W. Park, K.-S. Kwon, W.-T. Choi, S.-K. Yun, I.-J. Yeo, K.-B. Han, T-S. Kim, and S.-I. Park
`CMOS Single-Chip Electronic Compass With Microcontroller ............ C. Schon‘, R. Racz, A. Manco, and N. Simonne
`A 2 MW 100 nV/rtHz Chopper—Stabilized Instrumentation Amplifier for Chronic Measurement of Neural Field
`Potentials ....................................... T Denison, K. Consoer, W. Santa, A.-T. Avestruz, J. Cooley, and A. Kelly
`A 232-Channel Epiretinal Stimulator ASIC ........................ M. Ortmanns, A. Rocke, M. Gehrke, and H. -J. Tiedtke
`A 1/2.7—in 2.96 MPixel CMOS Image Sensor With Double CDS Architecture for Full High-Definition Camcorders .....
`............................................................................................. H. Takahashi, T Nada, T. Matsuda,
`T. Watanabe, M. Shinohara, T Endo, S. Takimoto, R. Mishima, S. Nishimura, K. Sakurai, H. Yuzurihara, and S. Inoue
`Multiple-Ramp Column-Parallel ADC Architectures for CMOS Image Sensors ............................' ..................
`.................................................... M. F. Snoeij, A. J. P. Theuwissen, K. A. A. Makinwa, and J. H. Huijsing
`A Spatial-Temporal Multiresolution CMOS Image Sensor With Adaptive Frame Rates for Tracking the Moving Objects
`2978'
`in Region-of-Interest and Suppressing Motion Blur ............ J. Choi, S.-W. Han, S. -J. Kim, S.-I. Chang, and E. Yoon
`—————_—_—____—___________#_.—v
`
`2913
`2923
`
`2934
`2946
`
`2960
`
`2968
`
`' 2007INDEX .........................................................................................................................
`_——————___———____._.___._
`
`2990
`
`iv
`
`iv
`
`

`

`This material may be protected by Copyright law (Title 17 U.S. Code)
`
`

`

`KIN-AK (31 (IL: 2 W CMOS HYBRID SWITCHING AMPLITUDE MODULATOR FOR EDGE POLAR TRANSMITTERS
`
`2667
`
`Amplitude Modulator
`
`R(r)=,/11+Q1
`
`I. Q
`
`to
`
`Polar
`
`RU)—>
`
`—»
`
`(00)
`
`W) = Ian"(Q/ I)
`
`
`
`
`W)
`
`.-
`
`Ir
`
`Fig. 1. Block diagram of a polar transmitter.
`
`
`
`
`
`
`
`(b)
`
`I Linear Amp Switching Amp
`(a)
`
`(a) Conceptual diagram of the hybrid switching amplifier. (b) Phase
`\Fig. 2.
`diagram of each current.
`
`
`
`
`1(EER) applications [6], it has not been used for polar transmit-
`ters in CMOS process because of the difficulty of designing a
`
`'linear amplifier with a wide bandwidth, a low output impedance,
`
`and a high current-driving capability. However, if the switching
`stage with a wide bandwidth and a low ripple current is used
`
`'for the hybrid switching amplifier, such burdens of the linear
`amplifier can be reduced. By the way, a bandwidth and a ripple
`current are influenced by the control method. Compared with
`'pulsewidth modulation (PWM) control, a hysteretic control of
`
`the switching amplifier relatively has a narrow bandwidth and
`a large constant ripple current because the switching frequency
`
`Varies according to the output voltage and the bandwidth is
`limited by the minimum switching frequency. Therefore, the
`100nventional hybrid switching amplifier based on the hysteretic
`:Control has a relatively lower bandwidth and a larger ripple
`.‘Punent. To extend the narrow bandwidth wider,
`the linear
`
`:fimplifier must have a high current-driving capability according
`5'30 (l) to provide more signal current for making up for the
`ldistortion from the switching stage. In case of a large ripple
`_;Cl_1rrent, in particular, the linear amplifier must have a lower
`'_;°11tput impedance at the switching frequency to reduce the
`.l'_°11tput ripple voltage because the multiplication of the output
`
`impedance of the linear amplifier and the ripple current makes
`'the output ripple voltage.
`
`
`
`
`
`B. Proposed Hybrid Switching Amplifier
`
`As shown in Fig. 3(a), the PWM control is used for the
`switching stage to mitigate the difficulties in the design of the
`linear amplifier. Hence, the switching frequency f, is fixed,
`which makes the unity-gain frequency constant as well. In addi-
`tion, the peak—to-peak ripple current of the PWM-based hybrid
`switching amplifier is less than that of the hysteresis-based one
`[5] with the constant ripple current on the assumption that the
`switching frequency of the former is equal to the maximum
`switching frequency of the latter. This is because the relation
`between the switching frequency and the peak-to-peak ripple
`current Air is expressed as follows for both cases:
`
`f, - At, = (Vdd/L) - D - (1 — D)
`
`(2)
`
`where D is the duty. ratio, Vdd is the supply voltage, and L is
`the inductance.
`
`However, when we use the PWM control, we must consider
`
`the loop stability. From Fig. 3(a), the current loop gain fl can be
`found by
`
`MS) =
`
`AsAIAM/(ZL + 5L)
`
`_
`
`(3)
`
`where A5, AI, and AM are the current sense gain, integrator
`gain, and modulation gain, respectively, and (ZL + sL) is the
`impedance from a switching node Vx. The modulation gain AM
`is the ratio of Vdd to a peak—to-peak magnitude of a triangular
`wave. For loop compensation, as shown in Fig. 3(b), one zero
`at about 160 kHz is inserted into the integrator since two poles
`result from the integrator and the inductor in the current loop.
`
`C. Third—Order Ripple Filter and Current Feedback
`
`Although the linear amplifier has low output impedance, the
`switching ripple current should be reduced to decrease both
`the output ripple voltage and the power consumption of the
`linear amplifier. For this purpose, as shown in Fig. 4, a third-
`order filter with L1, L2, and CF is used in the current loop.
`
`

`

`2668
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`I
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 12, DECEMBER 2-;.
`
`
`
`
`'
`
`I
`
`Fig. 4. Hybrid switching amplifier with the third—order ripple filter and the cur.
`rent feedback.
`
`
`EMS) = id / is = ASA|A|v|l (ZL + 5L) 4...------._-.—
`
`Current Loop [3
`
`(a)
`
`1 1 (RL + sL)
`
`””5
`
`42:13
`
`'50“!
`
`RL = 4
`L = 4uH
`
`A”
`
`sea
`
`
`
`(b)
`
`(a) Simplified block diagram of the hybrid switching amplifier. (b) Bode
`Fig. 3.
`plots for the current loop design.
`
`In spite of the desirability of lowering the resonant frequency
`for greater reduction of the ripple current, two additional poles
`should have little impact on the current loop. Accordingly, the
`resonant frequency is chosen between the unity-gain frequency
`of the current loop and the switching frequency. Additionally,
`a damping resistor Rd is inserted, taking a quality factor into
`account, because an excessively small Rd can generate an un-
`wanted resonance.
`
`To stabilize the current loop in spite of the relatively small
`Rd, the current feedback suggested in [7] is introduced. The
`ripple information is used for the hysteretic control in the ref-
`erence, whereas only a high—frequency signal current passing
`through the capacitor CF is used for the PWM control with the
`same but negative gain as the current sense gain A5, because the
`
`Fig. 5. Hybrid switching amplifier with the feedforward path.
`
`D. Feedforward Path
`
`
`
`sensed ripple information is attenuated at the output of the in-.l
`'
`
`tegrator. The current loop therefore remains stable because the
`same voltage VSEN, as in the case of a single inductor, is reCOV-J .'
`
`ered without losing the high-frequency current component.
`
`
`-'
`
`As given in (l), the linear amplifier should provide some com" '
`pensation current to prevent the output voltage from being dis":
`torted by the delay of the current loop at the high frequency . T1195
`
`higher the frequency, the more the compensation current flows“ 't.
`There are higher frequency components than the EDGE base;
`
`.-
`band signal of about 270 kHz in the amplitude path of the 13013r
`
`transmitter. Hence, an auxiliary circuit is necessary to alleviatea-
`the burden of the linear amplifier.
`"-
`
`If we add a feedforward path, like the one shown in Fig. 5, the.
`input signal can directly control the switching amplifier. Such 3g-
`l
`
`
`1:
`
`;_
`
`.
`
`

`

`
`
`19W“
`
`at 411.: 2 W CMOS HYBRID SWITCHING AMPLITUDE MODULATOR FOR EDGE POLAR TRANSMITTERS
`
`2669
`
`Summing Circuit + Integrator
`
`
`
`
`Feedtonivard Path
`
`..u
`
`'-
`
` Ripple Filter +
`Current Feedback
`
`
`
`>iif”
`
`
`Fig. 6. Detailed block diagram of the hybrid switching amplifier.
`
`
`path is faster than the feedback current path formed by sensing
`the output current of the linear amplifier. Although the feedfor-
`
`ward signal can be injected after the integrator, it is added before
`the integrator in Fig. 5 considering the implementation of the
`
`summing circuit and integrator as will be explained in the next
`
`section. With this feedforward path, we can express the output
`
`current as follows:
`
`Av
`”yin
`.
`.
`1
`*L— :Za+(AS'la+AF‘Uin)'AI'AM'm
`(4)
`
`'Where A,f is_ the overall closed—loop gain of 1 / F . Since the
`Putput current of the linear amplifier ia ideally has to be equal
`to zero, the gain of the feedforward path AF (s) is given as
`
`
`AF(S)_Avf'ill+S/WpIZL+3L
`AM A10 1+S/wz
`ZL
`
`Avf _ i1 +s/wp
`AM A10 1+s/wz
`
`(5)
`
`
`
`.
`
`.r
`
`.there the integratorgain AI(s) is AID-((1+s/wz)/(1+3/wp)).
`
`:Nétice that the gain of the feedforward path has the reciprocal
`
`'Fharacteristic of the integrator and the inductor to compensate
`
`BIfOI their delays.
`
`
`
`E.
`
`Implementation ofa Hybrid Switching Amplifier
`
`Fig. 6 shows the detailed circuit of the hybrid switching am-
`plifier. In CMOS design, although three voltage signals can be
`added and then integrated as shown in Figs. 4 and 5, the simul-
`taneous summation and integration of the signals at the node
`VC, after the conversion of the three voltage signals into cur-
`rent ones, is advantageous, that is, the sensed output current of
`the linear amplifier, the feedforward current, and the high-fre-
`quency current through the ripple filter are added together and
`integrated at the node with the inverted polarity of the last one.
`In this case, the dc gain of the integrator A10 is replaced by
`Rm and the sensing ratio of the output current of the linear
`amplifier is 1 to N so that the current sense gain As is 1/N.
`The feedforward path gain AF(s) given in (5) can be expressed
`as AFv(-9) / RF because the input voltage Vin is converted into
`the current by RF after passing through the lead compensator
`AFV (s). As mentioned before, the zero and the pole of Apv(s)
`should be located at the pole and the zero of the integrator, re—
`spectively. If the transfer functions of the integrator and AFV (s)
`are given, the value of RF can be found to set the dc gain of
`A5(3) The capacitor in the feedforward path 01 is a coupling
`capacitor with a large capacitance.
`After the high-frequency current that passes through the
`ripple filter is sensed as a voltage by the damping resistor Rd,
`the voltage is converted into the current by Rcf. Since the
`
`

`

`2670
`
`high-frequency current should be transferred to the integrator
`with the same gain of l/N as the output current of the linear
`amplifier, the value of Rcf is set equal to N - Rd. The capacitor
`02 is also a coupling capacitor like Cl.
`
`F Design for the Class-E2 EDGE
`
`The Class—E2 EDGE specifications require an average output
`power of 26 dBm and a peak—to-average power ratio of 3.2 dB.
`Accordingly, the amplitude modulator should be able to supply
`more than about 2.2 W, assuming that the RF power amplifier
`has a maximum efficiency of 40%. This means that the equiva-
`lent dc load resistance is approximately 4 9 when the maximum
`output voltage of the amplitude modulator is 3 V at Vdd : 3.5 V
`[2]. Hence, the hybrid switching amplifier is designed to drive a
`power amplifier with an equivalent impedance of 4 9 while its
`output voltage varies from 0.4 to 3 V.
`Despite the EDGE signal bandwidth of about 270 kHz, the
`amplitude modulator should have a bandwidth wider than 2 MHz
`to satisfy the error vector magnitude (EVM) and the spectral
`mask requirements because, as mentioned before, the amplitude
`component for the polar modulator becomes much wider than
`that of the original EDGE signal in the process of extracting it
`[I], [2]. Fortunately, however, the low-speed switching amplifier
`can efficiently supply most of the output current because most of
`the EDGE amplitude signal power is concentrated on the low-
`frequency band of less than 50 kHz, as shown in [1]. This is why
`the current loop [3 is designed to have a unity-gain frequency
`of about 460 kHz using a 2 MHz switching frequency with a
`4 pH inductance, as shown in Fig. 3(b). As a result, a switching
`ripple current of about 110 mApp is generated without the use
`of the third-order ripple filter at a duty ratio of 0.5. However, it
`is reduced up to about 40 mApp with the third-order ripple filter
`and the current feedback. The values of the used components are
`
`as follows: L1 : 3uH,L2 : 1 uH,Cf = 100nF,Rd : 29,
`and Rcf = 390 9.
`
`On the other hand, the linear amplifier should have a band-
`width that is much wider than 2 MHz to compensate for the
`fast varying amplitude components that the switching ampli-
`fier cannot follow. The driving capability of the linear amplifier
`should also be more than at least 80 mA, including a switching
`ripple current and a high-frequency signal current, because, ac-
`cording to (l) and Fig. 3(b), the required output current of the
`linear amplifier is approximately 34 mA on the condition that
`the maximum output voltage at 50 kHz, VO : 1.25 - sin(27r '
`50 k - t) + 1.75 Vac, is applied to a 4 0 load. To put it con-
`cretely,
`|13| = 9.2, 6 = 90° at 50 kHz from Fig. 3(b), and the
`output current from the switching stage is slower than the output
`current by a = 62°.
`
`III. LINEAR AMPLIFIER WITH A NOVEL CLASS-AB BUFFER
`
`A. Critical Design Parameters for the Linear Amplifier
`
`If the amplitude modulator has an input signal of a(t) and
`an output signal of a’ (t) with a closed—loop gain of l, a’(t) is
`expressed as the summation of a(t) and the switching ripple
`voltage of cm - cos(th + gb), where am is the switching fre-
`quency. By assuming the phase-modulated signal of cos(wct +
`6(t)) is applied at the input of the RF power amplifier, we can
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 42, NO. 12, DECEMBER'.2007
`
`5’00) :a(t) - cos (wet + 6(t)) + 04R -c0s(er + (l5)
`- cos (wct + 6(t))
`
`
`
`express the output of the power amplifier 5/00,) by the am -1_
`tude modulation of a’ (t) and cos(wct + 9(t)) as follows. mp .
`
`
`The last term is caused by the output ripple voltage of [he .-
`plitude modulator, that is the ripple voltage from the who I
`
`amplifier results1n unwanted interference with the phase--111
`lated carrier at the offset frequency of run away front the cam -'
`
`frequency we Consequently. the fundamental component oft
`output ripple voltage should be a factor of approximately 7
`
`less than the output voltage of the amplitude modulator to salt
`the spectral requirement of about —63 cch for the maxim
`
`output power of 29.2 dBm at the switching frequency [13]_
`Because the switching ripple voltage at the output of the 11
`
`about 200 m9 at a switching frequency of 2 MHz.
`In addition,
`the linear amplifier should be able to sink
`
`
`
`source the ripple current at any level of the output voltage
`varying in the positive range during operation. In other words; i
`
`
`
`
`amplifier. We based our definition of the four—quadrant opera-g
`tion on the assumption that the output voltage at the center 1s]; -.-
`half Vdd because of using a single supply voltage.
`
`
`
`B. Conventional Class-AB Output Stages
`
`slew rate.
`
`
`A local negative feedback using an operational transCOIl
`ductance amplifier (OTA) has often been applied to reduce the:
`
`output impedanceIn a CS output stage [9] The loop gain of thE .1
`
`local feedback loop effectively reduces the output impedance 1
`together with that of a global feedback loop. The highe1 th9".1_-
`
`loop gain of the OTA, the greater the decrease of the output\ 1 It'-
`impedance. However, the output impedance1ncreases at a hlgh 2
`
`frequency because the gains of both feedback loops decreflSf'
`
`due to the bandwidth limitation. While increasing the transcOIl"
`
`ductance of the output transistor in a CS output stage help_
`to reduce the output impedance with a Miller compensatiO‘l
`capacitor at a high frequency, it requires much power consumP'.
`tion and large area to obtain the desired output impedance.
`
`1
`
`.
`
`
`
`

`

`1(wa et (11.: 2 W CMOS HYBRID SWITCHING AMPLITUDE MODULATOR FOR EDGE POLAR TRANSMITTERS
`
`267 l
`
`
`
` (b)
`
`_ Fig. 7. Composite output stages advantageous to sourcing the output current.
`
`The output stages, which are a combination of the CS and
`.lSF stages, have sometimes been suggested as a solution for
`lboth rail-to-rail operation and low output impedance [10], [11].
`|The output impedance of the composite output stage in [10]
`|depends solely on the transconductance of the SF stage, so
`[that it is not easy to implement the desired impedan