United States Patent
`Ohsawa
`
`5:5
`
`US005870340A
`(11] Patent Number:
`[45] Date of Patent:
`
`5,870,340
`Feb. 9, 1999
`
`[54] MULTIPLEXER
`
`[75]
`
`Inventor: Takashi Ohsawa, Yokohama, Japan
`
`4,882,709 11/1989 Wyland sssssssnstsnsnainne 365/189.02
`4,888,739
`12/1989 Frederick ..........
`. 365/189.02
`
`5,012,126
`4/1991 Feldbaumer et al...
`cceseee 307/243
`.......
`. 365/189.02
`5,262,990
`11/1993 Mills et al.
`
`[73] Assignee: Kabushiki Kaisha Toshiba, Kawasaki, SAEQOS Hastie abesssssssscisecsscesese SeHA08SALBAB)
`
`
`
`
`3/1996 Feng essssn
`.. 365/189.02
`5,497,347
`Tapa
`5,502,683
`3/1996 Marchioro
`» 365/189,02
`5,570,320
`10/1996 Ruinas .......06.
`. 365/189,02
`FOREIGN PATENT DOCUMENTS
`
`[21] Appl. No.: 889,441
`
`[22]
`
`Filed:
`
`Jul. 8, 1997
`
`Related U.S. Application Data
`
`[62] Division of Ser. No. 763,036, Dec. 10, 1996, Pat. No.
`5,701,095, which is a continuation of Ser. No. 393,076, Feb.
`23, 1995, abandoned.
`Foreign Application Priority Data
`[30]
`Feb. 25,1994
`[JP]
`Japan cscscsssssscssscsssssssssssnsssnse 6-028593
`[51] TRG? ccuncacuasessupeacenicarann GIIC 7/00
`[52], UES GD ccscccnsevaccaeeen 365/189.02; 365/201; 365/203
`[58]
`Field of Search ..........0.ccc.ee 365/189.02, 201,
`365/203, 189.05, 190
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`4/1994 European Pat. Off..
`0593 152
`9/1994
`European Pal. Off. .
`Q615 251
`Primary Examiner—lan T. Nguyen
`Attorney, Agent, or Firm—Banner & Witcoff, Ltd.
`3
`[57]
`ABSTRACT
`A semiconductorintegrated circuit device has a data select-
`ing circuit connected to a first power supply terminal, a
`precharge circuit, connected to a second power supply
`terminal, for receiving a precharge signal, and a wiring line
`connected to a common connection point between the data
`selecting circuit and the precharge circuit. The data selecting
`circuit
`includes at
`least
`two,
`i-e.,
`first and second data
`transmission circuits. A first
`input data signal and a first
`selecting signal are supplied to the first data transmission
`circuit. A second input data signal and a second selecting
`signal are supplied to the second data transmission circuit.
`
`25 Claims, 27 Drawing Sheets
`
`4,280,212
`AGES,944.
`
`7/1981 Ransom et al. oe 327/410
`DAGEA Uys vcccscsasicccsssseeccseesereccpemannane 327/410
`
`16M BIT-
`CELL ARRAY A
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`
`
`INTEL 1119
`
`INTEL 1119
`
`

`

`U.S. Patent
`
`Feb. 9, 1999
`
`Sheet 1 of 27
`
`5,870,340
`
`
`
`
`F 1G.
`
`4
`
`(PRIOR ART)
`
`F |G.
`
`2 (PRIOR ART)
`
`

`

`U.S. Patent
`
`Feb. 9, 1999
`
`Sheet 2 of 27
`
`5,870,340
`
`
`
`INPUTDATASIGNALS
`
`0OowD>
`
`DATA SELECTING CIRCUIT
`
`~
`OUTPUT
`abed
`ofye8PRECHARGE
`DATA SELECTING
`Deat:
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`PRECHARGE
`SIGNAL
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`CIRCUIT
`200
`
`‘GND
`
`FIG.
`
`3
`
`

`

`U.S. Patent
`
`Feb. 9, 1999
`
`Sheet 3 of 27
`
`5,870,340
`
`(®)--- PRECHARGE PERIOD
`(@)--- ACTIVE PERIOD
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`

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`U.S. Patent
`
`5,870,340
`
`Feb. 9, 1999
`
`Sheet 4 of 27
`
` FIG 7
`(PRIOR ART)
`
`

`

`U.S. Patent
`
`Feb. 9, 1999
`
`Sheet 5 of 27
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`5,870,340
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`U.S. Patent
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`Feb. 9, 1999
`
`Sheet 6 of 27
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`5,870,340
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`U.S. Patent
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`Feb. 9, 1999
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`Sheet 7 of 27
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`5,870,340
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`U.S. Patent
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`Feb. 9, 1999
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`U.S. Patent
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`Feb. 9, 1999
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`Sheet 9 of 27
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`5,870,340
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`Feb. 9, 1999
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`U.S. Patent
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`Feb. 9, 1999
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`U.S. Patent
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`Feb. 9, 1999
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`Feb. 9, 1999
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`Feb. 9, 1999
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`Feb. 9, 1999
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`Sheet 16 of 27
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`Feb. 9, 1999
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`U.S. Patent
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`Feb. 9, 1999
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`Sheet 18 of 27
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`U.S. Patent
`
`Feb. 9, 1999
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`Sheet 19 of 27
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`5,870,340
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`U.S. Patent
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`Feb. 9, 1999
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`Sheet 20 of 27
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`5,870,340
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`Sheet 21 of 27
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`5,870,340
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`U.S. Patent
`
`Feb. 9, 1999
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`U.S. Patent
`
`Feb. 9, 1999
`
`Sheet 22 of 27
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`5,870,340
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`U.S. Patent
`
`Feb. 9, 1999
`
`Sheet 23 of 27
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`5,870,340
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`U.S. Patent
`
`Feb. 9, 1999
`
`Sheet 24 of 27
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`5,870,340
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`U.S. Patent
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`Feb. 9, 1999
`
`Sheet 25 of 27
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`5,870,340
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`U.S. Patent
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`Feb. 9, 1999
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`Sheet 26 of 27
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`5,870,340
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`U.S. Patent
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`Feb. 9, 1999
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`Sheet 27 of 27
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`5,870,340
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`2
`Parasitic capacitances, and particularly junction capaci-
`tances added to the common node of the semiconductor
`integrated circuit device with the above arrangement are
`present only at a connection point between the first data
`transmission circuit and the common node, a connection
`point between the second data transmission circuit and the
`common node, and a connection point between the pre-
`charge circuit and the common node. Therefore, the parasitic
`capacitances added to the common node are decreased to
`allow the high-speed operation of the semiconductor inte-
`The present invention relates to a semiconductor inte-
`grated circuit device.
`grated circuit device and, more particularly, to a semicon-
`
`ductor integrated circuit device in whichaplurality of signal! In order to achieve the second object, according to the
`lines are integrated into a single signal line.
`present invention, there is provided a semiconductor inte-
`grated circuit device in which a potential fixing circuit for
`2. Description of the Related Art
`fixing the potential of a common node at a predetermined
`Currently, multiplexers are used as semiconductor inte-
`potential is connected to the common node.
`grated circuit devices in which a plurality of signal lines are
`In the semiconductor integrated circuit device with the
`integrated into a single signal line.
`In the multiplexer, a
`above arrangement, the potential of the common node is set
`signal line is selected from the plurality of signal lines, and
`at a floating level during a certain period from the OFF
`the selected signal line is electrically connected to the single
`timing of the precharge circuit to the ON timing of the data
`signal line.
`transmission circuit. When the potential fixing circuit
`is
`As a multiplexer consisting of a CMOS transistor circuit,
`connectedto the common node, the potential of the common
`a transfer gate type multiplexer as shown in FIG, 1, or a
`node can be fixed at a predetermined potential while the
`clocked inverter type multiplexer as shown in FIG. 2 has
`potential of the common node is at a floating level.
`been considered. In either type multiplexer, from selecting
`Therefore, the semiconductor integrated circuit device can
`signals a, Ba, b, Bb, c, Be, d, and Bd (the prefix “B”
`prevent an erroneous operation caused by noise.
`represents an inverted signal), data correspondingto a signal
`In order to achieve the third object, the semiconductor
`of high level is selected and transmitted to a common node
`integrated circuit device which achieves the first or second
`X serving as an output terminal. Note that signals A to D are
`object is used as the data multiplex circuit of a semicon-
`input data signals, and a signal Q is an output data signal.
`ductor memory device.
`In the multiplexer shown in FIG. 1 or 2, however, if the
`number of to-be-selected data is large, parasitic capacitances
`In the semiconductor memory device with this
`such as a junction capacitance and a gate capacitance added
`arrangement, the parasitic capacitances of the data multiplex
`to the common node X increase. For this reason, a high-
`circuit are decreased, Therefore, the semiconductor memory
`speed data selecting operation to select and output the input;
`device operates at a high speed.
`data may be impaired.
`In order to achieve the fourth object, in addition to a
`SUMMARY OF THE INVENTION
`normal mode in which an input data signal is selected in
`accordance with a selecting signal, a test mode in which all
`input data signals are selected in accordance with a selecting
`signal
`is provided. The semiconductor integrated circuit
`device which achievesthe first or second object can perform
`an OR operation by simultaneously transmittingall the input
`data signals to the common node. By using the OR operation
`function, correct/erroneous data is determined.
`In the semiconductor memory device with the above
`arrangement, the multiplex circuit can be used as the OR
`operation circuit of the test circuit, thereby simplifying the
`test circuit.
`
`This application is a divisional of application Ser. No.
`08/763,036, filed Dec. 10, 1996 now U.S. Pat. No. 5,701,
`095, which is a continuation of application Ser. No. 08/393,
`076, filed Feb. 23, 1995, now abandoned.
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`It is the first object of the present invention to provide a
`semiconductor integratedcircuit device capable of operating
`at a high speed even when the numberof to-be-selected data
`is large.
`It is the second object of the present invention to provide
`a semiconductor integrated circuit device which achievesthe
`first object and prevents an erroneous operation caused by
`noise.
`
`It is the third object of the present invention to provide a
`semiconductor memory device which uses the above semi-
`conductor integrated circuit device to operate at a high
`speed.
`It is the fourth object of the present invention to provide
`a semiconductor memory device which uses the above
`semiconductor integrated circuit device to simplify a test
`circuit.
`
`In order to achieve the first object, according to the
`present invention, there is provided a semiconductor inte-
`grated circuit device having a data selecting circuit con-
`nected to a first power supply terminal, a precharge circuit,
`connected to a second power supply terminal, for receiving
`a precharge signal, and a wiring line connected to a common
`connection point between the data selecting circuit and the
`precharge circuit. The data selecting circuit includes at least
`two, ie., first and seconddata transmission circuits. A first
`input data signal and a first selecting signal are supplied to
`the first data transmission circuit. Asecond input data signal
`and a secondselecting signal are suppliedto the second data
`transmission circuit.
`
`1
`MULTIPLEXER
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`Additional objects and advantagesofthe invention will be
`set forth in the description which follows, and in part will be
`obvious from the description, or may be learned by practice
`of the invention, The objects and advantages ofthe invention
`may be realized and obtained by means of the instrumen-
`talities and combinations particularly pointed out
`in the
`appendedclaims.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The accompanying drawings, which are incorporated in
`and constitute a part of the specification, illustrate presently
`preferred embodiments of the invention and, together with
`the general description given above and the detailed descrip-
`tion of the preferred embodiments given below, serve to
`explain the principles of the invention.
`FIG. 1 is a circuit diagram of a conventional multiplexer;
`FIG. 2 is a circuit diagram of another conventional
`multiplexer;
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`FIG, 33 is a circuit diagram of a semiconductor integrated
`circuit device according to the fourth embodiment of the
`present invention;
`FIG, 34 is a circuit diagram of a selecting circuit shown
`in FIG. 33;
`FIG, 35is a circuit diagram of a semiconductor integrated
`circuit device according to the fifth embodiment of the
`present invention;
`FIG, 36 is a circuit diagram of a semiconductor integrated
`circuit device according to the sixth embodiment of the
`present invention;
`FIG. 37 is a chart showing the operating waveforms ofthe
`semiconductor integrated circuit device according to the
`sixth embodiment of the present invention; and
`FIG, 38is a circuit diagram of a semiconductor integrated
`circuit device according to the seventh embodimentof the
`present invention.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`The present invention will be described below in accor-
`dance with preferred embodiments. The same reference
`numerals and symbols denote the same elements throughout
`the drawings, and a detailed description thereof will be
`omitted.
`
`FIG. 3 is a block diagram of a semiconductor integrated
`circuit device according to the first embodiment ofthe
`present invention. FIG. 4 is a circuit diagram of the semi-
`conductor integrated circuit device according to the first
`embodiment.
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`FIG. 3 is a block diagram of a semiconductor integrated
`circuit device according to the first embodiment of the
`present invention;
`FIG, 4 is a circuit diagram of the semiconductor inte-
`grated device according to the first embodiment of the
`present invention;
`FIG. 5 is a chart showing the operating waveformsof the
`semiconductor integrated circuit device according to thefirst
`embodiment ofthe present invention;
`FIG. 6 is a view showingthe parasitic capacitances ofthe
`semiconductor integrated circuit device accordingto thefirst
`embodiment of the present invention;
`FIG. 7 is a view showing the parasitic capacitances of the
`conventional multiplexer shown in FIG. 1;
`FIG, 8 is a view showing the parasitic capacitances of the
`conventional multiplexer shown in FIG. 2;
`FIG. 9 is a block diagram of a DRAM accordingto the
`second embodiment ofthe present invention;
`FIG. 10 is a block diagram of a 16 Mbit-cell array shown
`in FIG, 9;
`FIG, 1 is a block diagram of a 256 kbit-cell array shown
`in FIG. 10;
`FIG, 12 is a circuit diagram of a DQ buffer shown in FIG,
`10;
`FIG. 13 is a chart showing the operating waveforms ofthe
`DQ buffer shown in FIG. 12;
`FIG. 14 is a block diagram of a read multiplexer & write
`multiplexer shown in FIG, 9;
`FIG, 15 is a circuit diagram of a multiplex signal gener-
`ating circuit shown in FIG, 14;
`FIG, 16 is a block diagram of the read multiplexer shown
`in FIG, 14;
`FIG, 17 is a circuit diagram of the multiplex circuit of a
`first multiplex stage shown in FIG. 16;
`FIG, 18 is a circuit diagram of the multiplex circuit of a
`second multiplex stage shown in FIG. 16;
`FIG, 19 is a block diagram of the read multiplexer of a
`DRAMcapable of changing the number ofoutput bits;
`FIG. 20 is a circuit diagram of a switch circuit shown in
`FIG, 19;
`FIGS, 21 and 22 are charts showing the operating wave-
`forms of the read multiplexer shown in FIG. 16;
`FIG. 23 is a circuit diagram of a test circuit shown in FIG.
`
`9;
`
`As shown in FIG. 3, the integrated circuit device accord-
`ing to this embodiment includes a data selecting circuit 100
`and a precharge circuit 200, both of which are connected in
`series between a high potential power supply terminal VDD
`and a ground terminal GND. A wiring line 1 is arranged
`between the circuits LOO and 200. The wiring line 1 is
`connected to a common node X between the circuits 100 and
`200. The common node X serves as an output terminalof the
`integrated circuit device according to this embodiment. An
`output data signal BQ is output from the output terminal
`(common node X). Note that a prefix “B” of the output
`signal BQ represents that the level of an input data signal is
`inverted and output. Additionally, in this specification, the
`prefix “B” is defined to represent that the level of an input
`signal
`is inverted and output, as described above, or the
`signal itself is a negative logic. In the drawings, the prefix
`“B” is represented by “-” (bar).
`FIG, 24 is a circuit diagram of a selecting circuit shown
`in FIG. 9;
`As shownin FIG. 4, the data selecting circuit 100 includes
`a plurality of PMOSseries circuits 102. The plurality of
`FIGS, 25 and 26 are circuit diagrams schematically show-
`PMOSseries circuits 102 are connected in parallel between
`ing the multiplex circuit shown in FIG. 17;
`the terminal VDD and the common node X. Each of the
`FIG, 27 is a block diagram of the write multiplexer shown
`PMOSseriescircuits 102 includes a p-channel MOSFET(to
`in FIG. 14;
`be referred to as a PMOShereinafter) 2 and a PMOS 3,
`FIG, 28 is a circuit diagram of a selecting circuit shown
`which are connected in series with each other. The PMOS 2
`in FIG. 27;
`connected to the terminal VDDisatransistor for receiving
`FIG. 29 is a block diagram of a DRAM according to the
`an input signal while the PMOS3 connected to the common
`third embodiment ofthe present invention;
`node X is a transistor for receiving a data selecting signal.
`FIG, 30 is a block diagram of a 16 Mbit-cell array shown
`The integrated circuit device according to this embodi-
`in FIG. 29;
`ment has four sets of PMOSseries circuits 102 (102-1 to
`FIG. 31 is a circuit diagram of the multiplex circuit of a
`102-4). The PMOSseries circuit 102-1 includes a PMOS 2-1
`first multiplex stage provided to the DRAM accordingto the
`and a PMOS3-1. The remaining PMOSseriescircuits 102-2
`third embodimentofthe present invention;
`to 102-4 respectively include PMOSs2-2 and 3-2, PMOSs
`FIG. 32 is a circuit diagram of the multiplex circuit of a
`2-3 and 3-3, and PMOSs2-4 and 3-4. Input data signals A
`second multiplex stage provided to the DRAM according to
`to D are supplied to the gates of the PMOSs 2-1 to 2-4,
`the third embodiment of the present invention;
`respectively. The PMOSs2-1 to 2-4 are turned on when the
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`for the remaining selecting signals Bb to Bd, the data signals
`B to D can be transmitted to the common node X.
`
`5
`potentials of the data signals A to D go tolow level. On the
`other hand, selecting signals Ba to Bd are supplied to the
`gates of the PMOSs3-1 to 3-4, respectively. The PMOSs3-1
`Asdescribed above, the integrated circuit device accord-
`to 3-4 are turned on when the potentials of the selecting
`ing to the first embodimentof the present invention can act
`signals Ba to Bd go to low level.
`as a multiplexer. This is because only one data signal lineis
`The precharge circuit 200 includes one n-channel MOS-
`selected from the plurality of data signal
`lines, and the
`FET(to be referred to as an NMOShereinafter) 4 connected
`selecteddata signal line can be electrically connected to the
`in series between the terminal GND and the common node
`wiring line 1.
`X. The NMOS4 isatransistor for receiving a precharge
`FIG. 6 is a view showingparasitic capacitances added to
`signal, and a precharge signal PRCH is suppliedto the gate
`the common node X of the integrated circuit device shown
`of the NMOS 4.
`in FIGS. 3 and 4. Similarly, FIG. 7 is a view showing
`One of important functions of the NMOS4 isto set the
`parasitic capacitances added to the common node X of the
`initial state of the potential level of the output signal BO in
`multiplexer shown in FIG. 1, and FIG. 8 is a view showing
`response to the precharge signal. Another function is to
`parasitic capacitances added to the common node X of the
`control activation/inactivation of the integrated circuit
`multiplexer shown in FIG, 2.
`device itself shown in FIG. 1 or 2 in response to the
`As shown in FIG. 6, the integrated circuit device shown
`precharge signal.
`in FIGS. 3 and 4 has only five parasitic capacitances, and
`The NMOS4 is turned on while the signal PRCH is at
`particularly, p-n junction capacitances PN-J added to the
`high level and charges the common node X to the ground
`common node X, ie., four junction capacitances at
`the
`potential. At this time, the initial state of the potential level
`drains of the PMOSs 3-1 to 3-4 whose gates receive the
`of the output signal BOQis set at the ground potential. At the
`selecting signals Ba to Bd, and one junction capacitance at
`same time, the common node X is charged to the ground
`the drain of the NMOS4 whosegate receives the precharge
`potential so that
`the integrated circuit device itself is set
`signal PRCH.
`inactive. More specifically, even when the data signal and
`the multiplexer
`To the contrary, as shown in FIG. 7,
`the data selecting signal are supplied to the data selecting
`shown in FIG. 1 has eight p-n junction capacitances PN-J
`circuit LOO, the potential of the common node X is substan-
`added to the common node X,i.e., four Junction capaci-
`tially equal to the ground potential.
`tances at the drains of the PMOSsofthe CMOStransfergate
`On the other hand, the NMOS4is turned off while the
`circuits, and four junction capacitances at the drains of the
`30
`NMOSs.
`signal PRCH is at low level. At this time, the integrated
`circuit device itself shown in FIG.3 is activated, and the
`common node X is charged to a predetermined potential by
`a current output from the PMOSseries circuits 102.
`‘The basic operationof the integrated circuit device shown
`in FIGS. 3 and 4 will be described below.
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`As shownin FIG. 8, the multiplexer shown in FIG. 2 has
`eight p-n junction capacitances PN-J added to the common
`node X, i.e., four junction capacitances at the drains of the
`PMOSsof the CMOS clocked inverter circuits, and four
`junction capacitances at the drains of the NMOSs.
`Therefore, the integrated circuit device shown in FIGS, 3
`and 4 can act as a multiplexer and also operate at a high
`speed because the parasitic capacitances are largely
`decreased as compared to the multiplexers shown in FIGS.
`1 and 2.
`
`FIG. 5 is a chart of the operating waveforms showing the
`operation of the integrated circuit device according to the
`first embodiment of the present invention.
`In the integrated circuit device shown in FIGS. 3 and 4,
`the data signals A to D correspondingtothe selecting signals
`Ba to Bd of low level are transmitted to the common node
`In addition, the data signals A to D ofhigh level (in a
`X. That is, the precharge signal PRCH is set at high level
`precharge state) go to low level. For this reason, when these
`first, and the common node X is fixed at low level (ground
`signals are set at a level lower than the power supply voltage
`potential) (T1). Thereafter, the precharge signal PRCHis set
`VDD only by the absolute value of a threshold voltage Vth
`45
`at low level (T2), and the common nodeXis set at a floating
`of the PMOS, the PMOSs 2 (2-1 to 2-4) are turned on to
`level (T3). One of the selecting signals Ba to Bd is set at low
`transmit the data signals to the common node X. Therefore,
`level. In this case, assume that the signal Ba is set at low
`the data signals A to D can be quickly transmitted to the
`level (T4). At
`this time, depending on whether the data
`common node X.
`signal A of high level goes to low level or not,
`it
`is
`determined whether the common node X is charged to high
`level or kept at
`low level (low floating level
`in this
`embodiment). In FIG, 5, the data signal A of high level goes
`to low level (TS). Therefore, the common node X is charged
`to high level (T6).
`The precharge levels of the data signals A to D of the
`integrated circuit device shown in FIGS. 3 and 4 are high
`(high-level precharge type).
`In such an integrated circuit
`device of a high-level precharge type, the input data signal
`is transmitted to the common node X depending on whether
`the potential level of the input data signal goesto low ornot.
`If another data signal is to be output after one data signal
`is output, the selecting signal Ba is set at high level (TLL).
`Thereafter, the precharge signal PRCHis set at high level
`(T12), and the common node X is charged to low level
`(ground potential) (T13). With this operation, the integrated
`circuit device is restored from the active period to the
`precharge period. When the above operation is performed
`
`The second embodiment is a detailed application example
`of the present
`invention,
`in which an integrated circuit
`device according to the present invention is used as the data
`multiplex circuit of a dynamic RAM (DRAM).
`FIG. 9 is a block diagram schematically showing a
`DRAM according to the second embodimentof the present
`invention. FIG. 10 is a block diagram showing one of 16
`Mbit-cell arrays shown in FIG. 9 in more detail. FIG. 11 is
`a block diagram showing one of 256 kbit-cell arrays shown
`in FIG. 10 in more detail. FIG. 12 is a circuit diagram
`showing one of DQ buffers shown in FIG. 10 in more detail.
`
`Because ofthese advantages, the integrated circuit device
`shown in FIGS. 3 and 4 operates at a high speed as compared
`to the multiplexers shownin FIGS. 1 and2.
`The basic arrangement and operation have been described
`above.
`
`The second embodimentof the present invention will be
`described below.
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`The DRAM shownin FIG. 9 is a 64 Mbit DRAM.
`
`As shownin FIG. 9, the 64 Mbit DRAM includes four 16
`Mbit-cell arrays A to D.
`As shown in FIG, 10, a row decoder is arranged at the
`center of each 16 Mbit-cell array. Thirteen pairs of row
`addresses AOR to A12R and BAOR to BA12R are supplied
`to the row decoder. A column decoderis arranged at one end
`of the 16 Mbit-cell array. Eight pairs of column addresses
`AOCto ATC and BAOC to BA7C are suppliedto the column
`decoder. The 16 Mbit-cell array also includes 64 256 kbit-
`cell arrays.
`As shownin FIG, 11, bit line pair precharge circuits (PC),
`sense amplifiers (SA), and DQ gates (DQG)are arranged on
`both the sides of a 256 kbit-cell array (ARY). Each bit line
`pair precharge circuit (PC) equalizes the potential difference
`between the bit line pairs (the bit line pair includes a bit line
`BL and an inverted bit line BBL) and precharges the bit line
`pairs. After the bit line pairs are precharged, a data signal is
`read out from a memory cell (CELL). At this time, a small
`potential difference is generated between the bit line pairs.
`The sense amplifier (SA) amplifies this small potential
`difference. The DQ gate (DQG) transmits the data signal
`amplified by the sense amplifier (SA) to a data line pair (the
`DQ line pair includes a DQ line DQ andan inverted DQ line
`BDQ) on the basis of a signal CSL. The signal CSL is a
`signal for selecting a column of the memory cell array,
`which is output from the column decoder. In the DRAM
`according to this embodiment,
`four data line pairs are
`arranged on each side of the 256 kbit-cell array (ARY).
`In the DRAM according to this embodiment,
`the data
`signal amplified by the sense amplifier (SA) is supplied to
`four DQ buffers (DQB) shown in FIG. 11. The data signal
`received by the DQ buffers (DOB) is further amplified by the
`DQ buffers (DQB). The data signal amplified by the DQ
`buffers (DQB)is supplied to a read/write data line pair (the
`read/write data line pair includes a read/write data line RWD
`and an inverted read/write data line BRWD).
`As shown in FIG. 12, the DQ buffer (DQB) includes a DO
`line equalizer 300 for equalizing a potential difference
`between the pair of DQ lines (DQ, BDQ), a transfer gate 302
`for transferring a data signal from the pair of DQ lines to a
`pair ofinternal DQ lines (DQI, BDQIJ), an internal DQ line
`equalizer 304 for equalizing a potential difference between
`the pair of internal DQ lines, a sense amplifier 306 for
`amplifying a potential difference betweenthe pair ofinternal
`DQ lines, and an RWDline pair driving circuit 308 for
`driving a pair of read/write data lines (RWD, BRWD)based
`on data in the internal DQ line pair.
`An RWDline equalizer 310 for equalizing a potential
`difference between the pair of read/write data lines is con-
`nected between the read/write data line RWD and the
`inverted read/write data line BRWD.
`
`The DQ line equalizer 300 includes a PMOS 321 con-
`nected in series between the high potential power source
`terminal VDD and the line DQ, a PMOS 322 connected in
`series between the power source terminal VDDandthe line
`BDQ, and a PMOS 323 connected in series between the
`lines DQ and BDQ. The gates of the PMOSs 321, 322 and
`323 are connected to a line through which a DQ line
`equalizing signal CEQ is supplied.
`The transfer gate 302 includes a PMOS 324 connected in
`series between the lines DQ and DQI and a PMOS 325
`connectedin series between the lines BDQ and BDQI. The
`gates of the PMOSs 324 and 325 are connected to a line
`through which a signal LATCH, which is an inversion ofan
`inverted latch signal BLATCH, is supplied.
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`The internal DQ line equalizer 304 includes a PMOS 326
`connected in series between the power source terminal VDD
`and the line DOI, a PMOS 327 connected in series between
`the power source terminal VDD and the line BDQI, and a
`PMOS328 connected in series between the lines DQI and
`BDOQI. The gates of the PMOSs 326, 327 and 328 are
`connected to a line through which the DQ line equalizing
`signal CEQis supplied.
`The sense amplifier 306 includes a PMOS 329 connected
`in series between the power source terminal VDD and the
`line DOT, a PMOS 330 connected in series between the
`powersource terminal VDDand the line BDQI, an NMOS
`331 connected in series between the line DQI and the line
`through which the inverted latch signal BLATCHis
`supplied, and an NMOS332 connectedin series betweenthe
`line BDOQI and the line through which the inverted latch
`signal BLATCHis supplied. The gate of the PMOS 329 is
`connected to the line BDQI. The gate of the PMOS 330 is
`connected to the line DOI. The gate of the NMOS 331 is
`connected to the line BDOI. The gate of the NMOS 332is
`connected to the line DOI.
`The RWD line pair driving circuit 308 includes a two-
`input NOR gate 333 having an input terminal connected to
`the line DQI, a two-input NOR gate 334 having an input
`terminal connected to the line BDQI, an NMOS 335 con-
`nected in series between the output terminal of the NOR gate
`333 and the low potential power source terminal GND, an
`NMOS336 connected in series