a2 United States Patent
`US 6,300,826 Bl
`(0) Patent No.:
`Oct. 9, 2001
`(45) Date of Patent:
`Matheet al.
`
`US006300826B1
`
`(54)
`
`(76)
`
`APPARATUS AND METHOD FOR
`EFFICIENTLY AMPLIFYING WIDEBAND
`ENVELOPE SIGNALS
`
`Inventors: Lennart Mathe, 6755 Mira Mesa
`Blvd., #123-260, San Diego, CA (US)
`92121; Don Kimball, 12880
`Orangeburg Ave., San Diego, CA (US)
`92129; Joe Archambault, 10540
`Mathieson, San Diego, CA (US) 92129;
`Walter Haley, 2110 DogwoodPL.,
`Escondido, CA (US) 92026
`
`(*)
`
`Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`21)
`
`(22)
`
`(51)
`(52)
`(58)
`
`(656)
`
`Appl. No.: 09/566,194
`
`Filed:
`
`May5, 2000
`
`Tint. C17 oo eccccssseeceeee HO03F 3/38; HO3F 3/68
`
`US. Ce iecceeccceseeeeteeseesceseeeeneneeneenees 330/10; 330/126
`Field of Search. .......0.00. 330/10, 126, 207 A,
`330/136, 251, 149
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,973,556 * 10/1999 SU Loe eeeeceeeteeereeeeee 330/207 A
`6,084,468 *
`7/2000 Sigmonetal.
`.. 330/251
`..
`6,137,358 * 10/2000 Midyaet al.
`... 330/149
`6,175,273 *
`1/2001 Sigmonet al. wee 330/136
`
`
`
`FOREIGN PATENT DOCUMENTS
`
`2262705 * 10/1990 (IP) cecceccceesscsseeceesesenseenes 330/10
`OTHER PUBLICATIONS
`
`Lohrmann “Amplifier has 85% Efficiency” Electronic
`Design; vol. 14, Mar. 1, 1966, pp. 38-43.*
`
`* cited by examiner
`
`Primary Examiner—Michael B Shingleton
`(74) Attorney, Agent, or Firm—Lyon & Lyon LLP
`
`(57)
`
`ABSTRACT
`
`Systems and methods for amplifying an RF input signal
`include employing a moderately powerefficient wide band-
`width device, such as an AB-type amplifier, to amplify the
`powerresiding in the high frequency components of the
`input signal, and a highly powerefficient narrow bandwidth
`device, such as a synchronous buck DC/DC converter, to
`amplify the powerresiding in the low frequency components
`of the input signal. The amplified low frequency components
`and high frequency components are then combined to pro-
`duce an amplified replica of the RF input signal. A positive
`feedback loop is provided between the output of the AB-type
`amplifier and the input of the DC/DC converter to provide
`stability to the amplified RF signal. A negative feedback
`loop is provided between the output of the DC/DC converter
`and the input of the AB-type amplifier to minimize inter-
`ference introduced by the DC/DC converter.
`
`24 Claims, 5 Drawing Sheets
`
`
`R?
`
`\b
`
`|
`
`—~158
`
`118
`
`
`
`
`
`
`126
`
`INTEL 1114
`
`VERROR(I)
`
`|||||||
`
`SEN O
`
`INTEL 1114
`
`

`

`U.S. Patent
`
`Oct. 9, 2001
`
`Sheet 1 of 5
`
`US 6,300,826 B1
`
`100a
`
`RFin
`
`
`
`110
`108
`
`
`
`BUFFER
`AMPLIFIER
`CIRCUIT
`
`SENV
`
`112
`
`114
`
`

`

`U.S. Patent
`
`Oct. 9, 2001
`
`Sheet 2 of 5
`
`US 6,300,826 B1
`
`RFin = A(t)cos(@e*t+¢t)
`
`
`
` CDMASIGNAL
`
`Qo
`
`2
`
`50
`
`100
`
`150
`
`200
`
`250
`
`300
`
`FIG. 2
`
`Sgnv =A(t)
`
`
`
`50
`
`100
`
`150
`
`200
`
`250
`
`300
`
`FIG. 8
`
`zZ 2
`
`&~
`
`0
`
`2
`
`0
`
`* a
`
`ea==
`
`Sg=cos(W.*+9t)
`
`SIGNAL
` PHASE
`
`FIG. 4
`
`

`

`U.S. Patent
`
`Oct. 9, 2001
`
`Sheet 3 of 5
`
`US 6,300,826 B1
`
`RFout = A’(t)cos(@c*t+¢t),
`
`
`
`CDMASIGNAL
`
`
`
`Wha|Lara
`
`
`WEEE
`
`
`
`FIG. 5
`
`

`

`U.S. Patent
`
`Oct. 9, 2001
`
`Sheet 4 of 5
`
`US 6,300,826 B1
`
`si
`
`961
`
`
`
`
`
`
`
`
`
`ASINdA
`
`7ol——44
`
`9‘OIAAY
`
`GYMOMAR=WyS|
`
`
`
`
`
`
`3SIONA|ANA|
`
`OANAS
`
`Bit
`
`
`
`
`
`
`
`
`
`

`

`U.S. Patent
`
`Oct. 9, 2001
`
`Sheet 5 of 5
`
`US 6,300,826 B1
`
`110oN
`
`128
`
`(SENVI))
`
`/2(f
`
`/t(p
`
`vo) LEN)|
`
`Vewyy)
`
`vagy
`
`SENV
`
`POWER
`
`AMPLIFIED BY
`HIGHLY EFFICIENT
`NARROW BANDWIDTH
`DEVICE
`
`AMPLIFIED BY
`MODERATELY EFFICIENT
`WIDE BANDWIDTH
`DEVICE
`
`FIG. 6
`
`

`

`US 6,300,826 B1
`
`1
`APPARATUS AND METHOD FOR
`EFFICIENTLY AMPLIFYING WIDEBAND
`ENVELOPE SIGNALS
`FIELD OF THE INVENTION
`
`2
`an amplifier for a variety of purposes, which mayinclude the
`provision of DC powerto an RF power amplifier within an
`EER amplifier system.
`
`SUMMARYOF THE INVENTION
`
`15
`
`,
`
`The present invention relates generally to amplifiers, and
`The present inventionis directed to systems and methods
`more particularly to high frequency wide bandwidth ampli-
`for efficiently amplifying relatively wide bandwidth signals.
`fiers.
`In accordance withafirst aspect of the present inventions,
`BACKGROUND
`10
`a method can be employed to amplify an input signal (e.g.,
`In the wireless communications industry, a premium is
`an envelope signal obtained from a CDMAsignal), which
`placed onthe ability to amplify wide bandwidthsignals,e.g.,
`exhibits one or more lower frequency components and one
`spread spectrum signals, in a highly efficient manner. As an
`or more higher frequency components. It should be under-
`example, a typical eighteen-channel base station requires
`stood that “lower” and “higher”are relative terms, and are
`approximately 540 watts of RF power output (30 watts per
`only meant to define a frequency component wilh respect to
`each channel). Assuming a typical power amplifier effi-
`another frequency component. It should also be understood
`ciency of 5 percent, the amount of power needed to generate
`that a lower frequency component may encompass a DC
`an RI’ poweroutput of 540 watts will be 10.8 kW, with 10.26
`component. The method includes generatingafirst signal by
`kW being dissipated as heat. This dissipated heat represents
`amplifying the input signal, sensing the first signal (e.g., the
`a drawback in that it not only requires the use of fans and ,
`current), and generating a second signal by amplifying the
`heat sinks to cool the base station, but also translates to
`powerresiding in the one or more lower frequency compo-
`wasted energy, thereby reducing battery life. In short, the
`nents of the first signal. The power residing in the one or
`cost of the base station increases as the efficiency of the
`more lower frequency components of the first signal
`is
`power amplifiers used in the base station decreases.
`inversely varied with the second signal. In effect, amplifi-
`cation of the power residing in the one or more lower
`Although various attempts have been madeto address this ,
`frequency components of the input signal is minimized
`problem,
`it remains difficult
`to design a high efficiency
`during the first stated amplification, and maximized during
`power amplifier that is able to lincarly amplify wide band-
`the second stated amplification. The first and second signals
`width signals. This is due to the paradoxical nature of a
`are then combined to produce an amplified input signal. The
`typical amplifier, which exhibits a wide bandwidth capabil-
`positive feedback provided from the sensed first signal to the
`ity that is inversely proportionaltoits efficiency. The ampli-
`amplification of the second signal provides stability to the
`fication of spread spectrum signals, such as code division
`amplified input signal. Optionally, the second signal can be
`multiple access (CDMA)signals, which typically have high
`sensed (e.g.,
`the voltage) and the input signal inversely
`peak-to-average signal amplitude ratios, makeit difficult, if
`varied with the sensed secondsignal, e.g., to minimize noise
`not impossible, to continuously operate the power amplifier
`otherwise created during the second stated amplification.
`in saturation, thereby reducing the efficiency of a power ,
`amplifier even further.
`The bandwidth of the input signal may berelatively wide,
`A method that has been proposed to solve this problem
`e.g., between 0 MHz and 10 MHz.In such a case, the one
`involves the use of envelope elimination and restoration
`or more lower frequency components will make up a rela-
`(EER), which is a technique through which highly efficient
`tively narrow range within the bandwidth, e.g., between 0
`radio frequency (RF) power amplifiers can be combined to
`MHz and 1 MHz, and the one or more higher frequency
`produce a high efficiency linear amplifier system. In this
`components will make uparelatively higher range within
`method, a modulated input signal is split into two paths: an
`the bandwidth, e.g., between 1 MHz and 10 MHz.In such
`amplitude path through which the envelope of the modulated
`a case, amplification of the one or more high frequency
`input signal is processed, and a phase path through which the
`components is preferably accomplished at a first power
`phase modulated carrier of the modulated input signal is
`efficiency, and amplification of the one or more lowfre-
`processed. The envelope of the modulated input signal is
`quency components is preferably accomplished al a second
`amplified through a highly efficient amplifier, which oper-
`higher powerefficiency. As a result, the power within the
`ates at the narrower modulated bandwidth, ie., the band-
`narrower low frequency range is efficiently amplified, and
`width of the envelope,
`thereby producing an amplified
`the power within the wider high frequency range is ampli-
`envelope signal. A high frequency, highly efficient amplifier
`fied substantially tree of distortion.
`is then used to modulate the high frequency phase modu-
`In accordance with a second aspect of the present
`lated carrier with the amplified envelope signal, thereby
`inventions, an amplifier circuit is provided for amplifying an
`generating an amplified replica of the modulated input
`input signal, e.g., an envelope signal extracted from a
`signal. Specifically, the amplifier that generates the ampli-
`CDMA signal. The amplifier circuit includes an AB-type
`fied envelope signal acts as the DC powersupply to the high
`amplifier, which is configured to receive the input signal,
`frequency amplifier. The efficiency of this EER amplifier
`and a synchronous buck DC/DC converter,
`the input of
`system can be calculated by multiplying the efficiencies of
`which is coupled to the output of the amplifier through a
`the two amplifiers. For example, if the efficiency of each of
`positive feedback loop. A resistive load is coupled in parallel
`the amplifiers is 50%,
`the total efficiency of the EER
`between the respective outputs of the AB-type amplifier and
`amplifier system will be 25%.
`the DC/DC converter.
`In the preferred embodiment,
`the
`Although the use of an EER amplifier system to amplify
`positive feedback loop includes a current sensor coupled to
`wide bandwidth modulated signals is, in general, beneficial,
`the output of the AB-type amplifier, and a pulse width
`its efficiency and maximum modulation bandwidth is depen-
`modulator coupled between the current sensor and the input
`of the DC/DC converter. The sensed current is driven to a
`dent uponthe efficiency and bandwidth of the power supply
`amplifier.
`relatively low value due to the feedback process, such that
`Accordingly, it would be desirable to provide apparatus
`mostly the higher frequency components remain in the
`and methods for increasing the efficiency and bandwidth of
`sensed current. Optionally, a negative feedback loop can be
`
`40
`
`45
`
`60
`
`65
`
`

`

`US 6,300,826 B1
`
`3
`coupled between the output of the DC/DC converter and the
`input of the AB-type amplifier. The negative feedback loop
`may include a differential operational amplifier having an
`output coupled to the input of the AB-type amplifier, an
`inverting input coupled to the output of the converter, and a
`noninverting input for receiving the input signal.
`In accordance with a third aspect of the present
`inventions, an amplifier circuit is provided for amplifying an
`input signal. The amplificr circuit compriscs a dependent
`voltage source, e.g., an AB-type RF amplifier, that operates
`at a first bandwidth and a first power efficiency, and a
`dependent current source, e.g., a synchronous buck DC/DC
`converter, that operates at a second bandwidth narrower than
`the first bandwidth and a second powerefficiency greater
`than the first powerefficiency. The dependent voltage source
`is configured to generate a first voltage that varies with the
`input signal, and the dependent current source is configured
`to generate a second current that varies with a first current
`produced by the dependent voltage source. A load is coupled
`in parallel between the dependent voltage source and the -
`dependent current source, wherein the first voltage appears
`across the load, and thefirst and second current flow through
`the load.
`
`10
`
`15
`
`Optionally, the dependent voltage source is configured,
`such that the first voltage inversely varies with a second *
`noise voltage generated by the current source. In the pre-
`ferred embodiment,
`the first bandwidth encompasses the
`second bandwidth, with the second bandwidth being at the
`lower end of the first bandwidth. For example,
`the first
`bandwidth can range from 0 MHz to 10 MHz, with the
`second bandwidth ranging from 0 MHz to 1 MHz.
`Other objects and features of the present invention will
`become apparent
`from consideration of the following
`description,
`taken in conjunction with the accompanying
`drawings.
`
`BRIEF DESCRIPTION OF THE DRAWING
`
`Preferred embodiments of the present invention are illus-
`trated by way of example, and not by way of limitation, in
`the figures of the accompanying drawings, in which like
`reference numerals refer to like components, and in which:
`FIG. 1 is a schematic block diagram of an EER system
`constructed in accordance with present inventions;
`FIG. 2 is a plot of an exemplary CDMAsignal input into
`the EER system of FIG. 1;
`FIG. 3 is a plot of the envelope of the CDMAsignal of
`FIG. 2;
`FIG. 4 is a plot of the phase modulated carrier of the
`CDMAsignal of FIG.2;
`FIG. 5 is a plot of the amplified CDMAsignal of FIG. 2;
`FIG. 6 is a schematic diagram of a buffer amplifier circuit
`employed within the EER system of FIG. 1;
`FIG. 7 is a functional block diagram of the buffer ampli-
`fier circuit of FIG. 5; and
`FIG. 8 is a spectral power plot of an exemplary envelope
`signal input into the buffer amplifier circuit of FIG. 5.
`
`DETAILED DESCRIPTION OF‘THE
`PREFERRED EMBODIMENTS
`
`Referring to FIG. 1, an envelope elimination and resto-
`ration (EER) system 100, which is constructed in accor-
`dance with the present inventions, is generally shown. The
`EER system 100 comprises an RF input 102 into which a
`radio frequency (RF) signal RF,, is input, and an RF output
`
`40
`
`45
`
`60
`
`65
`
`4
`104 from which an amplified RF signal RFoz-7 is output. In
`the illustrated embodiment, the input signal RF,,, 1s a code
`division multiple access (CDMA) signal, an exemplary
`waveform of whichis depicted in FIG. 2. As can be seen, the
`input signal RF,,, is modulated both in amplitude and phase,
`and can thus be represented by the equation: RF,,=A(t)cos
`[we*t+t], where A is the amplitude modulation coefficient,
`we is the carrier frequency, t is time, and
`is the phase
`modulation coefficient. Without modification, amplification
`of the input signal RF,,, would be relatively inefficient due
`to the relatively high peak-to-average amplitude ratio. The
`EERsystem 100, however, is configured to amplify the input
`signal RF,,, in a more efficient manner. To this end, the EER
`system 100 generally comprises a power divider 106, enve-
`lope detector 108, buffer amplifier circuit 110, time delay
`element 112, limiter 114, and RF power amplifier 116.
`The power divider 106 splits the input signal RF,, into an
`amplitude path and a phase path. With regard to the ampli-
`tude path, the envelope detector 108 detects the envelope
`from the input signal RF,,’, and generates an envelope signal
`Senv in response thereto. The envelope signal S;ay, repre-
`sents the amplitude information of the input signal RF,,y. As
`can be scen from an exemplary waveform of the envclope
`signal S,;,y,depicted in FIG. 3, the relatively high frequency
`components of the input signal RF,,, have been removed,
`leaving a relatively low frequency envelope signal Sj,
`equal to the time-varying amplitude modulation coefficient
`A(t). As will be discussed in further detail below,
`the
`envelope signal S,yy is efficiently amplified through the
`buffer amplifier circuit 110, generating an amplified enve-
`lope signal S;,;’. Because the envelope signal S,-a,, has a
`relatively low frequency, the buffer amplifier circuit 110 is
`operated at a relatively low bandwidth, thereby improving
`its efficiency. With regard to the phase path, the time delay
`element 112 produces a delayed input signal RF,,,,,, with the
`delay selected to be equal to that introduced by the buffer
`amplifier circuit 110 in the amplitude path. Of course, if the
`delay introduced in the amplitude path is minimal or
`nonexistent, the time delay clement 112 can be climinated.
`The limiter 114 limits the amplitude of the delayed input
`signal RF;y,,, generating a phase signal Sj. that represents
`the phase modulated carrier of the input signal RF/,,. As can
`be seen from an exemplary waveform of the phasesignal Sy,
`depicted in FIG. 4, the amplitude varianceof the input signal
`Ry, has been removed, leaving a relatively high frequency
`signal with a uniform amplitude equal to the phase modu-
`lated carrier cos[me*t+ot]. The phase signal Sy, is amplified
`through the RF power amplifier 116, the efficiency of which
`is improved by the uniformity of
`the phase signal
`S,amplitude. To this end, the amplitude of the phase signal
`Sy is preferably selected to maintain operation of the RF
`power amplifier 116 in saturation.
`is modulated with the
`The amplified phase signal Sg,
`amplified envelope signal S,-,,,to produce the amplified RF
`output signal RFoy,. Specifically, the bias (in the case of
`JFET-based RF power amplifier, the drain bias) is varied in
`accordance with the amplified envelope signal S,,,,, which
`is applied to the DC power terminal of the RF power
`amplifier 116 as a time-varying DC supply voltage Vp.
`Thus, the DC supply voltage V,, appears on the output of
`the RF power amplifier 116, which, in effect, modulates the
`phase signal Sy. with the supply voltage Vp. The waveform
`of the output signal RF,,,; is exemplified in FIG. 5. As can
`be scen, the output signal RFo;,7 is an amplified replica of
`the input signal RF,,, and is represented by the equation
`RFoz-7=A'(t)coslmc*t+ot], with A’ being equal to the ampli-
`fied amplitude modulation coefficient.
`
`

`

`US 6,300,826 B1
`
`10
`
`15
`
`5
`Because the efficiency and bandwidth performance of the
`EER system 100 is dependent on the efficiency and band-
`width performanceof the buffer amplifier circuit 110 used in
`the amplitude path,
`the buffer amplifier circuit 1 10 is
`configured to efficiently and linearly amplify the envelope
`signal S,ax, by amplifying the power residing in the rela-
`tively low frequency components of the envelope signal
`Sevyy With a device exhibiting a relatively high power
`efficiency and narrow bandwidth performance, and ampli-
`fying the power residing in the relatively high frequency
`components of the envelope signal S,.,, with a device
`exhibiting a relatively moderate power efficiency and wide
`bandwidth performance.
`To this end, and with reference to FIG. 6, the buffer
`amplifier circuit 110 is shown with an input 118 on which the
`envelope signal S,.,, appears, and an output 120 on which
`the amplified envelope signal S,,,' appears. The amplifier
`circuit 110 generally includes an AB-type RF amplifier 122,
`which is a moderately power efficient device having high
`bandwidth capabilities, and a synchronous buck DC/DC .
`converter 124, whichis a highly efficient device having low
`bandwidth capabilities. With this said, the AB-type amplifier
`122 is advantageously employed by the amplifier circuit 110
`to amplify the power residing in the relatively high fre-
`quency components of the envelope signal Spay, thereby ,
`providing the amplifier circuit 110 with wide bandwidth
`capability. The DC/DC converter 124 is employed by the
`amplifier circuit 110 to amplify the powerin the relatively
`low frequency components of the envelope signal S,a,,.
`providing the amplifier circuit 110 with increased power ,
`efficiency.
`The amplifier circuit 110 further comprises a positive
`current feedback loop 126 coupled between an output 132 of
`the AB-type amplifier 122 and an input 134 of the DC/DC
`converter 124, as well as a negative voltage feedback loop 3
`128 coupled between an output 136 of the DC/DC converter
`124 and an input 130 of the AB-type amplifier 122. As will
`be described in further detail below, the current and voltage
`feedback loops 126 and 128 advantageously provide bilat-
`eral feedback between the AB-type amplifier 122 and
`DC/DC converter 124, thereby ensuring that the amplifier
`circuit 110 generates a substantially stable and distortion-
`free amplified envelope signal Spyy’.
`We nowdescribe the structure of the amplifier circuit 110
`in further detail. It is noted that for purposes of brevity in
`illustration, only the components and connections necessary
`to describe the functionalities of the amplifier circuit 110 are
`depicted in FIG. 6. The amplifier circuit 110 may, in fact,
`include more components and connections than those shown
`in FIG. 6.
`
`40
`
`45
`
`The AB-type amplifier 122 can be characterized as a
`push-pull voltage follower. To this end, the AB-type ampli-
`fier 122 comprises upper and lowertransistors Q1 and Q2,
`which in the illustrated embodiment, comprise N-channel
`and P-channel MOSFET’s, respectively. The sources of the
`transistors Q1 and Q2 are coupled together to form the
`output 132 of the AB-type amplifier 122, with the drain of
`the upper transistor Q1 being coupled to a positive DC
`voltage source, e.g., 11V, and the drain of the lower tran-
`sistor Q2 being coupled to a negative DC voltage source or
`ground, ¢.g., -1V.It is noted that the negative DC voltage
`allows the output 132 of the AB-type amplifier 122 to be
`pulled down to OV if necessary, which would otherwise be
`difficult, if not impossible, to accomplish if the drain of the
`transistor Q2 were instead coupled to ground. Thus,
`the
`uppertransistor Q1 provides the AB-type amplifier 122 with
`a voltage pull-up capability, and the lower transistor Q2
`
`60
`
`65
`
`6
`provides the AB-type amplifier 122 with a voltage pull-
`down capability.
`The AB-type amplifier 122 further includes a biasing
`circuit coupled between a DC voltage source, e.g., 18V, and
`the gates of the transistors Q1 and Q2. Specifically, a current
`source, composed ofparallel transistors Q3 and 04 (in this
`case, JFET’s), feeds current from the DC voltage source to
`the gates oftransistors Q1 and Q2, with resistors R1, R2, and
`R3 providing selectable bias points for the transistors QL
`and Q2. By way of nonlimiting example,
`the values of
`resistors R1, R2, and R3 can be selected to be 2K Q, 10 Q,
`and 2 Q, respectively.
`The input 118 of the amplifier circuit 110 is coupled to the
`input 130 of the AB-type amplifier 122 via a differential
`operational amplifier U1. For purposesthat will be described
`in further detail below, the operational amplifier U1 deter-
`mines the difference between an envelope voltage Vp-aq,
`obtained from the envelope signal S,,,, and a noisy voltage
`Vworsr Obtained from the output 136 of the DC/DC con-
`verter 124, generating a difference envelope voltage Varay
`at
`its output. The difference envelope voltage Vapay 1S
`applied to the gates of the transistors Q1 and Q2 via a
`capacitor Cl and the biasing circuit. In response to the
`difference envelope voltage Varyy, the AB-type amplifier
`122 generates a first signal S,, which is represented by a
`voltage V, and a current I,.
`Thefirst signal S,. is an amplified version of the envelope
`signal S-yy, and, taking the AB-type amplifier 122 by itself,
`would be an amplified replica of the envelope signal Spay,
`due to the wide bandwidth capability of the AB-type ampli-
`fier 122. As will be discussed in further detail below,
`however, the amplifier circuit 110 is configured, such that
`the AB-type amplifier 122 amplifies the power residing in
`the high frequency components of the envelope signal S,,
`with little or no power in the low frequency components of
`the envelope signal S,, being amplified by the AR-type
`amplifier 122.
`The DC/DC converter 124 is generally composed of
`upper and lower switching transistors Q5 and Q6, an induc-
`tive clement L1, and a control device U2. In the illustrated
`embodiment, the transistors Q5 and Q6 comprise JFET’s,
`and the inductive element I.1 has a suitable inductance
`
`value, e.g., 10 wH. In the illustrated embodiment, the control
`device U2 is embodied in an integrated circuit, which can be
`obtained from National Semiconductor located in Santa
`Clara, Calif. Of course, while an integrated device is
`preferable, any analog or digital circuit, discrete or
`integrated, or combinations thereof may be utilized if the
`functionalities of the invention may be achieved.
`Undercontrol of the control device U2, the transistors Q5
`and Q6, which in the illustrated embodiment comprise
`N-channel JFET’s, are switched opened and closed in a
`mannerthatalternately charges and discharges the inductive
`element L1. Specifically, the source and drain of the respec-
`tive transistors Q5 and Q6 are coupled together, with the
`drain of the upper transistor Q5 being coupled to a DC
`voltage supply, e.g., 11V, and the source of the lower
`transistor Q6 being coupled to ground. The gates of the
`upper and lower transistors Q5 and Q6 are respectively
`coupled to the DRVH and DRVLpinsof the control device
`U2. In this manner, the uppertransistor Q5 can be alternately
`closed (i.e., it represents a virtual short circuit) and opened
`(i.e.,
`it represents a virtual open circuit) by respectively
`transmitting high and lowsignals from the DRVH pin of the
`control device U2. Likewise, the lowertransistor Q6 can be
`alternately closed and opened by respectively transmitting
`high and low signals from the DRVL pin of the control
`device U2.
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`US 6,300,826 B1
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`10
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`15
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`20
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`The control device U2 effects the switching of the tran-
`sistors Q1 and Q2 in accordance with a control voltage
`Vpursr input into pin VIN. That is, when the control voltage
`Vpurse iS high, the control device U2 closes the upper
`transistor Q5 and opens the lower transistor Q6, thereby
`charging the inductive element L1. In contrast, when the
`control voltage Vprzs¢ 1s low, the control device U2 opens
`the upper transistor Q5 and closes the lowertransistor Q6,
`thereby discharging the inductive element L1. In response to
`the charging and discharging of the inductor L1, the DC/DC
`converter 124 generates a second signal S,, which is repre-
`sented by a voltage V, and a current 1,.
`As will be described in further detail below, the control
`voltage Vpyzsr 1S derived from the first amplified signalS,,
`whichis in turn, derived from the envelope signal Spxyy. In
`this respect, the second signal S, is an amplified version of 2
`the envelope signal S-,,. Due to the narrow bandwidth
`capability of the DC/DC converter 124, however, only the
`power residing in the low frequency components of the
`envelope signal S;yyv are amplified through the DC/DC
`converter 124.
`
`8
`7
`resistors R8 and R9 can be 316 ohmsand 953 ohms, with the
`To ensure that the switching transistors Q5 and Q6 are
`value of the voltage supply being 2.5V, thereby providing
`either substantially closed, or substantially open, Le., an
`the output of the operational amplifier U3 with a 2.5V offset.
`indefinite mode does not exist, the switching transistors Q5
`A resistor R10 is used to buffer the inverting input of the
`and Q6 are suitably biased. Specifically, a current source,
`operational amplifier U3.
`and in this case, a transistor Q7 (e.g., JFET), feeds the drains
`of the switching transistors Q5 and Q6 throughaparallel
`It should be noted that, to minimize the dissipation of
`combination of a capacitor C2 and Zener diode D1. The bias
`power within the current feedback loop 126, the resistance
`level can be adjusted by pins BST and SW ofthe control
`value of resistor R4 is preferably as small as practically
`device U2.
`possible, c.g., 0.01 ohms.
`In this case,
`the opcrational
`amplifier U3 is configured to be relatively sensitive to the
`small voltage produced by the resistor R4, in which case the
`differential gain and offset of the operational amplifier U3
`should be as precise as possible.
`The pulse width modulator 140 comprises a comparator
`U4, which compares the voltage of the error voltage Vierror
`to a threshold, outputting a high signal when the error
`voltage Virror 1S above the threshold, and outputting a low
`signal whenthe error voltage V-reop is below the threshold.
`Specifically, the noninverting input of the comparator U4 is
`coupled to the output of the operational amplifier U3
`through a buffer resistor R11, whichhasa suitable resistance
`value, e.g., 50 ohms. The inverting input of the comparator
`U4 is coupled to a DC reference voltage, e.g., 2.5V. The
`positive and negative terminals of the comparator U4 are
`respectively coupled to a DC supply voltage, e.g., 15V, and
`to ground.
`Thus, when the error voltage Verror ts greater than the
`reference voltage, the comparator U4 outputs a high voltage,
`and whenthe error voltage Verror IS less than the reference
`voltage,
`the comparator U4 outputs a low voltage. The
`output of the comparator U4 is coupled to a DC voltage
`supply, e.g., 5V,
`to translate the level of the high output
`voltage to that of the DC voltage supply. Thus, if the DC
`voltage supply is 5V, the output of the comparator U4 will
`toggle between OV and 5V.
`To provide the comparator U4 with hysteresis, a resistor
`R12is coupled between the supply voltage and the output of
`the comparator U4, and a resistor R13 is coupled between
`the output and noninverting input of the comparator U4.
`Thus, if the output of the comparator U4 is high, the error
`voltage Ve-rror Will have to be a predetermined value below
`the reference voltage for the output of the comparator U4 to
`transition from high to low. Likewise, if the output of the
`comparator U4 is low,the error voltage Vie-zror Will have to
`be a predetermined value above the reference voltage for the
`output of the comparator U4to transition from low to high.
`This predetermined valueis set by selecting the value of the
`resistors R12 and R13. By way of nonlimiting example, if
`the valueofthe resistors R12 and R13 are 1k ohmsand 49.9
`Kohms,respectively, the predetermined value will be 0.1V,
`assuming that the supply voltage is 5V.
`Thus, the alternating high and low voltages output from
`the comparator U4 are input into the control device U2 of
`DC/DC converter 124 as the control voltage Vpzz7s-. AS
`discussed above, the inductive element L1 is charged in
`response to the highs within the control voltage Vpzyz-,
`thereby increasing the power in the second signal S,, and
`discharged in response to the lows within the control voltage
`Vpurse thereby decreasing the powerin the second signal
`S,. In this manner, the second signal S, output from the
`DC/DC converter 125 discretely tracks the first current S1
`output from the AB-type amplifier 122, thereby providing
`stability to the amplified envelope signal S,,,/ generated on
`the output 120 of the amplifier circuit 110.
`As briefly discussed above, a voltage feedback loop 128
`is coupled between the output 136 of the DC/DC converter
`
`As will be described in further detail below,the first signal
`S, output from the AB-type amplifier 122 and the second
`signal S, output from the DC/DC converter 124 are super-
`imposed at the output 120 of the amplifier circuit 110 to
`generate the amplified envelope signal S,,,/, which is an
`amplified replica of the envelope signal Spay.
`As briefly discussed above, the current feedback loop 126
`is coupled between the output 132 of the AB-type amplifier
`122 and the input of the DC/DC converter 124 to provide
`stability to the amplified envelope signal S,.,,,/. To this end,
`the current feedback loop 126 generally includes a current
`sensor 138, which generates an error vollage Verror indica-
`tive of the first current I,, flowing from the output 132 ofthe
`AB-type amplifier 122. The current feedback loop 126
`further includes a pulse width modulator 140, which gen-
`erates the control voltage Vp;.<; aS a function of the error
`voltage Verror Output from the current sensor 138.
`Specifically, the current sensor 138 includesa resistor R4,
`whichis coupled to the output 132 of the AB-type amplifier
`122, and a differential operational amplifier U3, the nonin-
`verting and inverting inputs of which are coupled across the
`resistor R4. Thus,the first current I,, flows acrossthe resistor
`R4, which is,
`in turn, amplified through the operational
`amplifier U3 to the output
`thereof as the error voltage
`Verror: lhe positive and negative terminals of the opera-
`tional amplifier U3 are respectively coupled to a DC supply
`voltage, e.g., 15V, and to ground. Resistors R5, R6, and R7
`are used to select the differential gain of the operational
`amplifier U3. By way of nonlimiting example, the resistance
`values of resistors R5, R6, and R7 can be 397 ohms, 397
`ohms, and 10 ohms respectively,
`thereby providing the
`operational amplifier U3 with a differential gain of twenty-
`five. So that the crror voltage Verror 1S maintained at a
`positive level, the output of the operational amplifier U3 is
`offset by resistors R8 and R9 and a DC voltage supply. By
`way of nonlimiting example, the resistance values of the
`
`40