UNITED STATES PATENT AND TRADEMARK OFFICE
`
`________________________
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`________________________
`
`
`ARM Ltd. and ARM, Inc.,
`
`Petitioners
`
`v.
`
`Advanced Micro Devices, Inc. and ATI Technologies ULC, Patent Owner
`
`U.S. Patent 7,633,506
`Issue Date: December 15, 2009
`Title: Parallel Pipeline Graphics System
`
`________________________
`
`
`CASE: IPR2018-1149
`
`
`________________________
`
`
`Petition for Inter Partes Review of U.S. Patent 7,633,506
`
`________________________
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`
`
`
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`
`

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`Petition for Inter Partes Review of U.S. Pat. No. 7,633,506
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`
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`EXHIBIT LIST
`
`Ex. 1001 U.S. Patent No. 7,633,506 (“the ’506 Patent”).
`
`Ex. 1002
`(Excerpts).
`
`File History of U.S. Patent No. 7,633,506. (“File History”)
`
`Ex. 1003 Declaration of Dr. Hanspeter Pfister
`
`Ex. 1004 U.S. Patent No. 7,102,646 (“Rubinstein”)
`
`Ex. 1005 U.S. Patent No. 6,697,063 (“Zhu ’063”)
`
`Ex. 1006 U.S. Patent No. 6,856,320 (“Zhu ’320”)
`
`Ex. 1007 U.S. Patent Application Publication No. US 2003/0076320A1
`(“Collodi”)
`
`Ex. 1008 U.S. Patent No. 6,809,732 (“Zatz”)
`
`Ex. 1009 April 26, 2000 Press release describing Nvidia GeForce 2 Graphics
`Chip
`
`Ex. 1010
`
`January 5, 2001 Article describing Nvidia GeForce 3 Graphics Chip
`
`Ex. 1011
`
`Initial Determination in U.S. International Trade Commission Inv.
`No. 337-TA-1044
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`
`
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`Petition for Inter Partes Review of U.S. Pat. No. 7,633,506
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`TABLE OF CONTENTS
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`Page
`
`
`
`I.
`
`PRELIMINARY STATEMENT AND MOTION FOR JOINDER
`REFERENCE ................................................................................................. 1
`
`II.
`
`INTRODUCTION .......................................................................................... 3
`
`III.
`
`37 C.F.R. § 42.8(b): MANDATORY NOTICES .......................................... 5
`
`A.
`
`B.
`
`C.
`
`37 C.F.R. § 42.8(b)(1): Real Party In Interest ..................................... 5
`
`37 C.F.R. § 42.8(b)(2): Related Matters .............................................. 6
`
`37 C.F.R. § 42.8(b)(3) and (4): Notice Of Counsel And Service
`Information .......................................................................................... 7
`
`D.
`
`Fees under 37 C.F.R. § 42.103 ............................................................ 8
`
`IV. REQUIREMENTS FOR INTER PARTES REVIEW .................................... 8
`
`A.
`
`B.
`
`37 C.F.R. § 42.104(a): Ground For Standing ...................................... 8
`
`37 C.F.R. § 42.104(b): Identification Of Challenge ............................ 8
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`37 C.F.R. § 42.104(b)(1) Challenged Claims ............................ 8
`
`37 C.F.R. § 42.104(b)(2): The Prior Art And Statutory
`Grounds. .................................................................................... 9
`
`Level of Ordinary Skill in the Art ............................................. 9
`
`37 C.F.R. § 42.104 (b)(3) Claim Construction ........................10
`
`37 C.F.R. § 42.104(b)(4) How the Claims are Unpatentable. .10
`
`Supporting Evidence ................................................................10
`
`V.
`
`THERE EXISTS A REASONABLE LIKELIHOOD THAT THE
`CHALLENGED CLAIMS ARE UNPATENTABLE. ................................11
`
`A.
`
`B.
`
`C.
`
`D.
`
`
`
`Technology Background ....................................................................11
`
`The Alleged Invention of the ’506 Patent. .........................................14
`
`Prosecution History of the ’506 Patent ..............................................20
`
`Proposed Claim Construction ............................................................21
`
`1.
`
`2.
`
`Z-Buffer Logic Unit .................................................................22
`
`“Hierarchical Z-Interface” .......................................................22
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`Petition for Inter Partes Review of U.S. Pat. No. 7,633,506
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`“Early Z-interface” and “Late Z-interface” .............................23
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`3.
`
`E.
`
`Ground 1: Obviousness by Rubinstein in view of Collodi (Claims 1-
`9) ........................................................................................................26
`
`1.
`
`2.
`
`Rubinstein ................................................................................26
`
`Collodi .....................................................................................29
`
`3. Motivation to Combine ............................................................31
`
`4.
`
`5.
`
`6.
`
`7.
`
`8.
`
`9.
`
`Claim 1 .....................................................................................38
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`Claim 2 .....................................................................................51
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`Claim 3 .....................................................................................53
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`Claim 4 .....................................................................................58
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`Claim 5 .....................................................................................61
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`Claim 6 .....................................................................................63
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`10. Claim 7 .....................................................................................66
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`11. Claim 8 .....................................................................................69
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`12. Claim 9 .....................................................................................72
`
`F.
`
`Ground 2: Obviousness by Rubinstein in view of Collodi in further
`view of Zatz (Claims 8-9) ..................................................................73
`
`1.
`
`Zatz ..........................................................................................73
`
`2. Motivation to Combine ............................................................74
`
`3.
`
`4.
`
`Claim 8 .....................................................................................76
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`Claim 9 .....................................................................................80
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`VI. CONCLUSION ............................................................................................82
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`
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`Petition for Inter Partes Review of U.S. Pat. No. 7,633,506
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`I.
`
`PRELIMINARY STATEMENT AND MOTION FOR JOINDER
`REFERENCE
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`Petitioners ARM, Inc. and ARM Ltd. (“Petitioners”) respectfully request
`
`inter partes review and seek cancellation of claims 1-9 of U.S. Patent No.
`
`7,633,506 (the “’506 Patent”) under 35 U.S.C. §§ 311-319 and 37 C.F.R. § 42.100
`
`et seq. The Board previously instituted inter partes review of claims 1-9 of the
`
`’506 Patent in IPR2018-00102 on April 27, 2018. Petitioners seek to join
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`IPR2018-00102 and are filing a concurrent Motion for Joinder. This Petition and
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`the associated Motion for Joinder are timely under 37 C.F.R. §§ 42.22 and
`
`42.122(b), as they are submitted within one month of the date on which IPR2018-
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`00102 was instituted. Petitioners have consulted with the petitioners in IPR2018-
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`00102 and the Patent Owners. The petitioners in IPR2018-00102 do not oppose
`
`this motion for joinder. The Patent Owners did not provide a position on this
`
`joinder.
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`Joinder is appropriate because of the substantial similarity between
`
`IPR2018-00102 and the present Petition. The present Petition is largely a verbatim
`
`copy of the Petition in IPR2018-00102 with limited changes as cited below.
`
`Petitioners have retained the same expert as the Petitioners in IPR2018-00102 and
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`the expert’s declaration is substantively identical to that in IPR2018-00102. For
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`the convenience of the Board and parties, Petitioners have used the same Bates
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`1
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`Petition for Inter Partes Review of U.S. Pat. No. 7,633,506
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`stamping on exhibits and the same paragraph citations to the expert reports.
`
`As noted in the Motion for Joinder, other factors relevant to joinder also
`
`favor granting this motion, including that: (i) the same schedule for various
`
`proceedings can be adopted; (ii) Petitioners are not advancing any new expert
`
`testimony, and thus, discovery will not be impacted by joinder; (iii) joinder will not
`
`materially affect the range of issues needing to be addressed by the Board and by
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`the parties in the joined proceedings; (iv) joinder will not prejudice any party; and
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`(v) Petitioners are willing to agree to procedural safeguards to minimize burden.
`
`See Kyocera Corp. v. Softview LLC, IPR2013-00004, Paper 15 at 4 (Apr. 24,
`
`2013). As discussed below, Petitioners have not been served with a Complaint in
`
`any action asserting the ‘506 Patent and thus 35 U.S.C. § 315 does not bar this
`
`Petition. Even if such a Complaint had been served, section 315(b) does not apply
`
`to the co-filed motion for joinder. See Activision Blizzard, Inc. v. Game and
`
`Technology Co., Ltd., IPR2018-00157, Paper 12 at 17-18 (May 3, 2018). “Because
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`§ 315(b) expressly states that ‘[t]he time limitation set forth in the preceding
`
`sentence shall not apply to a request for joinder under subsection (c),’ Petitioner’s
`
`request for joinder is not time-barred.” Id. at 18.
`
`The following are the primary modifications between the current Petition
`
`and the Petition filed in IPR2018-00102. First, the explanations of the real party in
`
`interest and the related ITC Investigation below have been adapted. Second,
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`2
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`Petition for Inter Partes Review of U.S. Pat. No. 7,633,506
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`Petitioners attach as Exhibit 1011 a public version of the Initial Determination in
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`the related ITC Investigation. Third, Petitioners note that they adopt and agree
`
`with the Board’s claim construction of “unified shader” in the Institution Decision
`
`in IPR2018-00102. See IPR2018-00102, Paper 14 at 10-25 (April 27, 2018
`
`Institution Decision). Fourth, for claim constructions other than “unified shader,”
`
`Petitioners note that those claim constructions as proposed in the petition in
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`IPR2018-00101 are correct under both a broadest reasonable interpretation and
`
`under the claim construction analysis under Phillips v. AWH Corp., 415 F.3d 1303
`
`(Fed. Cir. 2005).
`
`II.
`
`INTRODUCTION
`
`Petitioners MediaTek, Inc. and MediaTek USA, Inc. respectfully request
`
`inter partes review and seek cancellation of claims 1-9 of U.S. Patent No.
`
`7,633,506 (the “’506 Patent”) under 35 U.S.C. §§ 311-319 and 37 C.F.R. § 42.100
`
`et seq.
`
`The ’506 Patent claims a graphics processing system with a purported novel
`
`pipeline comprising various features that were well-known and commonplace at
`
`the time the patent was filed. Specifically, the alleged “novel” pipeline contains a
`
`setup unit, a scan converter coupled to a z-buffer, a rasterizer, a unified shading
`
`unit performing both texturing and color operations, and a color buffer. This
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`pipeline, however, was well-known at the time. Many of the then-existing graphics
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`Petition for Inter Partes Review of U.S. Pat. No. 7,633,506
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`processors contained identical components configured in nearly the exact same
`
`way. U.S. Patent No. 7,102,646 (Rubinstein), for example, has a priority date of
`
`November 10, 2000 and, as demonstrated below, discloses a pipeline nearly
`
`identical to the one disclosed in the ’506 Patent:
`
`
`
`The patent owner may seek to distinguish the ’506 patent from the
`
`Rubinstein system on the ground that the ’506 patent claims multiple parallel
`
`pipelines. Parallel pipelines, however, were also well-known and obvious at the
`
`time the ’506 patent was filed. At that time—and for more than a decade prior—it
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`Petition for Inter Partes Review of U.S. Pat. No. 7,633,506
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`was well known that parallel pipelines could effectively improve the efficiency of
`
`graphics processors, and they were incorporated in many different types of
`
`graphics systems. Indeed, by 2002, graphics processor manufacturers had already
`
`released multiple generations of graphics chips with parallel pipelines. See Ex.
`
`1003 (Pfister Decl.), ¶ 85, Ex. 1009, Ex. 1010 (discussing graphics chips with
`
`multiple parallel pipelines released in 2000 and 2001).
`
`Further, Rubinstein provides explicit teachings for a POSITA to incorporate
`
`parallel pipelines in Rubinstein’s system: the tiling feature of Rubinstein—which
`
`divides the screen into independent tiles that could easily be processed
`
`simultaneously—makes parallel processing an intuitive addition. Moreover,
`
`Collodi (discussed herein) discloses a shading unit that can be implemented within
`
`the pipeline of Rubinstein and expressly discloses that parallel processing has
`
`been, and could be, used to improve the efficiency of graphics chips like
`
`Rubinstein.
`
`Accordingly, the challenged claims amount to nothing more than putting
`
`multiple commonplace prior art graphics pipelines in one system. The prior art
`
`references discussed below establish that the challenged claims are unpatentable.
`
`III.
`
`37 C.F.R. § 42.8(B): MANDATORY NOTICES
`
`A.
`
`37 C.F.R. § 42.8(b)(1): Real Party In Interest
`
`Petitioners are the real parties in interest. Petitioners are not respondents in
`
`
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`5
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`Petition for Inter Partes Review of U.S. Pat. No. 7,633,506
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`the pending ITC investigation below. None of the co-respondents in the pending
`
`investigation identified below is a real party in interest to this proceeding. The co-
`
`respondents included: the Petitioners in IPR2018-00102 (MediaTek Inc and
`
`MediaTek USA Inc.), LG Electronics, Inc., LG Electronics, USA, Inc., and LG
`
`Electronics MobileComm USA, Inc., Sigma Designs, Inc., and VIZIO, Inc. None
`
`of these parties financed or controlled this Petition (or had the opportunity to
`
`exercise control over this Petition) or otherwise meet the requirements of 35 U.S.C.
`
`§ 312(a)(2).
`
`B.
`
`37 C.F.R. § 42.8(b)(2): Related Matters
`
`The ’506 Patent is the subject of the following actions brought by Patent
`
`Owner against other parties that may affect or be affected by a decision in this
`
`proceeding: U.S. International Trade Commission Inv. No. 337-TA-1044 and U.S.
`
`District Court for the District of Delaware Case No. 1:17-cv-00065. Other patents
`
`asserted in the related matters include U.S. Patent Nos. 7,796,133; 8,760,454; and
`
`9,582,846. A copy of the public version of the ALJ’s Initial Decision in 337-TA-
`
`1044 is attached hereto as Exhibit 1008.
`
`The ’506 Patent was also subject to a petition for inter partes review, Case
`
`No. IPR2017-01670, which was terminated on September 29, 2017.
`
` In IPR2018-00101, the Board instituted trial based upon Claims 1–9 as
`
`unpatentable under 35 U.S.C. § 103 on the grounds that claims 1–3, 5–9 are
`
`
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`Petition for Inter Partes Review of U.S. Pat. No. 7,633,506
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`
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`obvious under 35 U.S.C. § 103(a) over the combination of “Reality Engine
`
`Graphics” authored by K. Akeley (“Akeley”) and U.S. Patent No. 5,808,690
`
`(“Rich”) and that claim 4 is obvious under 35 U.S.C. § 103(a) over the
`
`combination of Akeley, Rich, and U.S. Patent No. 6,646,639 (“Greene”). See
`
`IPR2018-00101, Paper 13 (April 27, 2018). Petitioners are concurrently filing a
`
`separate petition for inter partes review and motion for joinder seeking to join
`
`IPR2018-00101 in which, just as in the present Petition, Petitioners adopt the same
`
`arguments and include the same expert declaration as was filed by the petitioners
`
`in IPR2018-00101.
`
`C.
`
`37 C.F.R. § 42.8(b)(3) and (4): Notice Of Counsel And Service
`Information
`
`Petitioners provide the following designation of counsel:
`
`Lead Counsel
`
`Backup Counsel
`
`Kevin Anderson, Reg. No. 43,471
`kanderson@wileyrein.com
`Wiley Rein LLP
`1776 K. Street, N.W.
`Washington DC 20006
`Phone (202) 719-7000
`Fax (202) 719-7049
`
`Scott Felder, Reg. No. 47,558
`sfelder@wileyrein.com
`Wiley Rein LLP
`1776 K. Street, N.W.
`Washington DC 20006
`Phone (202) 719-7000
`Fax (202) 719-7049
`
`Deposit Account No. 50-1129 with
`
`Deposit Account No. 50-1129 with
`
`reference to Attorney Docket No.
`
`reference to Attorney Docket No.
`
`82819.0056
`
`82819.0056
`
`
`
`7
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`Petition for Inter Partes Review of U.S. Pat. No. 7,633,506
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`
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`Petitioners submit Powers of Attorney with this Petition. Please address all
`
`correspondence to lead and backup counsel. Petitioners consent to service by email
`
`at: kanderson@wileyrein.com and sfelder@wileyrein.com.
`
`D.
`
`Fees Under 37 C.F.R. § 42.103
`
`Petitioner concurrently submits fees of $30,500. If more fees are necessary
`
`to accord this Petition a filing date, authorization is granted to charge the same to
`
`Deposit Account No. 50-1129 with reference to Attorney Docket No. 82819.0056.
`
`IV. REQUIREMENTS FOR INTER PARTES REVIEW
`
`As set forth below, this Petition meets and complies with all requirements
`
`under 37 C.F.R. § 42.104 for inter partes review.
`
`A.
`
`37 C.F.R. § 42.104(a): Ground For Standing
`
`Pursuant to 37 C.F.R. § 42.104(a), Petitioners certify that the ’506 Patent is
`
`available for inter partes review and Petitioners are not barred or estopped from
`
`requesting inter partes review challenging the claims of the ’506 Patent on the
`
`grounds identified herein.
`
`B.
`
`37 C.F.R. § 42.104(b): Identification Of Challenge
`
`Pursuant to 37 C.F.R. § 42.104(b), Petitioners request that the PTAB
`
`invalidate the challenged claims of the ’506 Patent.
`
`1.
`
`37 C.F.R. § 42.104(b)(1) Challenged Claims
`
`Petitioners challenge claims 1-9 of the ’506 Patent.
`
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`8
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`Petition for Inter Partes Review of U.S. Pat. No. 7,633,506
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`
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`2.
`
`37 C.F.R. § 42.104(b)(2): The Prior Art And Statutory
`Grounds.
`
`The one-year time bar under pre-AIA 35 U.S.C. §102(b) is measured from
`
`the effective U.S. filing date of the ’506 Patent, which is no earlier than November
`
`27, 2002. The prior art references relied upon herein are:
`
`Patent/Publication
`
`Priority Date Publication
`Date
`
`Prior
`Art
`
`Ex.
`No.
`
`U.S. Patent No. 7,102,646 to
`Rubinstein (“Rubinstein”)
`
`U.S. Patent Application,
`Publication No. US
`2003/0076320 (“Collodi”)
`
`U.S. Patent No. 6,809,732
`(“Zatz”)
`
`Nov. 10, 2000 Sep. 5, 2006
`
`102(e) 1004
`
`Oct. 18, 2001 Apr. 24, 2003 102(e) 1007
`
`Jul. 18, 2002 Oct. 26, 2004
`
`102(e) 1008
`
`Below are the specific statutory grounds under 35 U.S.C. §§ 102 and 103
`
`(pre-AIA) on which the claims are challenged:
`
`Ground 1: Claims 1-9 are rendered obvious under 35 U.S.C. §103(a) by
`
`Rubinstein in view of Collodi.
`
`Ground 2: Claims 8-9 are rendered obvious under 35 U.S.C. § 103(a) by
`
`Rubinstein in view of Collodi in further view of Zatz.
`
`3.
`
`Level of Ordinary Skill in the Art
`
`A person of ordinary skill in the field, at the time the ’506 patent was
`
`effectively filed, would have had at least a four-year degree in electrical
`
`
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`9
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`Petition for Inter Partes Review of U.S. Pat. No. 7,633,506
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`
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`engineering, computer engineering, computer science, or a related field and two
`
`years relevant experience in the graphics processing field including developing,
`
`designing or programming hardware for graphics processing units. Ex. 1003
`
`(Pfister Decl.), ¶ 46.
`
`4.
`
`37 C.F.R. § 42.104 (b)(3) Claim Construction
`
`Petitioners’ proposed constructions of certain terms in the challenged claims
`
`pursuant to this standard are provided in Section V.D below. Petitioners adopt the
`
`Board’s claim construction of “unified shader” in the Institution Decision of
`
`IPR2018-00102 and assert that well-reasoned construction is the proper claim
`
`construction analysis under Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir.
`
`2005).
`
`5.
`
`37 C.F.R. § 42.104(b)(4) How the Claims are Unpatentable.
`
`Sections IV.E and IV.F below explain how claims 1-9 of the ’506 Patent are
`
`unpatentable, including an identification of where each element of the claims is
`
`found in the prior art.
`
`6.
`
`Supporting Evidence
`
`Supporting evidence relied upon includes the declaration of Dr. Hanspeter
`
`Pfister, Ph.D. (Ex. 1003) and other supporting evidence in the Exhibit List filed
`
`herewith. Dr. Pfister’s background and qualifications, and the information
`
`provided to him, are discussed in Ex. 1003.
`
`
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`Petition for Inter Partes Review of U.S. Pat. No. 7,633,506
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`V.
`
`THERE EXISTS A REASONABLE LIKELIHOOD THAT THE
`CHALLENGED CLAIMS ARE UNPATENTABLE.
`
`A. Technology Background
`
`Graphics processing is an important part of any computer system, and has
`
`been for the past several decades. The purpose of a graphics processor is to
`
`generate complex shapes and structures to be displayed on a screen. Ex. 1003
`
`(Pfister Decl.), ¶ 29. In order to accomplish that purpose, a graphics processor
`
`converts a 3D object or scene (comprised of points in 3D space called “vertices”
`
`that make up shapes called “primitives”) into a 2D image to be displayed on a
`
`computer screen (comprised of “pixels”). Generally, 3D graphics processing starts
`
`with creating a mathematical model of each object. Id., ¶ 29. The model is then
`
`processed through a series of steps, referred to as a “graphics processing pipeline,”
`
`that render the scene as a 2D image on a display:
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`Petition for Inter Partes Review of U.S. Pat. No. 7,633,506
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`In most cases, 3D objects are conceptualized as a series of primitives
`
`(e.g., triangles) that cover the surface of an object, such as a teapot:
`
`
`
`Each point of the primitive is called a “vertex” and each vertex has certain
`
`properties, which are represented as data. Id., ¶ 31. For example, a vertex includes
`
`not just its location, but may also include other information, such as the color of
`
`the object and its material properties (e.g., whether it is reflective). A vertex
`
`processor performs the steps in the graphics pipeline that transform these vertices
`
`from 3D space into 2D space and determines how lighting and other conditions in
`
`the 3D scene impact the color of the vertices. Id., ¶ 31. The ’506 Patent refers to
`
`these operations on vertices as “front-end” operations.
`
`After the “front-end” processing, a number of steps occur to transform the
`
`2D shapes into a final image that can be displayed.
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`Petition for Inter Partes Review of U.S. Pat. No. 7,633,506
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`The ’506 Patent refers to this as “back-end” processing. The first step, called
`
`rasterization, determines what pixels on the 2D screen are covered by each
`
`primitive. At least one “fragment” is generated for each pixel on the screen (as a
`
`result, the terms “fragment” and “pixel” are sometimes used interchangeably). Id.,
`
`¶ 32. Rasterization commonly includes the step of “scan conversion,” which
`
`involves stepping through the geometry of the primitives to determine which pixels
`
`are covered. Id., ¶ 33. Subsequent operations including various forms of shading,
`
`texturing, blending, and other effects, each of which affects the final color of each
`
`pixel. These operations are commonly called “pixel shading” operations and may
`
`involve lighting, texture and bump mapping, translucency and other phenomena.
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`The results of each operation is gathered together through merging or blending of
`
`pixels for the final image to be displayed on a screen.
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`Petition for Inter Partes Review of U.S. Pat. No. 7,633,506
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`B.
`
`The Alleged Invention of the ’506 Patent.
`
`The ’506 Patent discloses and claims a graphics processing system that
`
`
`
`includes a front-end and a back-end. Ex. 1001 at Abstract and Claim 1. The front-
`
`end receives instructions (and graphics data) and outputs primitives or
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`combinations of primitives (e.g. triangles, parallelograms, etc.) (i.e., geometry). Id.
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`at Claim 1. The back-end receives the primitives and processes them into a final
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`image comprised of colored pixels. Id. For various embodiments, the claimed
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`invention also includes one or more of the following features:
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`Back-end with Parallel Pipelines: The ’506 Patent discloses and claims a
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`system with a back-end comprised of multiple parallel pipelines. Id. These parallel
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`pipelines each process a different portion of the screen in parallel. Id.
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`Ex. 1001 (’506 Patent) at Figure 3.
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`Unified Shader: To help process the primitives, each pipeline contains a
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`“unified shader.” Id. at Claim 1. The ’506 Patent defines “unified shader” to mean
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`a shading unit that performs both pixel color shading and texture address shading.1
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`Id. at 6:49-53. The shader is capable of, for example, performing
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`calculations related to determining and applying a color to a fragment or pixel
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`1 This is contrary to the current understanding of the term “unified shader” in the
`industry today. Pursuant to developments outside of the ’506 Patent, the term
`“unified shader” has come to commonly mean a unit that performs computations
`on both vertex (geometry) data and pixel data. Ex. 1003 (Pfister Decl.), ¶ 38. Or, as
`the ’506 Patent would put it, a shader that performs computations on both “front-
`end” and “back-end” data. Id. The ’506 Patent, however, clearly does not use the
`term in this way, and, instead, gives the term a definition unique to the patent. Id.
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`(color shading), and it is also capable of calculations related to determining texture
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`coordinates for a texture look-up (texture address shading). Id.
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`Ex. 1001 (’506 Patent) at Figure 5 (showing various components within each of the
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`parallel pipelines of the ’506 graphics processing system, with the Unified Shader
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`annotated).
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`Tiling and Set-up Unit: Each pipeline in the ’506 Patent’s system processes
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`specific portion(s) or “tile(s)” of the screen. Id. at Claims 1 and 6. To facilitate this
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`process, the system includes a “set-up unit” that receives primitives/geometry from
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`the front-end, determines which portion or “tile” of the screen the geometry is
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`located in, and then directs the geometry to be processed by one of the multiple
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`pipelines. Id. at claim 6.
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`Ex. 1001 (’506 Patent) at Figure 5 (with Setup Unit annotated).
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`Z-buffering: In certain embodiments, each pipeline also includes a “z-buffer
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`logic unit” that scans the incoming primitives and determines which primitives will
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`be visible to the screen. Id. at Claims 3-5. The z-buffer logic unit may perform
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`“early z” operations through an early z-interface, i.e., visibility testing prior to
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`pixel shading. See e.g., claim 4. In other embodiments, it may perform “late z”
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`operations, i.e., visibility testing after pixel shading. Id. at Claim 5. The z-buffer
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`may also perform hierarchical z-buffering, which involves visibility testing at a
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`coarse level, i.e. coarser than fragment-by-fragment or pixel-by-pixel. Id. at 6:1-
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`15.
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`Ex. 1001 (’506 Patent) at Figure 5 (with Z buffer logic unit annotated).
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`C.
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`Prosecution History of the ’506 Patent
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`The ’506 Patent’s application was filed on November 26, 2003. The
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`application included 16 claims directed to “graphics chip[s]” comprising, among
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`other things, the elements listed in the previous section. Ex. 1002 (’506
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`Prosecution History). After several office actions, the Examiner allowed some of
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`the amended claims. Ex. 1002 at 39.
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`In allowing the claims of the ’506 Patent, the examiner recognized that
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`several prior art references (including Zhu ’063, discussed below) taught rendering
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`pipeline systems that used screen space tiling and double z-buffering schemes
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`claimed by the ’506 patent. Ex. 1002 at 36-41, 7/30/2009 Notice of Allowance.
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`The examiner stated, however, that the references he reviewed did not
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`disclose parallel pipelines with unified shaders as claimed by the ’506 Patent. Id.
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`Nonetheless, as explained below, using parallel pipelines and “unified
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`shaders” (as defined by the ’506 Patent) was well-known and obvious at the time
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`the ’506 Patent was filed. Ex. 1003 (Pfister Decl.), ¶ 45.
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`D.
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`Proposed Claim Construction
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`Petitioners propose construction of certain claim terms below pursuant to the
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`Phillips standard.2 The proposed claim constructions are offered to comply with
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`37 C.F.R. §§ 42.100(b) and 42.104(b)(3) and for the sole purpose of this Petition.
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`.
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`2 The Petitioners in IPR2018-00101 proposed these constructions under a
`“Broadest Reasonable Interpretation” standard. To maintain the consistency and
`identity with the petition in IPR2018-00101, this present Petition retains the
`language reciting “Broadest Reasonable Interpretation” for these constructions.
`However, the present Petitioners assert that these constructions are proper under
`both “Broadest Reasonable Interpretation” and the Phillips standard.
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`1.
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`Z-Buffer Logic Unit
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`Claims 3-5 require a “Z Buffer Logic Unit.” The Broadest Reasonable
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`Interpretation of a “Z-Buffer Logic Unit” is “a logic unit that facilitates visibility
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`testing by comparing depth values.” Ex. 1003 (Pfister Decl.), ¶¶ 47-48.
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`As the ’506 Patent explains, a “z-buffer” is a memory space that the z-buffer
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`logic unit uses to store the “z” or “depth” values (i.e., the distance from the screen)
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`for primitives or portions of primitives. See, e.g., Ex. 1001 (’506 Patent) at 6:20-
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`26; 6:64-7:3. The logic unit then compares those values to other primitives that
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`may occupy the same screen space. Id. at 6:20-23 (“For each quad, coverage and Z
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`(depth) information is computed…. [E]ach quad is passed to the Z buffer 555
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`where its Z values are compared against the values stored in the Z buffer at that
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`location.”) If the comparison reveals that the particular primitive or portion of the
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`primitive is behind another primitive (i.e. not visible to the screen) the Z-buffer
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`logic unit discards that primitive. Id. at 6:28-30 (“At this stage, those quads for
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`which none of the covered pixels passed the Z compare test are discarded.”)
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`Accordingly, the broadest reasonable interpretation of a Z-buffer Logic Unit
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`is “a logic unit that facilitates this visibility testing by comparing pertinent values.”
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`2.
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`“Hierarchical Z-Interface”
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`Claim 4 requires a “Hierarchical Z-Interface.” The broadest reasonable
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`interpretation of this term is “an interface with a z-buffer logic unit that provides
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`for visibility testing at a coarse level, including, for example, for an entire tile or
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`primitive.” Ex. 1003 (Pfister Decl.), ¶¶ 49-50.
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`The ’506 Patent discloses that a hierarchical Z-interface is one that steps
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`through the geometry at a coarse level (e.g., across an entire tile) to determine if
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`the entire geometry or portion of that geometry can be discarded:
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`A scan converter 540 works in conjunction with Hierarchical Z-
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`interface of Z buffer logic 555 to step through the geometry (e.g.,
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`triangle or parallelogram) within the bounds of the pipeline’s tile
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`pattern. In one embodiment, initial stepping is performed at a coarse
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`level. For each of the coarse level tiles, a minimum (i.e. closest) Z value
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`is computed. This is compared with the farthest Z value for the tile
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`stored in a hierarchical-Z buffer 550. If the compare fails, the tile is
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`rejected.
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`Ex. 1001 (’506 Patent) at 6:2-10 (emphasis added). The coarse level z-buffering
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`done by the hierarchical z-interface is in contrast to the finer pixel or fragment
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`level z-buffering done later. Id. at 6:16-18 (“The second section of the scan
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`converter 540 works in conjunction with the Early Z-interface… to step through
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`the coarse tile at a fine level.”) Accordingly, a POSITA would understand the
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`broadest reasonable interpretation of “Hierarchical Z-Interface” to be “an interface
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`with a z-buffer logic unit that provides for visibility testing at a coarse level,
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`including, for example, for an entire tile or primitive.”
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`3.
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`“Early Z-interface” and “Late Z-interface”
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`Claim 4 requires an “Early Z-interface.” The broadest reasonable
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`interpretation of this term is “an interface with a z buffer logic unit that provides
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`for visibility testing prior to shading and texturing.” Ex. 1003 (Pfister Decl.), ¶¶
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`53-55.
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`The ’506 Patent discloses that the early Z-