UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`ARM Ltd. and ARM, Inc.,
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`Petitioners
`
`v.
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`Advanced Micro Devices, Inc. and ATI Technologies ULC,
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`Patent Owner
`
`U.S. Patent 7,633,506 Issue Date: December 15, 2009
`Title: Parallel Pipeline Graphics System
`
`CASE: IPR2018-01149
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`DECLARATION OF DR. HANSPETER PFISTER, Ph.D.
`
`IN SUPPORT OF PETITION FOR INTER PARTES REVIEW
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`ARM, Ex. 1003, Page 1
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`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`ARM Ltd. and ARM, Inc.,
`
`Petitioners
`
`v.
`
`Advanced Micro Devices, Inc. and ATI Technologies ULC,
`
`Patent Owner
`
`U.S. Patent 7,633,506 Issue Date: December 15, 2009
`Title: Parallel Pipeline Graphics System
`
`CASE: IPR2018-01149
`
`DECLARATION OF DR. HANSPETER PFISTER, Ph.D.
`
`IN SUPPORT OF PETITION FOR INTER PARTES REVIEW
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`ARM, Ex. 1003, Page 1
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`
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`I, Dr. Hanspeter Pfister, Ph.D., declare as follows:
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`1.
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`I have been retained by counsel for Petitioners, ARM Ltd. and ARM, Inc.,
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`as an expert in this inter partes review to examine whether claims 1-9 of U.S. Patent No.
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`7,633,506 are patentable over certain prior art. With the exception of the identification
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`of the party retaining my services, this declaration is identical to my declaration that was
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`filed in IPR2018-00102.
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`2.
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`I have personal knowledge of all the facts set forth herein, and if called to
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`testify at any hearing in this inter partes review, I would competently testify and verify
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`that testimony contained herein.
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`3.
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`I am being compensated at my hourly rate of $600 per hour. I am also being
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`reimbursed for out-of-pocket expenses. My compensation does not depend in any way
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`on the outcome of this proceeding or the particular opinions I express, or the testimony I
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`give.
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`4.
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`I expect to be available for deposition and to testify at the evidentiary
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`hearing in this inter partes review to the extent required.
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`5.
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`This declaration contains my conclusions and a summary of my analysis
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`including a summary of my conclusions; an overview of my qualifications as an expert;
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`an overview of the scope and terms of my engagement for this declaration; an overview
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`of the materials I have considered in arriving at my conclusions; an overview of the
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`terminology and legal principles that I applied in my analysis; an overview of the
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`ARM, Ex. 1003, Page 2
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`technical background of the subject matter; an overview of the Patent in Suit; an analysis
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`of the level of ordinary skill in the art related to the Patent in Suit; an analysis of the
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`asserted references; and a patentability analysis of the challenged claims.
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`6.
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`This declaration is based on information currently available to me. I intend
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`to continue my investigation and study, which may include a review of documents and
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`information that may yet be produced, as well as deposition testimony from depositions
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`for which transcripts are not yet available or that may yet be taken in this review.
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`Therefore, I expressly reserve the right to expand or modify my opinions as my
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`investigation and study continue, and to supplement my opinions in response to any
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`additional information that becomes available to me, any matters raised by Patent Owner
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`and/or other opinions provided by Patent Owner’s expert(s), or in light of any relevant
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`orders from the Patent Trial and Appeal Board or other authoritative body.
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`I.
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`SUMMARY OF OPINION
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`7.
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`It is my opinion that claims 1-9 of the ’506 Patent are rendered obvious by
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`the prior art references discussed below. I will explain below my analysis and basis for
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`my opinion in detail.
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`II. EXPERT QUALIFICATIONS AND PRIOR TESTIMONY
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`8. My curriculum vitae is attached hereto as Attachment A, which provides an
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`accurate identification of my relevant background and experience in multithreaded
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`graphics processors. For the past 25 years, I have focused on computer graphics
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`ARM, Ex. 1003, Page 3
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`processing in both industrial and academic settings. I have designed cutting-edge
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`graphics processing systems, including the world’s first real- time volume rendering
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`graphics card. I have pioneered research into various aspects of computer graphics and
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`received academic awards and industry recognition for my work in computer graphics.
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`9.
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`In 1991, I received my M.Sc. in Electrical Engineering from the Swiss
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`Federal Institute of Technology (ETH) Zurich, Switzerland. I then proceeded to study
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`computer science at the State University of New York at Stony Brook, Stony Brook,
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`NY, where I earned my M.S. in Computer Science in 1994 and my Ph. D. in Computer
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`Science in 1996.
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`10.
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`I am the An Wang Professor of Computer Science at the Harvard John A.
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`Paulson School of Engineering and Applied Sciences and an affiliate faculty member of
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`the Center for Brain Science. My research in visual computing lies at the intersection of
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`visualization, computer graphics, and computer vision. It spans a wide range of topics,
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`including bio-medical visualization, image and video analysis, 3D fabrication, and data
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`science. From 2013 to 2017 I was director of the Institute for Applied Computational
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`Science. For most of this work we are leveraging the power of graphics processing units
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`(“GPUs”) for computer graphics, high-throughput computing, and visualization. I am
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`currently advising and co- advising seven Ph. D. students, six post-doctoral fellows, and
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`one research scientist. I also supervised numerous research and thesis projects and
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`student interns.
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`ARM, Ex. 1003, Page 4
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`11. Before joining Harvard, I worked for over a decade at Mitsubishi Electric
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`Research Laboratories where I was Associate Director and Senior Research Scientist. I
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`was the chief architect of Mitsubishi Electric's VolumePro, the world’s first PC graphics
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`card for real-time visualization of volume data. The technology was subsequently
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`acquired by TeraRecon and is still in wide commercial use in medicine, biology,
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`engineering, and oil and gas exploration. VolumePro received several technical awards,
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`including Mitsubishi Electric President's Award in 2000. Since then I have developed
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`several new methods for high-quality and interactive volume visualization on GPUs. I
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`am the recipient of the 2010 IEEE Visualization Technical Achievement award in
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`recognition of my “seminal technical achievements in real-time volume rendering.”
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`12.
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`I am a pioneer in point-based computer graphics, a subfield of computer
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`graphics that deals with modeling and rendering of point-sampled (e.g., laser-scanned)
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`objects. I am among the first to introduce data-driven approaches for complex real-world
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`objects to computer graphics, including human faces. And I developed new camera and
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`display technologies, including the world’s first end- to-end real-time 3D TV system
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`with auto-stereoscopic display. Currently, I am collaborating with Harvard scientists on
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`novel analysis and visualization approaches in computational science, including
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`neuroscience, genomics, systems biology, astronomy, and medicine. I am co-inventor of
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`over 50 US patents and co- author on more than 160 peer-reviewed publications,
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`including over 25 ACM SIGGRAPH papers, the premier forum in Computer Graphics.
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`ARM, Ex. 1003, Page 5
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`6
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`ARM, Ex. 1003, Page 6
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`ARM, Ex. 1003, Page 6
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`13.
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`From 1999 to 2007, I built a rich academic program in computer graphics at
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`the Harvard Extension School through the development of several new courses,
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`including CSCI E-234 “Introduction to Computer Graphics” (1999-2007), CSCI E-235
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`“Advanced Computer Graphics” (2002), CSCI E-236 “Advanced Topics in Computer
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`Graphics” (2004-2006), and INDR E-399 “Independent Study in Advanced Computer
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`Graphics” (2003). After joining Harvard in 2007, I introduced several new
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`undergraduate and graduate courses that are also offered to the general public through
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`the Harvard Extension School, including CS171 “Visualization” (2007-present), CS175
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`“Introduction to Computer Graphics” (2010), CS264 “Massively Parallel Computing”
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`(2009-2011), CS205 “Introduction to Computational Science” (2010-2012), and CS109
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`“Data Science” (2013- present).
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`14. Between 2009 and 2016 in collaboration with Prof. Alan Aspuru- Guzik of
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`the Chemistry and Chemical Biology faculty at Harvard, I was the co-PI (Principal
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`Investigator) of Harvard's CUDA Center of Excellence (CCOE). The CCOE supported
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`“outstanding research taking place in Massively Parallel Programming and Computing”
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`using GPUs.
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`15.
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`I have served on the papers committees of all major visualization and
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`graphics conferences, including ACM SIGGRAPH, IEEE Visualization, EuroVis,
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`Eurographics, Pacific Graphics, and many others. I have been the co-organizer of
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`various international workshops, symposia, and conferences in computer graphics and
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`ARM, Ex. 1003, Page 7
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`visualization, including general conference chair of IEEE Visualization 2002 and
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`technical papers chair of ACM SIGGRAPH 2012. I previously chaired and am currently
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`a director of the IEEE Visualization and Graphics Technical Committee. I served on the
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`editorial board of the IEEE Transactions on Visualization and Computer Graphics and
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`the ACM Transaction on Graphics, the top two journals in the field. I am co-editor of the
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`first textbook on Point-Based Computer Graphics, published by Elsevier in 2007, and of
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`the 2006 NIH/NSF Visualization Research Challenges Report. I am a senior member of
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`the IEEE Computer Society, and a member of ACM, ACM SIGGRAPH, and the
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`Eurographics Association. I received the IEEE Golden Core Award, the IEEE
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`Meritorious Service Award, and the Petra T. Shattuck Excellence in Teaching Award.
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`16.
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`I have been working as an independent consultant since 2007, specializing
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`in computer graphics, visualization, data science, technical due diligence reviews, and in
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`the provision of expert witness services, particularly patent infringement. My clients
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`range from domestic start-ups to international Fortune 500 companies, and include
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`Adobe, Disney Research, Novartis, as well as NVIDIA.
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`I. MATERIALS REVIEWED
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`17.
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`I have reviewed the following materials in forming my opinions:
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`•
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`•
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`•
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` U.S. Patent No. 7,633,506 (the “’506 Patent”)
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`File History of U.S. Patent No. 7,633,506. (“File History”)
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`“Reality Engine Graphics” by Kurt Akeley (“Akeley”)
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`ARM, Ex. 1003, Page 8
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`•
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`•
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`•
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`•
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`•
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`•
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`•
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`•
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`U.S. Patent No. 5,808,690 (“Rich”)
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`U.S. Patent No. 7,102,646 (“Rubinstein”)
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` U.S. Patent No. 6,697,063 (“Zhu ’063”)
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` U.S. Patent No. 6,856,320 (“Zhu ’320)
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`U.S. Patent Application Publication No. US 2003/0076320A1
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`(“Collodi”)
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`U.S. Patent No. 6,646,639 (“Greene”)
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` U.S. Patent No. 6,809,732 (“Zatz”)
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`April 26, 200 Press release describing Nvidia GeForce 2 Graphics
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`Chip
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`•
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`January 5, 2001 Article describing Nvidia GeForce 3 Graphics Chip
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`ARM, Ex. 1003, Page 9
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`18.
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`I have tried my best to list all the materials I considered and reviewed. I
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`may have accidentally left some materials off the above list that I cited in my analysis
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`below. Such materials, if any, should be included in the above list of materials I
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`considered and reviewed. I reserve the right to revise this list.
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`II. UNDERSTANDING OF THE LAW
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`19.
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`I am not a legal expert. In forming my opinions, I have been informed of and
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`applied the legal standards as follows. I understand that the legal standards relating to
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`anticipation and obviousness apply to the ‘506 Patent based on its effective filing date of
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`November 27, 2002.
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`20.
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`I understand that, during an inter partes review proceeding, patent claims are
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`given their “broadest reasonable interpretation in light of the specification of the patent.” It
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`is my further understanding that the prosecution history is relevant to determining the
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`correct construction of claim terms and that extrinsic evidence also may be relevant to
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`establish the meaning of terms to the extent it is consistent with the specification and
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`prosecution history.
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`21.
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`I understand that anticipation of a claim requires that each and every
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`limitation recited in a claim must be disclosed either expressly or inherently in a single
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`prior art reference. I further understand that, to be considered anticipatory, a written prior
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`art reference must be enabling and describe the applicant’s claimed invention sufficiently to
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`have placed it in possession of a person of ordinary skill in the field of the invention. Thus,
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`ARM, Ex. 1003, Page 10
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`I further understand that the disclosure of prior art is considered from the perspective of
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`one of ordinary skill in the art.
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`22.
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`I understand that a patent claim is “obvious” and therefore invalid when the
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`differences between the claimed subject matter and the prior art are such that the subject
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`matter as a whole would have been obvious at the time the invention was made to a
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`person having ordinary skill in the art to which the subject matter pertains.
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`ARM, Ex. 1003, Page 11
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`23.
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`In making an obviousness determination, I understand that there are several
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`factors to consider: (1) the scope and content of the prior art; (2) the level of ordinary
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`skill in the art at the time the invention was made; (3) the differences between the
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`claimed invention and the prior art, if any, and (4) objective considerations, if any exist,
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`such as any commercial success, copying, prior failure by others, licenses, longstanding
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`need, and unexpected results.
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`24.
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`I understand that prior art used to show that a claimed invention is obvious
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`must be “analogous art.” Prior art is analogous art to the claimed invention if (1) it is
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`from the same field of endeavor as the claimed invention (even if it addresses a different
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`problem) or (2) the reference is reasonably pertinent to the problem faced by the inventor
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`(even if it is not from the same field of endeavor as the claimed invention).
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`25.
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`I understand that it is improper to engage in hindsight when trying to
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`determine the obviousness of a patent claim. I understand that the obviousness inquiry
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`must be conducted from the standpoint of a person of ordinary skill in the field at the
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`time the claimed invention was made. What is known today, and what is learned from
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`the teachings and disclosures of the patent itself containing the claim under analysis,
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`should not be considered.
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`26.
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`I have been informed that various “secondary considerations” (sometimes
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`referred to as objective indicia of non-obviousness) may support a determination of non-
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`obviousness and that such secondary considerations must be considered as part of an
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`ARM, Ex. 1003, Page 12
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`obviousness analysis. I have been informed that secondary considerations of
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`nonobviousness may include:
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`•
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`•
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`•
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`commercial success of a product due to the merits of the claimed
`invention;
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`a long felt need for the solution provided by the claimed invention;
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`unsuccessful attempts by others to find the solution provided by the
`claimed invention;
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`copying of the claimed invention by others;
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`unexpected and superior results from the claimed invention; and
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`acceptance by others of the claimed invention as shown by praise from
`others in the field or from the licensing of the claimed invention.
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`27.
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`I understand that in order for such “secondary considerations” evidence to
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`be relevant to the obviousness inquiry, there must be a relationship or “nexus” between
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`the advantages and features of the claimed invention and the evidence of secondary
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`considerations.
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`28.
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`I understand that if a claim element is not obvious, then the claims that
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`depend from it are not obvious.
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`III. TECHNOLOGY BACKGROUND
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`29. Graphics processing is an important part of any computer system, and has
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`been for the past several decades. The purpose of a graphics processor is to generate
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`complex shapes and structures to be displayed on a screen. In order to accomplish that
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`purpose, a graphics processor converts a 3D object or scene (comprised of points in 3D
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`ARM, Ex. 1003, Page 13
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`space called “vertices” that make up shapes called “primitives”) into a 2D image to be
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`displayed on a computer screen (comprised of “pixels”). Generally, 3D graphics
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`processing starts with creating a mathematical model of each object. The model is then
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`processed through a series of steps, referred to as a “graphics processing pipeline,” that
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`render the scene as a 2D image on a display:
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`ARM, Ex. 1003, Page 14
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`30.
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`In most cases, 3D objects are conceptualized as a series of primitives (e.g.,
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`triangles) that cover the surface of an object, such as a teapot:
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`31.
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`Each point of the primitive is called a “vertex” and each vertex has certain
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`properties, which are represented as data. For example, a vertex includes not just its
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`location, but may also include other information, such as the color of the object and its
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`material properties (e.g., whether it is reflective). A vertex processor performs the steps
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`in the graphics pipeline that transform these vertices from 3D space into 2D space and
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`determines how lighting and other conditions in the 3D scene impact the color of the
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`ARM, Ex. 1003, Page 15
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`vertices. The ’506 Patent refers to these operations on vertices as “front-end” operations.
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`32. After the “front-end” processing, a step called rasterization determines what
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`pixels on the 2D screen are covered by each primitive. At least one “fragment” is
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`generated for each pixel on the screen (as a result, the terms “fragment” and “pixel” are
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`sometimes used interchangeably).
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`33. Rasterization commonly includes the step of “scan conversion,” which
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`involves stepping through the geometry of the primitives to determine which pixels are
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`covered.
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`34. A pixel processor then performs additional operations on the fragments or
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`pixel data, which includes determining the color of each pixel. These operations are
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`commonly called “pixel shading” operations and may involve lighting, texture and bump
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`mapping, translucency and other phenomena. All of this information is gathered
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`together through merging or blending of pixels for the final image to be displayed on a
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`screen.
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`ARM, Ex. 1003, Page 16
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`IV. THE ’506 PATENT
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`35.
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`The ’506 Patent discloses and claims a graphics processing system that
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`includes a front-end and back-end. Ex. 1001 at Abstract and Claim 1. The front-end
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`receives instructions and outputs primitives or combinations of primitives (e.g. triangles,
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`parallelograms, etc.) (i.e., geometry). Id. at Claim 1. The back-end receives the
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`primitives and processes them into a final image comprised of colored pixels. Id. For
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`various embodiments, the claimed invention also includes one or more of the following
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`features:
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`36. Back-end with Parallel Pipelines: The ’506 Patent discloses and claims a
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`system with a back-end comprised of multiple parallel pipelines. Id. These parallel
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`pipelines each process a different portion of the screen in parallel. Id.
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`ARM, Ex. 1003, Page 17
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`Ex. 1001 (’506 Patent) at Figure 3 (parallel pipelines annotated).
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`ARM, Ex. 1003, Page 18
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`Ex. 1001 (’506 Patent) at Figure 5 (parallel pipelines annotated).
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`37. Unified Shader: To help process the primitives, each pipeline contains a
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`“unified shader.” Id. at Claim 1. The ’506 Patent defines “unified shader” to mean a
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`shading unit that performs both pixel color shading and texture address shading. A
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`passage describing the unified shader of the ’506 Patent is provided below:
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`ARM, Ex. 1003, Page 19
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`ARM, EX. 1003, Page 20
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`A unified shader reads in rasterized texture addresses and colors, and
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`applies a programmed sequence of instructions. A unified shader is so
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`named because the functions of a traditional color shader and a
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`traditional texture address shader are combined into a single unified
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`shader. The unified shader performs both color shading and texture
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`address shading. The conventional distinction between shading
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`operations (i.e., color texture map and coordinate texture map or color
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`shading operation and texture address operation) is not handled by the
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`use of separate shaders. In this way, any operation, be it for color
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`shading or texture shading, may loop back into the shader and be
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`combined with any other operation.
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`Ex. 1001 (’506 Patent) at 6:49-52 (emphasis added).
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`38.
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`To be clear, the ’506 Patent does not use the term “unified shader” in the
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`way it is commonly used in the industry today. Today, a person of ordinary skill would
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`understand the term “unified shader” to mean a unit that performs computations on both
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`vertex (geometry) data and pixel data. Or, as the ’506 Patent would put it, a shader that
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`performs computations on both “front-end” and “back- end” data. The ’506 Patent,
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`however, clearly does not use the term in this way, and, instead, gives the term a
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`definition unique to the patent. Id. I apply the ’506 Patent’s definition of “unified
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`shader” for purposes of the opinions in this declaration.
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`39.
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`Figure 5 of the ’506 Patent, identifying the unified shader in green is
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`provided below:
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`ARM, Ex. 1003, Page 21
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`Ex. 1001 (’506 Patent) at Figure 5 (annotating Unified Shader)
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`40.
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`Tiling and Setup Unit: The system disclosed and claimed by the ’506 Patent
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`also includes a Setup Unit that assists with “Tiling.” Tiling is the process of breaking
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`ARM, Ex. 1003, Page 22
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`the screen into “tiles” and processing each tile separately. Tiling is a well-known
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`practice in the industry and was well-known at the time the ’506 Patent was filed. It was
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`often combined with parallel processing in order to processes multiple pieces of a final
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`image at the same time in order to increase efficiency. To assist in such a process, the
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`’506 Patent discloses a “Setup Unit” that receives primitives/geometry from the front-
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`end, determines which portion or “tile” of the screen the geometry is located in, and then
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`directs the geometry to be processed by the pipeline responsible for that tile. Ex. 1001
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`(’506 Patent) at claim Figure 5 from the ’506 Patent id reproduced below, identifying the
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`Setup Unit in green:
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`ARM, Ex. 1003, Page 23
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`Ex. 1001 (’506 Patent) at Figure 5 (annotating Setup Unit)
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`41.
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`Z-buffering: The ’506 Patent discloses that certain embodiments use z-
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`buffering. Z-buffering is the process of comparing the depth values or “z values” of
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`various objects—measured from the screen—to determine which objects are visible and
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`which objects are not visible (because they appear behind other objects from the point of
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`view of the screen). Z-buffering was a common feature for graphics processors at the
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`time the ’506 Patent was filed. In order to facilitate z-buffering, the ’506 Patent
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`ARM, Ex. 1003, Page 24
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`discloses that the system contains a “z-buffer logic unit,” which a person of ordinary
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`skill in the art would understand go be a logic unit that performs z-buffering.
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`ARM, Ex. 1003, Page 25
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`42.
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`The ’506 Patent discloses that the system may perform three different types
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`of z-buffering: hierarchical z-buffering, early z-buffering, and late z- buffering. Id. at
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`Claims 3-5. As explained in more detail in the context of claim construction, hierarchical
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`z-buffering involves visibility testing at a coarse level, i.e., coarser than fragment-by-
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`fragment or pixel-by-pixel, early z-buffering is z- buffering that occurs before pixel
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`shading, and late z-buffering is z-buffering that occurs after pixel shading. Hierarchical
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`z-buffering is z-buffering that occurs at a coarse level (e.g., an entire tile) as opposed to
`
`the finer fragment-by-fragment level. The various types of z-buffering are identified in
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`Figure 5 from the ’506 Patent:
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`
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`
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`26
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`ARM, Ex. 1003, Page 26
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`
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`Ex. 1001 (’506 Patent) at Figure 5 (annotating z-interfaces)
`
`A.
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`Prosecution History of the ’506 Patent
`
`43.
`
`The ’506 Patent’s application was filed on November 26, 2003. The
`
`application included 16 claims directed to “graphics chip[s]” comprising, among other
`
`things, the elements listed in the previous section. Ex. 1002 (’506 Prosecution History).
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`
`
`27
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`ARM, Ex. 1003, Page 27
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`
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`
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`After several office actions, the Examiner allowed several of claims applicant had
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`amended. Ex. 1002 at 39.
`
`44.
`
`In allowing the claims of the ’506 Patent, the examiner recognized that
`
`several prior art references (including Zhu ’063) taught rendering pipeline systems that
`
`used screen space tiling and double z-buffering schemes that use scan/z engines as
`
`claimed by the ’506 patent. Ex. 1002 at 7/30/2009 Notice of Allowance. The examiner
`
`stated, however, that the reviewed references did not disclose parallel pipelines with
`
`unified shaders as claimed by the ’506 Patent.
`
`45. As explained below, using parallel pipelines and “unified shaders” (as
`
`defined by the ’506 Patent) to perform pixel calculations was well-known and obvious at
`
`the time the ’506 Patent was filed.
`
`V. LEVEL OF ORDINARY SKILL IN THE ART
`
`46. A person of ordinary skill in the field, at the time the ’506 patent was
`
`effectively filed, would have had at least a four-year degree in electrical engineering,
`
`computer engineering, computer science, or a related field and two years relevant
`
`experience in the graphics processing field including developing, designing or
`
`programming hardware for graphics processing units.
`
`VI. PROPOSED CLAIM CONSTRUCTION
`
`A.
`
`Z-Buffer Logic Unit
`
`47. Claims 3-5 require a “Z Buffer Logic Unit.” A person of ordinary skill in
`
`
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`28
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`ARM, Ex. 1003, Page 28
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`
`
`
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`the art would understand that the broadest reasonable interpretation of a “Z-Buffer Logic
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`Unit” is “a logic unit that facilitates visibility testing by comparing depth values.”
`
`48.
`
`Z-buffering was well-known and common-place in the art by the time the
`
`’506 Patent was filed. A person of ordinary skill in the art would understand that a “z-
`
`buffer” is memory used to store the “z” or “depth” information. They would further
`
`understand that a z-buffer logic unit is the logic that uses that “z” or “depth” information
`
`to perform visibility testing. This is consistent with the disclosure of the ’506 Patent,
`
`which states that “Z (depth) information is computed” and “passed to the Z buffer” such
`
`that the “Z values are compared against the values stored in the Z buffer at that
`
`location.” Ex. 1001 (’506 Patent) at 6:20-23. In other words, a person of ordinary skill in
`
`the art would understand that a z-buffer logic unit is a logic unit that facilitates z-
`
`buffering, i.e., visibility testing done by comparing depth values.
`
`B.
`
`“Hierarchical Z-Interface”
`
`49. Claim 4 requires a “Hierarchical Z-Interface.” A person of ordinary skill in
`
`the art would understand that the broadest reasonable interpretation of a “hierarchical z-
`
`interface” to mean “an interface with a z-buffer logic unit that provides for visibility
`
`testing at a coarse level, including, for example, for an entire tile or primitive.”
`
`50. Hierarchical z-buffering was well-known and common-place by the time
`
`the ’506 Patent was filed. A person of ordinary skill in the art would have understood
`
`that hierarchical z-buffering involves visibility testing at a coarse level, i.e., coarser than
`
`
`
`29
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`ARM, Ex. 1003, Page 29
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`
`
`
`
`fragment-by-fragment / pixel-by-pixel. The ’506 Patent itself discloses that a
`
`hierarchical Z-interface is one that steps through geometry at a coarse level, including,
`
`for example, the entire portion of a geometry that contributes to a tile. Ex. 1001 (’506
`
`Patent) at 2:67-3:1 (“In one embodiment, each parallel pipeline comprises … a
`
`‘hierarchical-Z’ component to more precisely define the borders of the geometry.”). For
`
`example, the hierarchical z-buffer may compare the smallest z-value of such a geometry
`
`(i.e., the closes point to the screen) with the largest z-value of the current tile (i.e., the
`
`furthest point away). If the object being tested is further away (i.e., behind) the rest of
`
`the objects currently being displayed in that tile, it can be discarded in total:
`
`A scan converter 540 works in conjunction with Hierarchical Z-
`
`interface of Z buffer logic 555 to step through the geometry (e.g.,
`
`triangle or parallelogram) within the bounds of the pipeline’s tile
`
`pattern. In one embodiment, initial stepping is performed at a coarse
`
`level. For each of the coarse level tiles, a minimum (i.e. closest) Z value
`
`is computed. This is compared with the farthest Z value for the tile
`
`stored in a hierarchical-Z buffer 550. If the compare fails, the tile is
`
`rejected.
`
`Ex. 1001 (’506 Patent) at 6:2-10 (emphasis added).
`
`51.
`
`The coarse level z-buffering done by the hierarchical z-interface is in
`
`contrast to the finer pixel or fragment level z-buffering done later. Id. at 6:16-18 (“The
`
`second section of the scan converter 540 works in conjunction with the Early Z-
`
`interface… to step through the coarse tile at a fine level.”)
`
`
`
`30
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`ARM, Ex. 1003, Page 30
`
`
`
`
`
`C.
`
`“Early Z-interface” and “Late Z-interface”
`
`52.
`
`The ’506 Patent also discloses and claims and “early z-interface” and a
`
`“late z-interface.” These interfaces coincide with the concepts of “early z- buffering” and
`
`“late z-buffering,” which were both well-known and commonplace prior to the filing of
`
`the ’506 Patent.
`
`53.
`
`Early z-buffering is simply z-buffering that is done prior to shading. This is
`
`efficient because the graphics processor doesn’t have to spend time shading primitives
`
`that will never be seen anyway (e.g., a tree that is behind a building). Accordingly, the
`
`broadest reasonable interpretation of this an “early z interface” is “an interface with a z
`
`buffer logic unit that provides for visibility testing prior to shading and texturing.”
`
`54.
`
`Late z-buffering is simply z-buffering that is done after shading. In certain
`
`cases early z-buffering does not discard all of the fragments that will be obstructed and
`
`they are caught by the late z-buffering. Accordingly, the broadest reasonable
`
`interpretation of this a “late z interface” is “an interface with a z buffer logic unit that
`
`provides for visibility testing after shading and texturing.”
`
`55.
`
`These well understood concepts are described in the ’506 Patent:
`
`If the current Z buffering mode is set to “early,” each quad is passed to
`
`the Z buffer 555 where its Z values are compared against the values
`
`stored in the Z buffer at that location…. At this stage, those quads for
`
`which none of the covered pixels passed the Z compare test are
`
`discarded. The early Z functionality attempts to minimize the amount
`
`
`
`31
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`ARM, Ex. 1003, Page 31
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`
`
`
`
`
`
`
`
`
`
`of work applied by the unified shader and texture unit to quads that are
`
`not visible.
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`Ex. 1001 (’506 Patent) at 6:22-33 (emphasis added).
`
`
`[i]f the current Z buffering mode is set to “late,” the Z values for the
`
`quad are compared against the values stored in the Z buffer at that
`
`location…. Although early Z operation is preferred for performance
`
`reasons, in certain situations the unified shader might modify the
`
`contents of the coverage mask… and in these cases the z buffering
`
`mode will need to be set to “late”
`
`Id at 6:66-7:9 (describing operations after shading and texturing).
`
`
`32
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`ARM, Ex. 1003, Page 32
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`
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`
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`
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`Ex. 1001 (’506 Patent) at Figure 5 (disclosing
`early z-interface prior to shading and texturing and
`the late z-interface after shading and texturing)
`
`
`
`VII. GROUND 1: RUBINSTEIN IN VIEW OF COLLODI (CLAIMS 1-9)
`
`56.
`
`I have reviewed and am familiar with the following prior art references: (1)
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`U.S. Patent No. 7,102,646 (“Rubenstein”) (Ex. 1004) and (2) U.S. Patent Application
`
`
`
`33
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`ARM, Ex. 1003, Page 33
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`
`
`
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`No. 10/037/992, which was later published as Publication No. US 2003/0076320A1
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`(“Collodi”) (Ex. 1007).
`
`57.
`
`It is my opinion that the combination of Rubinstein in view of Collodi
`
`renders claims 1-7 and 9 of the ’506 Patent obvious.
`
`B.
`
`Rubinstein
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`58. U.S. Patent No. 7,102,646 (“Rubenstein”) was filed on July 9, 2014 as a
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`continuation of Application No. 09/709,964, now U.S. Patent No. 6,856,320 (“Zhu
`
`’320”). Zhu ’320 was filed on November 10, 2000 as a continuation in part of an
`
`application that issued as U.S. Patent No. 6,697,063 (“Zhu ’063”). Rubinstein
`
`incorporates the disclosures of Zhu ’320 and Zhu ’063 by references because the three
`
`patents relate to different features of the same inventive graphics processing chip. Ex.
`
`1004 (Rubinstein)
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