UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`ARM Ltd. and ARM, Inc.,
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`Petitioners
`
`v.
`Advanced Micro Devices, Inc. and ATI Technologies ULC, Patent
`Owner
`
`U.S. Patent No. 7,633,506
`Date: December 15, 2009
`Title: Parallel Pipeline Graphics System
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`CASE: IPR2018-01148
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`Petition for Inter Partes Review of U.S. Patent No. 7,633,506
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`

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`Petition for Inter Partes Review of U.S. Patent No. 7,633,506
`
`EXHIBIT LIST
`Ex. 1001 U.S. Patent No. 7,633,506 (“the ’506 Patent”).
`Ex. 1002
`File History of U.S. Patent No. 7,633,506. (“File History”) (Excerpts).
`Ex. 1003 Declaration of Dr. Hanspeter Pfister
`Ex. 1004
`“Reality Engine Graphics” by Kurt Akeley (“Akeley”)
`Ex. 1005 U.S. Patent No. 5,808,690 (“Rich”)
`Ex. 1006 U.S. Patent No. 6,646,639 (“Greene”)
`Ex. 1007 April 26, 2000 Press release describing Nvidia GeForce 2 Graphics
`Chip Ex. 1008 January 5, 2001 Article describing Nvidia GeForce 3
`Graphics Chip
`Initial Determination in U.S. International Trade Commission Inv. No.
`337-TA-1044
`
`Ex. 1008
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`
`
`
`
`i
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`

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`TABLE OF CONTENTS
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`Page
`
`I.
`
`II.
`III.
`
`PRELIMINARY STATEMENT AND MOTION FOR JOINDER
`REFERENCE ................................................................................................. 1
`INTRODUCTION .......................................................................................... 3
`37 C.F.R. § 42.8(b): MANDATORY NOTICES .......................................... 6
`A.
`37 C.F.R. § 42.8(b)(1): Real Party In Interest ..................................... 6
`B.
`37 C.F.R. § 42.8(b)(2): Related Matters .............................................. 7
`C.
`37 C.F.R. § 42.8(b)(3) and (4): Notice Of Counsel And Service
`Information .......................................................................................... 8
`Fees under 37 C.F.R. § 42.103 ............................................................ 8
`D.
`IV. REQUIREMENTS FOR INTER PARTES REVIEW .................................... 8
`A.
`37 C.F.R. § 42.104(a): Ground For Standing ...................................... 9
`B.
`37 C.F.R. § 42.104(b): Identification Of Challenge ............................ 9
`1.
`37 C.F.R. § 42.104(b)(1) Challenged Claims ........................... 9
`2.
`37 C.F.R. § 42.104(b)(2): The Prior Art And Statutory
`Grounds. .................................................................................... 9
`Level of Ordinary Skill in the Art ........................................... 10
`3.
`37 C.F.R. § 42.104 (b)(3) Claim Construction ........................ 10
`4.
`37 C.F.R. § 42.104(b)(4) How the Claims are Unpatentable. . 11
`5.
`Supporting Evidence ............................................................... 11
`6.
`THE CHALLENGED CLAIMS ARE UNPATENTABLE. ....................... 11
`A.
`Technology Background .................................................................... 11
`B.
`The Alleged Invention of the ’506 Patent. ......................................... 14
`C.
`Prosecution History of the ’506 Patent .............................................. 20
`
`V.
`
`ii
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`

`

`D.
`
`E.
`
`F.
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`TABLE OF CONTENTS
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`Page
`Proposed Claim Construction ............................................................ 21
`1.
`Z-Buffer Logic Unit ................................................................ 22
`2.
`“Hierarchical Z-Interface” ....................................................... 22
`3.
`“Early Z-interface” and “Late Z-interface” ............................. 23
`4.
`“Unified Shader” ..................................................................... 26
`Ground 1: Obviousness by Akeley in view of Rich (Claims 1-3 and
`5-9) ..................................................................................................... 26
`1.
`Akeley ...................................................................................... 26
`2.
`Rich .......................................................................................... 28
`3. Motivation to Combine ............................................................ 32
`4.
`Claim 1 .................................................................................... 36
`5.
`Claim 2 .................................................................................... 53
`6.
`Claim 3 .................................................................................... 54
`7.
`Claim 5 .................................................................................... 59
`8.
`Claim 6 .................................................................................... 60
`9.
`Claim 7 .................................................................................... 64
`10. Claim 8 .................................................................................... 65
`11. Claim 9 .................................................................................... 70
`Ground 2: Akeley in View of Rich in Further View of Greene (Claim
`4). ....................................................................................................... 72
`1.
`Greene ...................................................................................... 72
`2. Motivation to Combine ............................................................ 72
`3.
`Claim 4 .................................................................................... 75
`
`iii
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`TABLE OF CONTENTS
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`Page
`VI. CONCLUSION ............................................................................................ 79
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`
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`iv
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`

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`Petition for Inter Partes Review of U.S. Patent No. 7,633,506
`
`I.
`
`PRELIMINARY STATEMENT AND MOTION FOR JOINDER
`REFERENCE
`Petitioners ARM, Inc. and ARM Ltd. (“Petitioners”) respectfully request
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`inter partes review and seek cancellation of claims 1-9 of U.S. Patent No.
`
`7,633,506 (“the ’506 Patent”) under 35 U.S.C. §§ 311-319 and 37 C.F.R. § 42.100
`
`et seq. The Board previously instituted inter partes review of claims 1-9 of the
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`’506 Patent in IPR2018-00101 on April 27, 2018.1 Petitioners seek to join
`
`IPR2018-00101 and are filing a concurrent Motion for Joinder. This Petition and
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`the associated Motion for Joinder are timely under 37 C.F.R. §§ 42.22 and
`
`42.122(b), as they are submitted within one month of the date on which IPR2018-
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`00101 was instituted. Petitioners have consulted with the petitioners in IPR2018-
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`00101 and the Patent Owners. The petitioners in IPR2018-00101 do not oppose
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`this motion for joinder. The Patent Owners did not provide a position on this
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`joinder.
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`Joinder is appropriate because of the substantial similarity between
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`IPR2018-00101 and the present Petition. The present Petition is largely a verbatim
`
`copy of the Petition in IPR2018-00101 with limited changes as cited below.
`
`
`1 According to the Patent Owner’s Preliminary Response (“POPR”) filed in
`IPR2018-00101, ATI Technologies ULC is the owner of the ‘506 patent. See
`IPR2018-00101, POPR at 1, n. 1 (Paper 6, January 3, 2018). For consistency with
`the petition in IPR2018-00101 and with the POPR in IPR2018-00101, ATI
`Technologies ULC and Advanced Micro Devices, Inc. are jointly referred to herein
`as “ATI” or “Patent Owner” or “Patent Owners.”
`
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,633,506
`
`
`Petitioners have retained the same expert as the Petitioners in IPR2018-00101 and
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`the expert’s declaration is substantively identical to that in IPR2018-00101. For
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`the convenience of the Board and parties, Petitioners have used the same Bates
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`stamping on exhibits and the same paragraph citations to the expert reports.
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`As noted in the Motion for Joinder, other factors relevant to joinder also
`
`favor granting this motion, including that: (i) the same schedule for various
`
`proceedings can be adopted; (ii) Petitioners are not advancing any new expert
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`testimony, and thus, discovery will not be impacted by joinder; (iii) joinder will not
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`materially affect the range of issues needing to be addressed by the Board and by
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`the parties in the joined proceedings; (iv) joinder will not prejudice any party; and
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`(v) Petitioners are willing to agree to procedural safeguards to minimize burden.
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`See Kyocera Corp. v. Softview LLC, IPR2013-00004, Paper 15 at 4 (Apr. 24,
`
`2013). As discussed below, Petitioners have not been served with a Complaint in
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`any action asserting the ‘506 Patent and thus 35 U.S.C. § 315 does not bar this
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`Petition. Even if such a Complaint had been served, section 315(b) does not apply
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`to the co-filed motion for joinder. See Activision Blizzard, Inc. v. Game and
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`Technology Co., Ltd., IPR2018-00157, Paper 12 at 17-18 (May 3, 2018). “Because
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`§ 315(b) expressly states that ‘[t]he time limitation set forth in the preceding
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`sentence shall not apply to a request for joinder under subsection (c),’ Petitioner’s
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`request for joinder is not time-barred.” Id. at 18.
`2
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`

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`Petition for Inter Partes Review of U.S. Patent No. 7,633,506
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`
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`The following are the primary modifications between the current Petition
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`and the Petition filed in IPR2018-00101. First, the explanations of the real party in
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`interest and the related ITC Investigation below have been adapted. Second,
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`Petitioners attach as Exhibit 1008 a public version of the Initial Determination in
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`the related ITC Investigation. Third, Petitioners note that they adopt and agree
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`with the Board’s claim construction of “unified shader” in the Institution Decision
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`in IPR2018-00101. See IPR2018-00101, Paper 13 at 9-24 (April 27, 2018
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`Institution Decision). Fourth, for claim constructions other than “unified shader,”
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`Petitioners note that those claim constructions as proposed in the petition in
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`IPR2018-00101 are correct under both a broadest reasonable interpretation and
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`under the claim construction analysis under Phillips v. AWH Corp., 415 F.3d 1303
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`(Fed. Cir. 2005).
`
`II.
`
`INTRODUCTION
`The ’506 Patent claims a graphics processing system with various features
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`that were well-known and commonplace at the time the patent was filed. It alleges
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`these claimed features are innovative and novel, but, at the time the patent was
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`filed, persons of skill in the art had already been implementing these features in
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`graphics systems for a decade. As shown below, these features were all well-
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`known before the ’506 Patent’s priority date in 2002:
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`
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`3
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`

`Petition for Inter Partes Review of U.S. Patent No. 7,633,506
`
`•
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`Parallel Pipelines for Pixel Processing: This practice has been
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`implemented in prior art systems since the 1980s, and was extremely
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`common in graphics systems by 2000. Akeley, for example, is a 1993
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`reference that discusses a system that used parallel pipelines for pixel
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`processing.
`
`•
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`Unified Shaders: Flexible and programmable shaders that performed
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`both color shading and texture shading were also used as early as the
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`1980s. Akeley, for example, is a 1993 reference that discloses such
`
`unified shaders.
`
`•
`
`Tiling: Tiling is a feature that was developed in the 1990s, nearly a
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`decade prior to the filing of the ’506 Patent. Moreover, it was a well-
`
`known and common feature in graphics pipelines by 2002. Akeley
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`(1993) discloses a system that performs a form of tiling and Rich is a
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`patent filed in 1996 that describes tiling as a prior art technique.
`
`•
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`Z-buffering: Z buffering was also developed more than a decade prior
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`to the ’506 patent and common place in graphics pipelines by the time
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`the ’506 Patent was filed. Akeley (1993) discloses a system that
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`performs z-buffering and Rich (1996) describes it as a feature that was
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`already well-known.
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`4
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`

`Petition for Inter Partes Review of U.S. Patent No. 7,633,506
`
`
`
`As the above discussion makes clear, there were systems in existence 10
`
`years prior to the filing of the ’506 Patent that implemented the features the ’506
`
`Patent claims as novel. Akeley (Ex. 1004, described within) is one system with
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`such implementations, but there were others. See, e.g., Exhibit 1005 (Rich) at
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`2:40-59 (describing Pixel Planes and Pixel Flow systems as prior art). Generally,
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`these systems were graphics boards comprising a number of flexible processors
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`that could perform both color shading and texture shading (unified shaders) and
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`that processed individual portions of the screen (tiling). The processors in these
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`systems also processed their portions of the screen simultaneously with the other
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`processors (parallel processing) and had the ability to perform depth testing in
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`order to cull out hidden objects (z-buffering).
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`The patent owner may seek to distinguish the ’506 patent from prior art
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`systems like Akeley on the ground that the ’506 system is limited to a single chip.
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`But, the applicable law does not allow for such a distinction because the
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`’506 Patent claims are not limited to single chip embodiments. Moreover, even if
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`they were so limited, persons of skill in the art had already started to compress
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`graphics boards into graphics chips at least as early as the mid-1990s – well before
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`the ’506 Patent. Rich, for example, is a 1996 patent that discloses a method for
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`implementing the functionality of graphics boards like Akeley using flexible and
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`parallel “ALU processing elements” within a single chip instead of separate
`5
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`Petition for Inter Partes Review of U.S. Patent No. 7,633,506
`
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`processors on a board. Ex. 1005 (Rich) at 3:44-46 (“Preferably, an image
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`generation system according to the present invention is formed as a single
`
`integrated device or chip.”). Moreover, by 2001—a year before the priority date of
`
`the ’506 Patent—there were already multiple generations of single-chip processors
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`on the market. See Ex. 1003, 1007, and 1008 (describing single-chip graphics
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`processors released in 2000 and 2001).
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`Accordingly, the alleged invention of the ’506 Patent amounts to nothing
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`more than the reproduction of well-known and commonly-used features, and the
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`prior art discussed below renders the challenged claims unpatentable.
`
`III. 37 C.F.R. § 42.8(B): MANDATORY NOTICES
`37 C.F.R. § 42.8(b)(1): Real Party In Interest
`A.
`Petitioners are the real parties in interest. Petitioners are not respondents in
`
`the pending ITC investigation below. None of the co-respondents in the pending
`
`investigation identified below is a real party in interest to this proceeding. The co-
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`respondents included: the Petitioners in IPR2018-00101 (MediaTek Inc and
`
`MediaTek USA Inc.), LG Electronics, Inc., LG Electronics, USA, Inc., and LG
`
`Electronics MobileComm USA, Inc., Sigma Designs, Inc., and VIZIO, Inc.. None
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`of these parties financed or controlled this Petition (or had the opportunity to
`
`exercise control over this Petition) or otherwise meet the requirements of 35 U.S.C.
`
`§ 312(a)(2).
`
`
`
`6
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`

`Petition for Inter Partes Review of U.S. Patent No. 7,633,506
`
`
`
`37 C.F.R. § 42.8(b)(2): Related Matters
`B.
`The ’506 Patent is the subject of the following actions brought by Patent
`
`Owner against other parties that may affect or be affected by a decision in this
`
`proceeding: U.S. International Trade Commission Inv. No. 337-TA-1044 and U.S.
`
`District Court for the District of Delaware Case No. 1:17-cv-00065. Other patents
`
`asserted in the related matters include U.S. Patent Nos. 7,796,133; 8,760,454; and
`
`9,582,846. A copy of the public version of the ALJ’s Initial Decision in 337-TA-
`
`1044 is attached hereto as Exhibit 1008.
`
`The ’506 Patent was also subject to a petition for inter partes review, Case
`
`No. IPR2017-01670, which was terminated on September 29, 2017.
`
`In IPR2018-00102, the Board instituted trial based upon Claims 1–9 as
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`unpatentable under 35 U.S.C. § 103 over U.S. Patent No. 7,102,646 (“Rubinstein”)
`
`in view of U.S. Patent Appl. Publ. No. 2003/0076320 (“Collodi”), and Claims 8–9
`
`as unpatentable under 35 U.S.C. § 103 over Rubinstein, in view of Collodi, and in
`
`further view of U.S. Patent No. 6,809,732 (“Zatz”). See IPR2018-00102, Paper 14
`
`(April 27, 2018). Petitioners are concurrently filing a separate petition for inter
`
`partes review and motion for joinder seeking to join IPR2018-00102 in which, just
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`as in the present Petition, Petitioners adopt the same arguments and include the
`
`same expert declaration as was filed by the petitioners in IPR2018-00102.
`
`
`
`7
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`Petition for Inter Partes Review of U.S. Patent No. 7,633,506
`
`
`
`C.
`
`37 C.F.R. § 42.8(b)(3) and (4): Notice Of Counsel And Service
`Information
`Petitioners provide the following designation of counsel:
`
`Lead Counsel
`
`Backup Counsel
`
`Kevin Anderson, Reg. No. 43,471
`kanderson@wileyrein.com
`Wiley Rein LLP
`1776 K Street, N.W.
`Washington DC 20006
`Phone (202) 719-7000
`Fax (202) 719-7049
`
`Scott Felder, Reg. No. 47,558
`sfelder@wileyrein.com
`Wiley Rein LLP
`1776 K Street, N.W.
`Washington DC 20006
`Phone (202) 719-7000
`Fax (202) 719-7049
`
`Deposit Account No. 50-1129 with
`
`Deposit Account No. 50-1129 with
`
`reference to Attorney Docket No.
`
`reference to Attorney Docket No.
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`82819.0056
`
`
`
`82819.0056
`
`Petitioners submit Powers of Attorney with this Petition. Please address all
`
`correspondence to lead and backup counsel. Petitioners consent to service by email
`
`at: kanderson@wileyrein.com and sfelder@wileyrein.com.
`
`Fees under 37 C.F.R. § 42.103
`D.
`Petitioners concurrently submit fees of $30,500. If more fees are necessary
`
`to accord this Petition a filing date, authorization is granted to charge the same to
`
`Deposit Account No. 50-1129 with reference to Attorney Docket No. 82819.0056.
`
`IV. REQUIREMENTS FOR INTER PARTES REVIEW
`
`
`
`8
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`

`Petition for Inter Partes Review of U.S. Patent No. 7,633,506
`
`
`
`As set forth below, this Petition meets and complies with all requirements
`
`under 37 C.F.R. § 42.104 for inter partes review.
`
`37 C.F.R. § 42.104(a): Ground For Standing
`A.
`Pursuant to 37 C.F.R. § 42.104(a), Petitioners certify that the ’506 Patent is
`
`available for inter partes review and Petitioners are not barred or estopped from
`
`requesting inter partes review challenging the claims of the ’506 Patent on the
`
`grounds identified herein.
`
`37 C.F.R. § 42.104(b): Identification Of Challenge
`B.
`Pursuant to 37 C.F.R. § 42.104(b), Petitioners request that the PTAB
`
`invalidate the challenged claims of the ’506 Patent.
`
`37 C.F.R. § 42.104(b)(1) Challenged Claims
`1.
`Petitioners challenge claims 1-9 of the ’506 Patent.
`
`2.
`
`37 C.F.R. § 42.104(b)(2): The Prior Art And Statutory
`Grounds.
`The one-year time bar under pre-AIA 35 U.S.C. §102(b) is measured from
`
`the effective U.S. filing date of the ’506 Patent, which is no earlier than November
`
`27, 2002. The prior art references relied upon herein are:
`
`Patent/Publication
`
`U.S. Patent No. 5,808,690
`(“Rich”)
`
`Priority Date Publication
`Date
`
`Prior
`Art
`
`Ex.
`No.
`
`June 10, 1996 Sep. 16, 1998
`
`102(b) 1005
`
`
`
`9
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,633,506
`
`“Reality Engine Graphics”
`authored by K. Akeley
`(“Akeley”)
`
`At least as
`early as June
`30, 1994
`
`At least as
`early as June
`30, 1994
`
`102(b) 1004
`
`U.S. Patent No. 6,646,639
`(“Greene”)
`
`May 23, 2001 Nov. 11, 2003
`
`102(e) 1006
`
`
`
`
`
`Below are the specific statutory grounds under 35 U.S.C. §§ 102 and 103
`
`(pre-AIA) on which the claims are challenged:
`
`Ground 1: Claims 1-3 and 5-9 are rendered obvious under 35 U.S.C.
`
`§103(a) by Akeley in view of Rich.
`
`Ground 2: Claim 4 is rendered obvious under 35 U.S.C. § 103(a) by Akeley
`
`in view of Rich in further view of Greene.
`
`Level of Ordinary Skill in the Art
`3.
`A person of ordinary skill in the art, at the time the ’506 patent was
`
`effectively filed, would have had at least a four-year degree in electrical
`
`engineering, computer engineering, computer science, or a related field and two
`
`years relevant experience in the graphics processing field including developing,
`
`designing or programming hardware for graphics processing units. Ex. 1003
`
`(Pfister Decl.), ¶ 46.
`
`37 C.F.R. § 42.104 (b)(3) Claim Construction
`4.
`Petitioners’ proposed constructions of certain terms in the challenged claims
`
`
`
`10
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,633,506
`
`
`pursuant to this standard are provided in Section V.D below. Petitioners adopt the
`
`Board’s claim construction of “unified shader” in the Institution Decision of
`
`IPR2018-00101 and assert that well-reasoned construction is the proper claim
`
`construction analysis under Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir.
`
`2005).
`
`37 C.F.R. § 42.104(b)(4) How the Claims are Unpatentable.
`5.
`Sections V.E and V.F below explain how claims 1-9 of the ’506 Patent are
`
`unpatentable, including an identification of where each element of the claims is
`
`found in the prior art.
`
`Supporting Evidence
`6.
`Supporting evidence relied upon includes the declaration of Dr. Hanspeter
`
`Pfister, Ph.D. (Ex. 1003) and other supporting evidence in the Exhibit List filed
`
`herewith. Dr. Pfister’s background and qualifications, and the information
`
`provided to him, are discussed in Ex. 1003.
`
`V. THE CHALLENGED CLAIMS ARE UNPATENTABLE.
`A. Technology Background
`Graphics processing is an important part of any computer system, and has
`
`been for the past several decades. The purpose of a graphics processor is to
`
`generate complex shapes and structures to be displayed on a screen. Ex. 1003
`
`(Pfister Decl.), ¶ 29. In order to accomplish that purpose, a graphics processor
`
`
`
`11
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,633,506
`
`
`converts a 3D object or scene (comprised of points in 3D space called “vertices”
`
`that make up shapes called “primitives”) into a 2D image to be displayed on a
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`computer screen (comprised of “pixels”). Generally, 3D graphics processing starts
`
`with creating a mathematical model of each object. Id., ¶ 29. The model is then
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`processed through a series of steps, referred to as a “graphics processing pipeline,”
`
`that render the scene as a 2D image on a display:
`
`In most cases, 3D objects are conceptualized as a series of primitives (e.g.,
`
`triangles) that cover the surface of an object, such as a teapot:
`
`
`
`
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`12
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,633,506
`
`
`
`
`
`Each point of the primitive is called a “vertex” and each vertex has certain
`
`properties, which are represented as data. Id., ¶ 31. For example, a vertex includes
`
`not just its location, but may also include other information, such as the color of
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`the object and its material properties (e.g., whether it is reflective). A vertex
`
`processor performs the steps in the graphics pipeline that transform these vertices
`
`from 3D space into 2D space and determines how lighting and other conditions in
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`the 3D scene impact the color of the vertices. Id., ¶ 31. The ’506 Patent refers to
`
`these operations on vertices as “front-end” operations.
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`After the “front-end” processing, a number of steps occur to transform the
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`2D shapes into a final image that can be displayed.
`
`
`
`
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`
`
`
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`13
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,633,506
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`
`
`The ’506 Patent refers to this as “back-end” processing. The first step, called
`
`rasterization, determines what pixels on the 2D screen are covered by each
`
`primitive. At least one “fragment” is generated for each pixel on the screen (as a
`
`result, the terms “fragment” and “pixel” are sometimes used interchangeably). Id.,
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`¶ 32. Rasterization commonly includes the step of “scan conversion,” which
`
`involves stepping through the geometry of the primitives to determine which pixels
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`are covered. Id., ¶ 33. Subsequent operations including various forms of shading,
`
`texturing, blending, and other effects, each of which affects the final color of each
`
`pixel. These operations are commonly called “pixel shading” operations and may
`
`involve lighting, texture and bump mapping, translucency and other phenomena.
`
`The results of each operation is gathered together through merging or blending of
`
`pixels for the final image to be displayed on a screen.
`
`B.
`
`The Alleged Invention of the ’506 Patent.
`
`
`
`14
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`

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`Petition for Inter Partes Review of U.S. Patent No. 7,633,506
`
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`The ’506 Patent discloses and claims a graphics processing system that
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`includes a front-end and a back-end. Ex. 1001 at Abstract and Claim 1. The front-
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`end receives instructions (and graphics data) and outputs primitives or
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`combinations of primitives (e.g. triangles, parallelograms, etc.) (i.e., geometry).
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`Id. at Claim 1. The back-end receives the primitives and processes them into
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`a final image comprised of colored pixels. Id. For various embodiments, the
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`claimed invention also includes one or more of the following features:
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`Back-end with Parallel Pipelines: The ’506 Patent discloses and claims a
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`system with a back-end comprised of multiple parallel pipelines. Id. These parallel
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`pipelines each process a different portion of the screen in parallel. Id.
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`Ex. 1001 (’506 Patent) at Figure 3.
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`Unified Shader: Each pipeline contains a “unified shader.” Id. at Claim 1.
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`The ’506 Patent defines a “unified shader” to mean a shading unit that
`performs both pixel color shading and texture address shading.2 Id. at 6:49-53. The
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`shader is capable of, for example, calculations related to determining and applying
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`a color to a fragment or pixel (color shading), and it is also capable of calculations
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`related to determining texture coordinates for a texture look-up (texture address
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`shading). Id.
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`2 This is contrary to the current understanding of the term “unified shader” in the
`industry today. Pursuant to developments outside of the ’506 Patent, the term
`“unified shader” has come to commonly mean a unit that performs computations
`on both vertex (geometry) data and pixel data. Ex. 1003 (Pfister Decl.), ¶ 38. Or, as
`the ’506 Patent would put it, a shader that performs computations on both “front-
`end” and “back-end” data. Id. The ’506 Patent, however, clearly does not use the
`term in this way, and, instead, gives the term a definition unique to the patent. Id.
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`Ex. 1001 (’506 Patent) at Figure 5 (showing various components within each of the
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`parallel pipelines of the ’506 graphics processing system, with the Unified Shader
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`annotated).
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`Tiling and Set-up Unit: Each pipeline in the ’506 Patent’s system processes
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`specific portion(s) or “tile(s)” of the screen. Id. at Claims 1 and 6. To facilitate this
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`process, the system includes a “set-up unit” that receives primitives/geometry from
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`the front-end, determines which portion or “tile” of the screen the geometry is
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`located in, and then directs the geometry to be processed by one of the multiple
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`pipelines. Id. at claim 6.
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`Ex. 1001 (’506 Patent) at Figure 5 (with Setup Unit annotated).
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`Z-buffering: In certain embodiments, each pipeline also includes a “z-buffer
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`logic unit” that scans the incoming primitives and determines which primitives will
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`be visible to the screen. Id. at Claims 3-5. The z-buffer logic unit may perform
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`“early z” operations through an early z-interface, i.e., visibility testing prior to
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`pixel shading. See e.g., claim 4. In other embodiments, it may perform “late z”
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`operations, i.e., visibility testing after pixel shading. Id. at Claim 5. The z-buffer
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`may also perform hierarchical z-buffering, which involves visibility testing at a
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`coarse level, i.e. coarser than fragment-by-fragment or pixel-by-pixel. Id. at 6:1-
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`15.
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`Ex. 1001 (’506 Patent) at Figure 5 (with Z buffer logic unit annotated).
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`Prosecution History of the ’506 Patent
`C.
`The ’506 Patent’s application was filed on November 26, 2003. The
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`application included 16 claims directed to graphics systems comprising, among
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`other things, the elements listed in the previous section. Ex. 1002 (’506
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`Prosecution History). After several office actions, the Examiner allowed some of
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`the amended claims. Ex. 1002 at 39.
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`In allowing the claims of the ’506 Patent, the examiner recognized that
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`several prior art references taught rendering pipeline systems that used screen
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`space tiling and double z-buffering schemes claimed by the ’506 patent. Ex. 1002
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`at 36-41, 7/30/2009 Notice of Allowance. The examiner stated, however, that the
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`references he reviewed did not disclose parallel pipelines with unified shaders as
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`claimed by the ’506 Patent. Id.
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`Nonetheless, as explained below, using parallel pipelines and “unified
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`shaders” (as defined by the ’506 Patent) was well-known and obvious at the time
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`the ’506 Patent was filed. Ex. 1003 (Pfister Decl.), ¶ 45.
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`Proposed Claim Construction
`D.
`Petitioners propose construction of certain claim terms below pursuant to the
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`Phillips standard.3 The proposed claim constructions are offered to comply with
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`37 C.F.R. §§ 42.100(b) and 42.104(b)(3) and for the sole purpose of this Petition.
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`3 The Petitioners in IPR2018-00101 proposed these constructions under a
`“Broadest Reasonable Interpretation” standard. To maintain the consistency and
`identity with the petition in IPR2018-00101, this present Petition retains the
`language reciting “Broadest Reasonable Interpretation” for these constructions.
`However, the present Petitioners assert that these constructions are proper under
`both “Broadest Reasonable Interpretation” and the Phillips standard.
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`Z-Buffer Logic Unit
`1.
`Claims 3-5 require a “Z Buffer Logic Unit.” The Broadest Reasonable
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`Interpretation of a “Z-Buffer Logic Unit” is “a logic unit that facilitates visibility
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`testing by comparing depth values.” Ex. 1003 (Pfister Decl.), ¶¶ 47-48.
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`As the ’506 Patent explains, a “z-buffer” is a memory space that the z-buffer
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`logic unit uses to store the “z” or “depth” values (i.e., the distance from the screen)
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`for primitives or portions of primitives. See, e.g., Ex. 1001 (’506 Patent) at 6:20-
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`26; 6:64-7:3. The logic unit then compares those values to other primitives that
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`may occupy the same screen space. Id. at 6:20-23 (“For each quad, coverage and Z
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`(depth) information is computed…. [E]ach quad is passed to the Z buffer 555
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`where its Z values are compared against the values stored in the Z buffer at that
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`location.”) If the comparison reveals that the particular primitive or portion of the
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`primitive is behind another primitive (i.e. not visible to the screen) the Z-buffer
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`logic unit discards that primitive. Id. at 6:28-30 (“At this stage, those quads for
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`which none of the covered pixels passed the Z compare test are discarded.”)
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`Accordingly, the broadest reasonable interpretation of a Z-buffer Logic Unit
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`is “a logic unit that facilitates this visibility testing by comparing pertinent values.”
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`“Hierarchical Z-Interface”
`2.
`Claim 4 requires a “Hierarchical Z-Interface.” The broadest reasonable
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`interpretation of this term is “an interface with a z-buffer logic unit that provides
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`for visibility testing at a coarse level, including, for example, for an entire tile or
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`primitive.” Ex. 1003 (Pfister Decl.), ¶¶ 49-50.
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`The ’506 Patent discloses that a hierarchical Z-interface is one that steps
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`through the geometry at a coarse level (e.g., across an entire tile) to determine if
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`the entire geometry or portion of that geometry can be discarded:
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`A scan converter 540 works in conjunction with Hierarchical Z- interface of
`Z buffer logic 555 to step through the geometry (e.g., triangle or
`parallelogram) within the bounds of the pipeline’s tile pattern. In one
`embodiment, initial stepping is performed at a coarse level. For each of the
`coarse level tiles, a minimum (i.e. closest) Z value is computed. This is
`compared with the farthest Z value for the tile stored in a hierarchical-Z
`buffer 550. If the compare fails, the tile is rejected.
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`Ex. 1001 (’506 Pate