UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`ARM Ltd. and ARM, Inc.,
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`Petitioners
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`v.
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`Advanced Micro Devices, Inc. and ATI Technologies ULC,
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`Patent Owner
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`U.S. Patent 7,633,506 Issue Date: December 15, 2009
`Title: Parallel Pipeline Graphics System
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`CASE: IPR2018-01148
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`DECLARATION OF DR. HANSPETER PFISTER, Ph.D. IN SUPPORT OF
`PETITION FOR INTER PARTES REVIEW
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`ARM, Ex. 1003, Page 1
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`
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`ARM Ltd. and ARM, Inc.,
`
`Petitioners
`
`v.
`
`Advanced Micro Devices, Inc. and ATI Technologies ULC,
`
`Patent Owner
`
`U.S. Patent 7,633,506 Issue Date: December 15, 2009
`Title: Parallel Pipeline Graphics System
`
`CASE: IPR2018-01148
`
`DECLARATION OF DR. HANSPETER PFISTER, Ph.D. IN SUPPORT OF
`PETITION FOR INTER PARTES REVIEW
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`ARM, Ex. 1003, Page 1
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`
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`I, Dr. Hanspeter Pfister, Ph.D., declare as follows:
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`1.
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`I have been retained by counsel for Petitioners, ARM Ltd. and ARM,
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`Inc., as an expert in this inter partes review to examine whether claims 1-9 of U.S.
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`Patent No. 7,633,506 are patentable over certain prior art. With the exception of the
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`identification of the party retaining my services, this declaration is identical to my
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`declaration that was filed in IPR2018-00101.
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`2.
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`I have personal knowledge of all the facts set forth herein, and if called
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`to testify at any hearing in this inter partes review, I would competently testify and
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`verify that testimony contained herein.
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`3.
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`I am being compensated at my hourly rate of $600 per hour. I am also
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`being reimbursed for out-of-pocket expenses. My compensation does not depend in
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`any way on the outcome of this proceeding or the particular opinions I express, or
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`the testimony I give.
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`4.
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`I expect to be available for deposition and to testify at the evidentiary
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`hearing in this inter partes review to the extent required.
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`5.
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`This declaration contains my conclusions and a summary of my
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`analysis including a summary of my conclusions; an overview of my qualifications
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`as an expert; an overview of the scope and terms of my engagement for this
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`declaration; an overview of the materials I have considered in arriving at my
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`conclusions; an overview of the terminology and legal principles that I applied in
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`my analysis; an overview of the technical background of the subject matter; an
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`ARM, Ex. 1003, Page 2
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`overview of the Patent in Suit; an analysis of the level of ordinary skill in the art
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`related to the Patent in Suit; an analysis of the asserted references; and a
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`patentability analysis of the challenged claims.
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`6.
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`This declaration is based on information currently available to me. I
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`intend to continue my investigation and study, which may include a review of
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`documents and information that may yet be produced, as well as deposition
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`testimony from depositions for which transcripts are not yet available or that may
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`yet be taken in this review. Therefore, I expressly reserve the right to expand or
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`modify my opinions as my investigation and study continue, and to supplement my
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`opinions in response to any additional information that becomes available to me, any
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`matters raised by Patent Owner and/or other opinions provided by Patent Owner’s
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`expert(s), or in light of any relevant orders from the Patent Trial and Appeal Board
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`or other authoritative body.
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`I.
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`SUMMARY OF OPINION
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`7.
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`It is my opinion that claims 1-9 of the ’506 Patent are rendered obvious
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`by the prior art references discussed below. I will explain below my analysis and
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`basis for my opinion in detail.
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`II. EXPERT QUALIFICATIONS AND PRIOR TESTIMONY
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`8. My curriculum vitae is attached hereto as Attachment A, which
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`provides an accurate identification of my relevant background and experience in
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`multithreaded graphics processors. For the past 25 years, I have focused on
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`ARM, Ex. 1003, Page 3
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`computer graphics processing in both industrial and academic settings. I have
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`designed cutting-edge graphics processing systems, including the world’s first real-
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`time volume rendering graphics card. I have pioneered research into various aspects
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`of computer graphics and received academic awards and industry recognition for my
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`work in computer graphics.
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`9.
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`In 1991, I received my M.Sc. in Electrical Engineering from the Swiss
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`Federal Institute of Technology (ETH) Zurich, Switzerland. I then proceeded to
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`study computer science at the State University of New York at Stony Brook, Stony
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`Brook, NY, where I earned my M.S. in Computer Science in 1994 and my Ph. D. in
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`Computer Science in 1996.
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`10.
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`I am the An Wang Professor of Computer Science at the Harvard John
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`A. Paulson School of Engineering and Applied Sciences and an affiliate faculty
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`member of the Center for Brain Science. My research in visual computing lies at
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`the intersection of visualization, computer graphics, and computer vision. It spans a
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`wide range of topics, including bio-medical visualization, image and video analysis,
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`3D fabrication, and data science. From 2013 to 2017 I was director of the Institute
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`for Applied Computational Science. For most of this work we are leveraging the
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`power of graphics processing units (“GPUs”) for computer graphics, high-
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`throughput computing, and visualization. I am currently advising and co- advising
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`seven Ph. D. students, six post-doctoral fellows, and one research scientist. I also
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`supervised numerous research and thesis projects and student interns.
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`11. Before joining Harvard, I worked for over a decade at Mitsubishi
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`Electric Research Laboratories where I was Associate Director and Senior Research
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`Scientist. I was the chief architect of Mitsubishi Electric's VolumePro, the world’s
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`first PC graphics card for real-time visualization of volume data. The technology
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`was subsequently acquired by TeraRecon and is still in wide commercial use in
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`medicine, biology, engineering, and oil and gas exploration. VolumePro received
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`several technical awards, including Mitsubishi Electric President's Award in 2000.
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`Since then I have developed several new methods for high-quality and interactive
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`volume visualization on GPUs. I am the recipient of the 2010 IEEE Visualization
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`Technical Achievement award in recognition of my “seminal technical
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`achievements in real-time volume rendering.”
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`12.
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`I am a pioneer in point-based computer graphics, a subfield of computer
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`graphics that deals with modeling and rendering of point-sampled (e.g., laser-
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`scanned) objects. I am among the first to introduce data-driven approaches for
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`complex real-world objects to computer graphics, including human faces. And I
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`developed new camera and display technologies, including the world’s first end- to-
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`end real-time 3D TV system with auto-stereoscopic display. Currently, I am
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`collaborating with Harvard scientists on novel analysis and visualization approaches
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`in computational science, including neuroscience, genomics, systems biology,
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`astronomy, and medicine. I am co-inventor of over 50 US patents and co- author on
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`more than 160 peer-reviewed publications, including over 25 ACM SIGGRAPH
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`ARM, Ex. 1003, Page 5
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`papers, the premier forum in Computer Graphics.
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`13. From 1999 to 2007, I built a rich academic program in computer
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`graphics at the Harvard Extension School through the development of several new
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`courses, including CSCI E-234 “Introduction to Computer Graphics” (1999-2007),
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`CSCI E-235 “Advanced Computer Graphics” (2002), CSCI E-236 “Advanced
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`Topics in Computer Graphics” (2004-2006), and INDR E-399 “Independent Study
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`in Advanced Computer Graphics” (2003). After joining Harvard in 2007, I
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`introduced several new undergraduate and graduate courses that are also offered to
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`the general public through the Harvard Extension School, including CS171
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`“Visualization” (2007-present), CS175 “Introduction to Computer Graphics” (2010),
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`CS264 “Massively Parallel Computing” (2009-2011), CS205 “Introduction to
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`Computational Science” (2010-2012), and CS109 “Data Science” (2013- present).
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`14. Between 2009 and 2016 in collaboration with Prof. Alan Aspuru-Guzik
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`of the Chemistry and Chemical Biology faculty at Harvard, I was the co-PI
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`(Principal Investigator) of Harvard's CUDA Center of Excellence (CCOE). The
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`COE supported “outstanding research taking place in Massively Parallel
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`Programming and Computing” using GPUs.
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`15.
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`I have served on the papers committees of all major visualization and
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`graphics conferences, including ACM SIGGRAPH, IEEE Visualization, EuroVis,
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`Eurographics, Pacific Graphics, and many others. I have been the co-organizer of
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`various international workshops, symposia, and conferences in computer graphics
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`ARM, Ex. 1003, Page 6
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`and visualization, including general conference chair of IEEE Visualization 2002
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`and technical papers chair of ACM SIGGRAPH 2012. I previously chaired and am
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`currently a director of the IEEE Visualization and Graphics Technical Committee. I
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`served on the editorial board of the IEEE Transactions on Visualization and
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`Computer Graphics and the ACM Transaction on Graphics, the top two journals in
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`the field. I am co-editor of the first textbook on Point-Based Computer Graphics,
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`published by Elsevier in 2007, and of the 2006 NIH/NSF Visualization Research
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`Challenges Report. I am a senior member of the IEEE Computer Society, and a
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`member of ACM, ACM SIGGRAPH, and the Eurographics Association. I received
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`the IEEE Golden Core Award, the IEEE Meritorious Service Award, and the Petra
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`T. Shattuck Excellence in Teaching Award.
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`16.
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`I have been working as an independent consultant since 2007,
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`specializing in computer graphics, visualization, data science, technical due
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`diligence reviews, and in the provision of expert witness services, particularly patent
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`infringement. My clients range from domestic start-ups to international Fortune 500
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`companies, and include Adobe, Disney Research, Novartis, as well as NVIDIA.
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`I. MATERIALS REVIEWED
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`17.
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`I have reviewed the following materials in forming my opinions:
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`• U.S. Patent No. 7,633,506 (the “’506 Patent”)
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`• File History of U.S. Patent No. 7,633,506. (“File History”)
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`• “Reality Engine Graphics” by Kurt Akeley (“Akeley”)
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`ARM, Ex. 1003, Page 7
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`• U.S. Patent No. 5,808,690 (“Rich”)
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`• U.S. Patent No. 7,102,646 (“Rubinstein”)
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`• U.S. Patent No. 6,697,063 (“Zhu ’063”)
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`• U.S. Patent No. 6,856,320 (“Zhu ’320)
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`• U.S. Patent Application Publication No. US
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`2003/0076320A1 (“Collodi”)
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`• U.S. Patent No. 6,646,639 (“Greene”)
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`• U.S. Patent No. 6,809,732 (“Zatz”)
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`• April 26, 200 Press release describing Nvidia GeForce 2
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`Graphics Chip
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`• January 5, 2001 Article describing Nvidia GeForce 3
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`Graphics Chip
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`18.
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`I have tried my best to list all the materials I considered and reviewed.
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`I may have accidentally left some materials off the above list that I cited in my
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`analysis below. Such materials, if any, should be included in the above list of
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`materials I considered and reviewed. I reserve the right to revise this list.
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`II. UNDERSTANDING OF THE LAW
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`19.
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`I am not a legal expert. In forming my opinions, I have been informed of
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`and applied the legal standards as follows. I understand that the legal standards relating
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`to anticipation and obviousness apply to the ‘506 Patent based on its effective filing
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`ARM, Ex. 1003, Page 8
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`date of November 27, 2002.
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`20.
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`I understand that, during an inter partes review proceeding, patent claims
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`are given their “broadest reasonable interpretation in light of the specification of the
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`patent.” It is my further understanding that the prosecution history is relevant to
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`determining the correct construction of claim terms and that extrinsic evidence also
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`may be relevant to establish the meaning of terms to the extent it is consistent with the
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`specification and prosecution history.
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`21.
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`I understand that anticipation of a claim requires that each and every
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`limitation recited in a claim must be disclosed either expressly or inherently in a single
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`prior art reference. I further understand that, to be considered anticipatory, a written
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`prior art reference must be enabling and describe the applicant’s claimed invention
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`sufficiently to have placed it in possession of a person of ordinary skill in the field of
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`the invention. Thus I further understand that the disclosure of prior art is considered
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`from the perspective of one of ordinary skill in the art.
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`22.
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`I understand that a patent claim is “obvious” and therefore invalid when
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`the differences between the claimed subject matter and the prior art are such that the
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`subject matter as a whole would have been obvious at the time the invention was
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`made to a person having ordinary skill in the art to which the subject matter pertains.
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`23.
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`In making an obviousness determination, I understand that there are
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`several factors to consider: (1) the scope and content of the prior art; (2) the level of
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`ordinary skill in the art at the time the invention was made; (3) the differences
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`ARM, Ex. 1003, Page 9
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`between the claimed invention and the prior art, if any, and (4) objective
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`considerations, if any exist, such as any commercial success, copying, prior failure
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`by others, licenses, longstanding need, and unexpected results.
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`24.
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`I understand that prior art used to show that a claimed invention is
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`obvious must be “analogous art.” Prior art is analogous art to the claimed invention
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`if (1) it is from the same field of endeavor as the claimed invention (even if it
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`addresses a different problem) or (2) the reference is reasonably pertinent to the
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`problem faced by the inventor (even if it is not from the same field of endeavor as
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`the claimed invention).
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`25.
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`I understand that it is improper to engage in hindsight when trying to
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`determine the obviousness of a patent claim. I understand that the obviousness
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`inquiry must be conducted from the standpoint of a person of ordinary skill in the
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`field at the time the claimed invention was made. What is known today, and what is
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`learned from the teachings and disclosures of the patent itself containing the claim
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`under analysis, should not be considered.
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`26.
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`I have been informed that various “secondary considerations”
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`(sometimes referred to as objective indicia of non-obviousness) may support a
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`determination of non-obviousness and that such secondary considerations must be
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`considered as part of an obviousness analysis. I have been informed that secondary
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`considerations of nonobviousness may include:
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`• commercial success of a product due to the merits of the claimed invention;
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`ARM, Ex. 1003, Page 10
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`• a long felt need for the solution provided by the claimed invention;
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`• unsuccessful attempts by others to find the solution provided by
`the claimed invention;
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`• copying of the claimed invention by others;
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`• unexpected and superior results from the claimed invention; and
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`• acceptance by others of the claimed invention as shown by praise
`from others in the field or from the licensing of the claimed
`invention.
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`27.
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`I understand that in order for such “secondary considerations” evidence
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`to be relevant to the obviousness inquiry, there must be a relationship or “nexus”
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`between the advantages and features of the claimed invention and the evidence of
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`secondary considerations.
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`28.
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`I understand that if a claim element is not obvious, then the claims that
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`depend from it are not obvious.
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`III. TECHNOLOGY BACKGROUND
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`29. Graphics processing is an important part of any computer system, and
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`has been for the past several decades. The purpose of a graphics processor is to
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`generate complex shapes and structures to be displayed on a screen. In order to
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`accomplish that purpose, a graphics processor converts a 3D object or scene
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`(comprised of points in 3D space called “vertices” that make up shapes called
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`“primitives”) into a 2D image to be displayed on a computer screen (comprised of
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`“pixels”). Generally, 3D graphics processing starts with creating a mathematical
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`model of each object. The model is then processed through a series of steps, referred
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`ARM, Ex. 1003, Page 11
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`to as a “graphics processing pipeline,” that render the scene as a 2D image on a
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`display:
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`ARM, Ex. 1003, Page 12
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`30.
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`In most cases, 3D objects are conceptualized as a series of primitives
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`(e.g., triangles) that cover the surface of an object, such as a teapot:
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`31. Each point of the primitive is called a “vertex” and each vertex has
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`certain properties, which are represented as data. For example, a vertex includes not
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`just its location, but may also include other information, such as the color of the
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`object and its material properties (e.g., whether it is reflective). A vertex processor
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`performs the steps in the graphics pipeline that transform these vertices from 3D
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`space into 2D space and determines how lighting and other conditions in the 3D
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`scene impact the color of the vertices. The ’506 Patent refers to these operations on
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`vertices as “front-end” operations.
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`ARM, Ex. 1003, Page 14
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`32. After the “front-end” processing, a step called rasterization determines
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`what pixels on the 2D screen are covered by each primitive. At least one “fragment”
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`is generated for each pixel on the screen (as a result, the terms “fragment” and
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`“pixel” are sometimes used interchangeably).
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`33. Rasterization commonly includes the step of “scan conversion,” which
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`involves stepping through the geometry of the primitives to determine which pixels
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`are covered.
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`34. A pixel processor then performs additional operations on the fragments
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`or pixel data, which includes determining the color of each pixel. These operations
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`are commonly called “pixel shading” operations and may involve lighting, texture
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`and bump mapping, translucency and other phenomena. All of this information is
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`gathered together through merging or blending of pixels for the final image to be
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`displayed on a screen.
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`ARM, Ex. 1003, Page 15
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`IV. THE ’506 PATENT
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`35. The ’506 Patent discloses and claims a graphics processing system that
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`includes a front-end and back-end. Ex. 1001 at Abstract and Claim 1. The front-end
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`receives instructions and outputs primitives or combinations of primitives (e.g.
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`triangles, parallelograms, etc.) (i.e., geometry). Id. at Claim 1. The back-end
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`receives the primitives and processes them into a final image comprised of colored
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`pixels. Id. For various embodiments, the claimed invention also includes one or
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`more of the following features:
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`36. Back-end with Parallel Pipelines: The ’506 Patent discloses and claims a
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`system with a back-end comprised of multiple parallel pipelines. Id. These parallel
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`pipelines each process a different portion of the screen in parallel. Id.
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`ARM, Ex. 1003, Page 16
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`Ex. 1001 (’506 Patent) at Figure 3 (parallel pipelines annotated).
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`ARM, Ex. 1003, Page 17
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`Ex. 1001 (’506 Patent) at Figure 5 (parallel pipelines annotated).
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`37. Unified Shader: Each pipeline contains a “unified shader.” Id. At Claim
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`1. The ’506 Patent defines a “unified shader” to mean a shading unit that performs
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`both pixel color shading and texture address shading. A passage describing the
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`unified shader of the ’506 Patent is provided below:
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`ARM, Ex. 1003, Page 18
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`A unified shader reads in rasterized texture addresses and colors,
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`and applies a programmed sequence of instructions. A unified
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`shader is so named because the functions of a traditional color
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`shader and a traditional texture address shader are combined into a
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`single unified shader. The unified shader performs both color
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`shading and texture address shading. The conventional distinction
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`between shading operations (i.e., color texture map and coordinate
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`texture map or color shading operation and texture address
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`operation) is not handled by the use of separate shaders. In this
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`way, any operation, be it for color shading or texture shading, may
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`loop back into the shader and be combined with any other
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`operation.
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`Ex. 1001 (’506 Patent) at 6:49-52 (emphasis added).
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`38. To be clear, the ’506 Patent does not use the term “unified shader” in the
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`way it is commonly used in the industry today. Today, a person of ordinary skill
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`would understand the term “unified shader” to mean a unit that performs
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`computations on both vertex (geometry) data and pixel data. Or, as the ’506 Patent
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`would put it, a shader that performs computations on both “front-end” and “back-
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`end” data. The ’506 Patent, however, clearly does not use the term in this way, and,
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`instead, gives the term a definition unique to the patent. Id. I apply the ’506 Patent’s
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`definition of “unified shader” for purposes of the opinions in this declaration.
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`39. Figure 5 of the ’506 Patent, identifying the unified shader in green is
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`provided below:
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`ARM, Ex. 1003, Page 19
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`Ex. 1001 (’506 Patent) at Figure 5 (annotating Unified Shader)
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`40. Tiling and Setup Unit: The system disclosed and claimed by the ’506
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`Patent also includes a Setup Unit that assists with “Tiling.” Tiling is the process of
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`ARM, Ex. 1003, Page 20
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`breaking the screen into “tiles” and processing each tile separately. Tiling is a well-
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`known practice in the industry and was well-known at the time the ’506 Patent was
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`filed. It was often combined with parallel processing in order to processes multiple
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`pieces of a final image at the same time in order to increase efficiency. To assist in
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`such a process, the ’506 Patent discloses a “Setup Unit” that receives
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`primitives/geometry from the front-end, determines which portion or “tile” of the
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`screen the geometry is located in, and then directs the geometry to be processed by
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`the pipeline responsible for that tile. Ex. 1001 (’506 Patent) at claim Figure 5 from
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`the ’506 Patent id reproduced below, identifying the Setup Unit in green:
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`ARM, Ex. 1003, Page 21
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`Rasterization
`Pipeline A
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`FIGURE &
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`Ex. 1001 (506 Patent) at Figure 5 (annotating Setup Unit)
`Ex. 1001 (’506 Patent) at Figure 5 (annotating Setup Unit)
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`41. Z-buffering: The ’506 Patent discloses that certain embodiments use z-
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`buffering. Z-buffering is the process of comparing the depth values or “z values” of
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`various objects—measured from the screen—to determine which objects are visible
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`and which objects are not visible (because they appear behind other objects from the
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`point of view of the screen). Z-buffering was a common feature for graphics
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`processors at the time the ’506 Patent was filed. In order to facilitate z-buffering,
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`the ’506 Patent discloses that the system contains a “z-buffer logic unit,” which a
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`person of ordinary skill in the art would understand go be a logic unit that performs
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`z-buffering.
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`42. The ’506 Patent discloses that the system may perform three different
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`types of z-buffering: hierarchical z-buffering, early z-buffering, and late z-
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`buffering. Id. at Claims 3-5. As explained in more detail in the context of claim
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`construction, hierarchical z-buffering involves visibility testing at a coarse level, i.e.,
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`coarser than fragment-by-fragment or pixel-by-pixel, early z-buffering is z-
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`buffering that occurs before pixel shading, and late z-buffering is z-buffering that
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`occurs after pixel shading. Hierarchical z-buffering is z-buffering that occurs at a
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`coarse level (e.g., an entire tile) as opposed to the finer fragment-by-fragment level.
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`The various types of z-buffering are identified in Figure 5 from the ’506
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`Patent:
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`23
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`ARM, Ex. 1003, Page 23
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`FIGURE &
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`530
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`515
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`Toother
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`Ex. 1001 (506 Patent) at Figure 5 (annotating z-interfaces)
`Ex. 1001 (’506 Patent) at Figure 5 (annotating z-interfaces)
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`24
`24
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`ARM, Ex. 1003, Page 24
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`ARM, Ex. 1003, Page 24
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`A.
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`Prosecution History of the ’506 Patent
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`43.
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`The ’506 Patent’s application was filed on November 26, 2003. The
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`application included 16 claims directed to graphics systems comprising, among
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`other things, the elements listed in the previous section. Ex. 1002 (’506 Prosecution
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`History). After several office actions, the Examiner allowed several of claims
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`applicant had amended. Ex. 1002 at 39.
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`44.
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`In allowing the claims of the ’506 Patent, the examiner recognized that
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`several prior art references (including Zhu ’063) taught rendering pipeline systems
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`that used screen space tiling and double z-buffering schemes that use scan/z engines
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`as claimed by the ’506 patent. Ex. 1002 at 7/30/2009 Notice of Allowance. The
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`examiner stated, however, that the reviewed references did not disclose parallel
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`pipelines with unified shaders as claimed by the ’506 Patent. Id.
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`45. Nonetheless, as explained below, using parallel pipelines and “unified
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`shaders” (as defined by the ’506 Patent) to perform pixel calculations was well-
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`known and obvious at the time the ’506 Patent was filed.
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`V. LEVEL OF ORDINARY SKILL IN THE ART
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`46. A person of ordinary skill in the field, at the time the ’506 patent was
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`effectively filed, would have had at least a four-year degree in electrical
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`engineering, computer engineering, computer science, or a related field and two
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`years relevant experience in the graphics processing field including developing,
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`designing or programming hardware for graphics processing units.
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`25
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`ARM, Ex. 1003, Page 25
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`VI. PROPOSED CLAIM CONSTRUCTION
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`A. Z-Buffer Logic Unit
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`47. Claims 3-5 require a “Z Buffer Logic Unit.” A person of ordinary skill
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`in the art would understand that the broadest reasonable interpretation of a “Z-Buffer
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`Logic Unit” is “a logic unit that facilitates visibility testing by comparing depth
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`values.”
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`26
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`ARM, Ex. 1003, Page 26
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`48. Z-buffering was well-known and common-place in the art by the time
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`the ’506 Patent was filed. A person of ordinary skill in the art would understand that
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`a “z-buffer” is memory used to store the “z” or “depth” information. They would
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`further understand that a z-buffer logic unit is the logic that uses that “z” or “depth”
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`information to perform visibility testing. This is consistent with the disclosure of the
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`’506 Patent, which states that “Z (depth) information is computed” and “passed to
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`the Z buffer” such that the “Z values are compared against the values stored in the Z
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`buffer at that location.” Ex. 1001 (’506 Patent) at 6:20-23. In other words, the
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`broadest reasonable interpretation of z-buffer logic unit is a logic unit that facilitates
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`z-buffering, i.e., visibility testing done by comparing depth values.
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`B.
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`“Hierarchical Z-Interface”
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`49. Claim 4 requires a “Hierarchical Z-Interface.” A person of ordinary skill
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`in the art would understand that the broadest reasonable interpretation of a
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`“hierarchical z-interface“ to mean “an interface with a z-buffer logic unit that
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`provides for visibility testing at a coarse level, including, for example, for an entire
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`tile or primitive.”
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`50. Hierarchical z-buffering was well-known and common-place by the time
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`the ’506 Patent was filed. A person of ordinary skill in the art would have
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`understood that hierarchical z-buffering involves visibility testing at a coarse level,
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`i.e., coarser than fragment-by-fragment / pixel-by-pixel. The ’506 Patent itself
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`discloses that a hierarchical Z-interface is one that steps through geometry at a
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`27
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`ARM, Ex. 1003, Page 27
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`coarse level, including, for example, the entire portion of a geometry that contributes
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`to a tile. Ex. 1001 (’506 Patent) at 2:67-3:1 (“In one embodiment, each parallel
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`pipeline comprises … a ‘hierarchical-Z’ component to more precisely define the
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`borders of the geometry.”). For example, the hierarchical z-buffer may compare the
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`smallest z-value of such a geometry (i.e., the closes point to the screen) with the
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`largest z-value of the current tile (i.e., the furthest point away). If the object being
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`tested is further away (i.e., behind) the rest of the objects currently being displayed
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`in that tile, it can be discarded in total:
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`A scan converter 540 works in conjunction with Hierarchical Z-
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`interface of Z buffer logic 555 to step through the geometry (e.g.,
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`triangle or parallelogram) within the bounds of the pipeline’s tile
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`pattern. In one embodiment, initial stepping is performed at a
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`coarse level. For each of the coarse level tiles, a minimum (i.e.
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`closest) Z value is computed. This is compared with the farthest Z
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`value for the tile stored in a hierarchical-Z buffer 550. If the
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`compare fails, the tile is rejected.
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`Ex. 1001 (’506 Patent) at 6:2-10 (emphasis added).
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`51. The coarse level z-buffering done by the hierarchical z-interface is in
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`contrast to the finer pixel or fragment level z-buffering done later. Id. at 6:16-18
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`(“The second section of the scan converter 540 works in conjunction with the Early
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`Z-interface… to step through the coarse tile at a fine level.”)
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`C.
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`“Early Z-interface” and “Late Z-interface”
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`28
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`ARM, Ex. 1003, Page 28
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`52. The ’506 Patent also discloses and claims and “early z-interface” and a
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`“late z-interface.” These interfaces coincide with the concepts of “early z-
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`buffering” and “late z-buffering,” which were both well-known and commonplace
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`prior to the filing of the ’506 Patent.
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`53. Early z-buffering is simply z-buffering that is done prior to shading.
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`This is efficient because the graphics processor doesn’t have to spend time shading
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`primitives that will never be seen anyway (e.g., a tree that is behind a building).
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`Accordingly, the broadest reasonable interpretation of this an “early z interface” is
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`“an interface with a z buffer logic unit that provides for visibility testing prior to
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`shading and texturing.”
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`54. Late z-buffering is simply z-buffering that is done after shading. In
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`certain cases early z-buffering does not discard all of the fragments that will be
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`obstructed and they are caught by the late z-buffering. Accordingly, the broadest
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`reasonable interpretation of this a “late z interface” is “an interface with a z buffer
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`logic unit that provides for visibility testing after shading and texturing.”
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`55. These well understood concepts are described in the ’506 Patent:
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`If the current Z buffering mode is set to “early,” each quad is passed
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`to the Z buffer 555 where its Z values are compared against the values
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`stored in the Z buffer at that location…. At this stage, those quads for
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`which none of the covered pixels passed the Z compare test are
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`discarded. The early Z functionality attempts to minimize the amount
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`of work applied by the unified shader and texture unit to quads that
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`29
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`ARM, Ex. 1003, Page 29
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`are not visible.
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`Ex. 1001 (’506 Patent) at 6:22-33 (emphasis added).
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`[i]f the current Z buffering mode is set to “late,” the Z values for the
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`quad are compared against the values stored in the Z buffer at that
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`location…. Although early Z operation is preferred for performance
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`reasons, in certain situations the unified shader might modify the
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`contents of the coverage mask… and in these cases the z buffering
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`mode will need to be set to “late”
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`Id at 6:66-7:9 (describing operations after shading and texturing).
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`30
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`ARM, Ex. 1003, Page 30
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`Ex. 1001 (’506 Patent) at Figure 5 (disclosing
`early z-interface prior to shading and texturing
`and the late z-interface after shading and
`texturing)
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`VII. GROUND 1: OBVIOUSNESS BY AKELEY IN VIEW OF
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`RICH (CLAIMS 1-3 AND 5-9)
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`56.
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`I have reviewed and am familiar with the following prior art references:
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`31
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`ARM, Ex. 1003, Page 31
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`a. “Reality Engine Graphics” authored by K. Akeley
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`(“Akeley”) in 1993 (Ex. 1004);
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`b. U.S. Patent No. 5,808,690 (“Rich”) (Ex. 1005)
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`57.
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`It is my opinion that the combination of Akeley and Rich renders claims
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`1-3 and 5-9 of the ’506 Patent obvious.
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`A. Akeley
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`58.
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`“Reality Engine Graphics” was authored by K. Akeley (“Akeley”) in
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`1993. Ex. 1004 (Akeley). It discloses a prior art graphics processing system with a
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`“geometry board” and multiple “raster memory board.” In the terms of the ’506
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`Patent, a person of ordinary skill in the art would understand the geometry board to
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`be a “front end” and the raster memory boards to make up a “back-end” as
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