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`U5005765027A
`
`[19]
`United States Patent
`5,765,027
`[11] Patent Number:
`[45] Date of Patent: Jun. 9, 1998
`Wang et al.
`
`
`
`[54] NETWORK CONTROLLER WHICH
`ENABLES THE LOCAL PROCESSOR TO
`HAVE GREATER ACCESS 1‘0 AT LEAST
`ONE MEMORY DEVICE THAN THE HOST
`COMPUTER IN RESPONSE TO A CONTROL
`SIGNAL
`
`[‘75]
`
`Inventors: Jerry Borjeng Wang. Lake Forest:
`Robert Vernon Harper. Torrance:
`Chili-Chung Shi. Ycrba Linda. all of
`Calif.
`
`['13] Assignee: Toshiba American Information
`Systems, Inc.. Irvine. Calif.
`
`[21] Appl. No.: 310,293
`
`[22} Filed:
`
`Sep. 2.6, 199d
`
`[51]
`Int. Cl.‘5 ..... s.. (3065' 13100
`
`[52] US. CL ........... 395.1860; 3950.00.45; 395000.59:
`3951882; 3951836
`34WSZS.05; 36069;
`Field of Search
`3951293. 500. 29?. 200.43. 200.59. 860.
`882: 38013; 4391'61
`
`[58]
`
`[56]
`
`4.503.933
`4.303.485
`4.8 11 .205
`4,899,306
`
`Rderences Cited
`ILLS. PATENT DOCURIENTS
`211985 Gian ......
`340(82505
`211939 Rypinsh
`
`345502
`3.0989 Normingtm
`.
`
`(List motioned on next page.)
`OTHER PUBLICATIONS
`
`“Wireless Data Networks and the Mobile Workforce". Ira
`Brodslcy. Telecommunications. Dec. 1990. vol. 24. No. 12.13.
`31.
`"File Engineering Monthly Index". May 1992. p. 27?.
`abstract of Cordless LANs Hit the Ainvaves. Ira Brodslcy.
`Telecomnnnicafions. Sep. 1991. v. 25. No. 9. 5p.
`
`“Wireless LANs Duel in Europe“. Fszaheth Heichler. Elec-
`tronic News. Apr. 25. 1994. p. 30.
`“PCMCLA Cards on Deck; Personal Computer Memory
`Card International Association Cards at Comdefoall [993
`Trade Show." Tammi Herbert. PC Week. Nov. 15. 1993. v.
`10. No. 5. p. 108.
`“Surge in Popularity Spans New Ideas for Wireless LANS."
`Morris Edwards. Commicat‘ion News. v. 31. No. 8. p. 55.
`Aug. 1994.
`
`Primary Examiner-whom C. Lee
`Assistant When—Po C. Huang
`Alfonse}; Agent, or Fina—Banner fl: Witcofi’. Ltd.
`[57]
`ABSTRACT
`
`An application specific integrated circuit (ASICVfield pro
`grarnmable gate array (FPGA) which is a component of a
`wireless LAN controller including a local prooessor and a
`memory enables the controller to interface with both PCM-
`CIAm and ATT“ host computer systems. The ASIC’FPGA
`enables communication between a radio frequency commu-
`nication module. a local processor. and the host computer.
`The ASICIFPGA also includes a throttle feature that
`decreases the access of the host computer in comparison to
`access of the local processor in order to enable the local
`processor to rapidly generate an acknowledge signal as
`required by various RF LAN Specifications. During opera~
`tion of the controller. data to be transmitted by the host
`computer onto the network is written by the host to an
`SRAM via the ASICFF'PGA. and the host commands the
`local processor via the ASICJ'FPGA to forward the trans-
`mitted data to the RF communication module. Under the
`control of the ASIO'FPGA. the local processor then for-
`wards the transmit data from the SRAM to the RF commu-
`nication module. When data is received from the RF com-
`munication module. the local processor. under the control of
`the ASICLFPGA. receives the data and stores the received
`data in the SRAM. The received data is then forwarded to
`the host computer via the ASICIFPGA.
`
`23 Claims, 1.6 Drawing Sheets
`
`
`'1le ”ICE
`
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`|PR2018—01067
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`

`5,765,027
`
`Page 2
`
`
`
`4.932.470
`5.043.938
`5.121.482
`5.159.684
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`US. Patent
`
`Jun. 9, 1993
`
`Sheet 1 of 16
`
`5,765,027
`
`FIG.1
`
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`US. Patent
`
`Jun. 9, 1993
`
`Sheet 2 of 16
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`5,765,027
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`US. Patent
`
`Jun. 9, 1998
`
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`US. Patent
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`Jun. 9, 1998
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`US. Patent
`
`Jun. 9, 1998
`
`Sheet 5 of 16
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`5,765,027
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`US. Patent
`
`Jun. 9, 1993
`
`Sheet 6 of 16
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`US. Patent
`
`Jun. 9, 1998
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`5,765,027
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`US. Patent
`
`Jun. 9, 1993
`
`Sheet 8 of 16
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`US. Patent
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`Jun. 9, 1998
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`US. Patent
`
`Jun. 9, 1998
`
`Sheet 10 of 16
`
`5,765,027
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`
`Jun. 9, 1998
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`US. Patent
`
`Jun. 9, 1998
`
`Sheet 12 of 16
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`

`US. Patent
`
`Jun. 9, 1998
`
`Sheet 13 of16
`
`5,765,027
`
`FIG. 12
`
`SOURCE
`
`SIGNALS A0 THROUGH A25 ARE 26 ADDRESS BUS LINES CAPABLE OF
`ADDRESSING 64 MEGABYTES OF MEMORY ON THE CARD. A25 IS THE MOST
`
`HOST
`
`SIGNIFICANT BIT.
`
`IN THE PCMCIA CARD. ONLY AD THROUGH AI 2 ARE USED.
`
`:I: D
`3
`,_D2::
`
`SIGNALS DO THROUGH DIS CONSTITUTE THE BI-DIRECTIONAL DATA BUS.
`OT 5 IS THE MOST SIGNIFICANT BIT.
`
`
`
`All-A25
`
`Ian—ms
`
`GE U, GET!
`
`HOST
`
`THE CE I! AND CEZI' ARE CARD-ENABLE SIGNALS. THE CEI.I ENABLES EYEN-
`NUMBERED-ADDRESS BYTES, CEL’ ENABLES ODD-NUMBERED-ADDRESS
`BYTES.
`
`THE OE! LINE ISTHE ACTIYE-LOW. INPUT SIGNAL USED TO GATE MEMORY
`READ DATA INTO THE PCMCIA CARD.
`
`THE WEI INPUT SIGNAL IS USED FOR STROBING MEMORY WRITE DATA INTO
`THE PCMCIA CARD.
`
`
`THE CDT! AND CD2! SIGNALS PROYIDE FOR PROPER DETECTION OF CARD
`INSERTION. THE CDT! AND CD2}F SIGNALS ARE CONNECTED TO GROUND
`INTE RNALLY ON THE PCMCIA CARD.
`
`
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`
`WHEN THE REG! SIGNAL IS ACTIYE. ACCESS IS UNITED TO ATTRIBUTE
`MEMORY AND ITO SPACE. REG! SIGNAL IS KEPT INACTIYE FOR ALL COMMON
`MEMORY ACCESS.
`
`THE RESET SIGNAL CLEARS THE CARD CONFIGURATION OPTION REGISTER
`THUS PLACING A CARD IN UNCONFIGURED STATE. THE HOST WILL ACTIIIATE
`THIS SIGNAL AT THE BEGINNING OF ANY CARD INSERTION.
`
`
`THE IAIAIT SIGNAL IS ASSERTED BY A CARD TO DELAY COMPLETION OF THE
`MEMORY-ACCESS OR ITO-ACCESS CYCLE IN PROGRESS.
`
`THE INTERRUPT REQUEST (IREOII SIGNAL IS ASSERTED TO INDICATE THE
`
`NEED OF THE HOST SOFTWARE SERVICE.
`IT'S AVAILABLE ONLY WHEN THE
`CARD AND THE INTERFACE ARE CONFIGURED FOR THE IIO INTERFACE. THE
`IREO! CAN BE EITHER LEYEL OR PULSE MODE.
`
`
`
`
`
`
`
`
`
`THE IORD! SIGNAL IS MADE ACTIYE TO READ DATA FROM THE CARD'S ITO
`SPACE. THE REG! SIGNAL AND AT LEAST ONE OF CEI.I OR CEIIf MUSTALSO
`BE ACTIIIE FOR THE ITO TRANSFER TO TAKE PLACE.
`
`THE IOWA! SIGNAL IS MADE ACTIYE TO WRITE DATA TO THE CARD'S II'O
`SPACE. THE REG! SIGNAL AND AT LEAST ON OF CEII OR CEII MUST ALSO BE
`ACTIYE FOR THE ITO TRANSFER TO TAIIE PLACE.
`
`
`
`YCC, GND
`
`HOST
`
`LOCAL
`
`HOST
`
`
`
`
`
`THE INPACIU SIGNAL IS ASSEIITED WHEN THE PCMCIA CARD'S ITO SPACE IS
`SELECTED. THIS SIGNAL IS USED TO CONTROL THE ENABLE OF ANY INPUT
`DATA BUFFER.
`
`TWO YCC AND FOUR GND PINS ARE EMPLOYED TO REDUCE THE IMPEDANCE
`BETWEEN THE PCMCIA CARD AND THE SYSTEM.
`
`
`
`
`Toshiba_Apricorn 1019-0015
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`

`US. Patent
`
`Jun. 9, 1993
`
`Sheet 14 of 16
`
`5,765,027
`
`FIG. 13
`
`
`ITEIE- SDIIIIEE
`
`DESE III PTION
`
`
`
`SAD-SAID
`
`HOST
`
`SIGIIALS SADTHIIouGII SAID AIIE 20 ADDIIESS BUS LIIIES EAPADLE
`or ADDRESSING I HEGADTTES DE IIEHDIIII ON THE (ADD. SAT 9 IS
`THE HDST SIGHITITAIIT BIT.
`
`SDD-SDIS
`
`HOST!
`[DUAL
`
`SIGNALS SDD TH ROUGH SD I5 CONSTITUTE THE Bl-DIHELTIDNAL DATA
`BUS. DIS IS THE MOST SIGHITICflINT BIT.
`
`UIlT-LAZS
`
`HOST
`
`SIGNALS LAIT THROUGH U23 HIRE T UNLHTEHED ADDRESS BUS
`LINES.
`
`HDST
`
`ADDIIESS EHADIE TDII Ho ADDEESS DECODING. WHEN HIGH, ALL
`ISA DDS ADDRESS. DATA AIID EDIIHAIID LIIIES AIIE CONTROLLED BY
`THE DIIIEET HEIIDIIT AEEESS (DNA).
`
`BALE
`
`HOST
`
`BUS ADDIIESS LATCH EIIADLE IIIDIEATES WHEN THE HDST [PU HAS A
`TALID ADDIIESS (III THE ISA DDS.
`
`mm“)?
`
`THE HEADS SIGIIAL To THE IIDSTTD IIIDIEATE THAT THE AT CARD IS
`IIEADT To HIIIITE or IIEAD DATA TEDII THE HGST TED.
`
`IORDI
`HOST
`m HOST
`
`THIS IS THE #0 HEAD SIG HILL
`THIS IS THE I10 WRITE SIGIIAL.
`
`THUS-4, T,
`9-l2, IS
`
`THE IIITEAIIIIET DEDHEST (IRQ) SIGNALS AIIE ASSEIITED T0 IIIDIEATE
`THE NEED OF THE HOST SOFTWARE SEIWICE.
`
`THE IIEIIDIIT IA-DIT {HIP SELECT EDIT A ITS-BIT.
`IIEIIDIIII ETELE.
`"mm"
`
`SBHEI’ m SISTEII BllS HIGH EIIADLE IIIDIEATESA ID-BITTBANSFER OF DATA
`m THIS IS THE IIEIIGIIT IIEAD SIGNAL.
`
`SIIEHw
`HOST
`THIS IS THE IIEIIDIIT wIIITE SIGIIAL.
`
`I WAIT STATE
`
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`RESET
`
`H05,
`
`THE IIESET SIGHAL IS USED TD HESET DII IHITIALIEE THE AT EAED
`LOGIES AETEII EDIHEE UP.
`
`+5I.I_ GND
`
`HOST
`
`
`
`TWO HEC AND FOUR GND PINS ILHE EMPLOYED T0 REDUEE THE
` IMPEDANCE BETWEEN THE HIT CHILD AND THE SYSTEM.
`
`
`
`Toshiba_Apricorn 1019-0016
`Toshiba_Apricorn 1019-0016
`IPR2018-01067
`|PR2018—01067
`
`

`

`US. Patent
`
`Jun. 9, 1998
`
`Sheet 15 of 16
`
`5,765,027
`
`FIG.
`
`
`
`HHI_CLII
`
`QQ
`
`IN." THIS5NH:cLocIIISPARTorMODEHNANAGEMENTINTERFACE(MIN). THIs
`
`
`SIGNAL GOES INTO FPGA TO CLOCK THE DATA OUT THROUGH THE MHI_SIO
`LINES.
`
`SERIALIZED ITO DATA IS PART OT MODEM MANAGEMENT INTERFACE
`
`(MMI). THE SIGNAL IS ACTIVE LOW AND, WHEN IN COMBINATION WITH
`MMLCLII. USED FOR SENDING COMMAND TO AND RECEIVING STATUS FROM
`THE RT MODULE.
`
`
`
`
`RH
`LOCAL
`
`LOCAL
`
`MODEM MANAGEMENT ENABLE (I‘IME) IS AN ACTIVE HIGH SIGNAL. WHEN
`ACTIVE I'IME WILL ENABLE THE MODEM MANAGEMENT INTERFACE (MMI).
`THIS SIGNAL IS GENERATED AUTOMATICALLY RV TI’GAI'ASIC DURING MMI
`REGISTER ACCESS.
`IT IS DISABLED DURING LOOPBACN TEST MODE.
`
`THIS IS A 2 MN: CLOCK TOR RT TRANSMITTER THIS SIGNAL IS CONNECTED
`TO BOTH TCLKI AND TCLN2 OF 63302 PORT I AND FORTE.
`
`THIS IS A 2 MN: CLOCII TOR RF RECEIVER THIS SIGNAL IS CONNECTED
`TO IIOTH RCLIII AND RCLAI OT 68301 PORT I AND PORT 2
`
`M TRANSMTTDATA(TAD)ISANacmeHIGHSIGNAL THE LOCALPROCESSOR
`
`WILL CLOCK THE DATA OUT VIA THIS LINE USING TACI' WHEN CTSI' IS ACTIVE.
`THIS SIGNAL IS THE OR OUTPUT OT TNDI! OR TALIZII OF 63302.
`
`RECEIVE DATA (RAD))IS AN ACTIVE HIGH SIGNAL. THE LOCAL PROCESSOR
`WILL CLOCII DATA IN VIA THIS LINE USING RXCI' WHEN CRSI' IS ACTIVE. THIS
`SIGNAL IS CONNECTED TO BOTH RADI AND RAD] OT 63302.
`
`RTSI'
`
`REQUEST TO SEND (RTSI) IS AN ACTIVE LOW SIGNAL. THIS SIGNAL IS THE
`OR OUTPUT OT RTSII“ OR RTSII' DE 68301.
`
`
`
`
`
`
`
`
`
`
`
`CLEAR TO SEND (CTSI) IS AN ACTIVE LOW SIGNAL THIS SIGNAL IS
`MONITORED IIV TPGAIASIC TO CREATE CTSSOZ! WHICH IS THEN
`CONNECTED TO BOTH CTSII‘ AND USE! DE 68302 AT PORT I AND PORT I
`
`CARRIER SENSE ACTIVE LOW. CRSI‘ BECOMES ACTIVE WHEN THE RT MODULE
`
`IS RECEIVING A HESSAGE WITH CORRECT NETWORK ID. CRSI‘ IS GENERATED
`
`ON THE RISING EDGE OF RAC_. THIS SIGNAL IS INVERTED BEFORE
`
`CONNECTED TO PB III OT 68302 TO GENERATE INTERRUPT. THIS SIGNAL
`ALSO CONNECTS TO BOTH CDI! AND CDII‘ OT 68301 PORT I AND PORT 2
`
`
`
`
`
`COLLISION DETECT (CDT!) ISAN ACTIVE LOW SIGNAL THIS SIGNAL
`CONNECTED TO FBI I OT 68302.
`
`LOCAL
`
`THIS ACTIVE HIGH SIGNAL WHEN ASSERTED WILL PUT THE RT MODULE INTO
`SLEEP MODE TO CONSERVE POWER THIS SIGNAL IS CONNECTED TO PA IO OT
`6830!
`
`m m LOCAL
`
`THIS ACTIVE HIGH SIGNAL WHEN ASSERTED wILL PUT THE RF INTO RESET
`STATE THIS SIGNAL Is CONTROLLED THROUGH PAI I or $3302.
`
`LOCAL
`++ISI
`m 5.39
`
`
`+|2VANDI2VAIIE UNIV REQUIRED TomPIN RF MODULE THE HILL IS
`REQUIREDFORBOTHTVPESOTRFHODULES
`
`
`
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`
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`
`
`
`Toshiba_Apricorn 1019-0017
`Toshiba_Apricorn 1019-0017
`IPR2018-01067
`|PR2018—01067
`
`

`

`US. Patent
`
`Jun. 9, 1993
`
`Sheet 16 of 16
`
`5,765,027
`
`FIG. 15
`
`IDENTIFICATION DATA TRANSMITTED EROI‘I HOST
`COMPUTER TO CONTROLLER VIA HOST INTERFAEE
`TO IDENTIFY THE ARCHITECTURE OF THE HOST
`
`NETWORK COI'II‘IUHIEATION MODULE
`
`DATA TO BE TRANSMITTED ONTO NETWORK
`WRITTEN TO CONTROLLER BY THE HOST
`COI‘IPUTE R
`
`DATA TO BE TRANSMITTED IS FORWARDEO
`FROM THE CONTROLLER TO A NETWORK
`COMMUNICATION MODULE VIA A NETWORK
`INTERFAEE
`
`DATA TRANSMITTED ONTO THE NETWORK BY THE
`
`ISOI
`
`ISO!
`
`I503
`
`|504
`
`Toshiba_Apricorn 1019-0018
`Toshiba_Apricorn 1019-0018
`IPR2018-01067
`|PR2018—01067
`
`

`

`1
`NETWORK CONTROLLER WHICH
`ENABLE-S THE LOCAL PROCESSOR TO
`HAVE GREATER ACCESS TO AT LEAST
`ONE MEMORY DEVICE THAN THE HOST
`COMPUTER IN RESPONSE TO A CONTROL
`SIGNAL
`
`BACKGROUND OF THE INVENTION
`
`The present invention relates to an integrated circuit/field-
`programmable gate array for use in a wireless radio fre—
`quency local area network (LAN) controller which enables
`a PCMCIAT“ or AT“ host computer to communicate within
`the LAN.
`To meet the demand for new and eflicient methods of
`communication. many types of local area networks (LANs)
`have been developed such as optical LANs (e.g.. FDDI
`networks) and LANS in which users communicate via
`modern over telephone lines (e.g.. Echoplex netwarks).
`However. the increasing pOpularity of portable personal
`computers. also known as laptop or notebook computers. has
`created a demand for LANs that can be accessed from these
`portable computers without requiring the computer to be in
`some way hardwired to the network. thus allowing for fully
`portable network access. As a result. wireless LANs such as
`radio frequency (RF) LANS have been developed in which
`packets of information including address information and
`data are transmitted wirelessly using radio frequency tech-
`nology.
`The increasing popularity of parable personal computers
`has also fueled the need for small.
`lightweight. portable
`expansion devices which take the form of memory cards. As
`a result. many manufacturers began to produce memory
`cards of various sizes and capabilities. creating the need for
`an industry standard
`The Personal Computer Memory Card International Asso-
`ciation (PCMCIA) was founded in 1989 and created die first
`standard (1.0) for memory cards. Since that time. die PCM—
`CIA has also released standard 2.1 which includes support
`not only for memory. but also for H0 devices. comprehen-
`sive software architecture. and other changes. In general.
`PCMCM cards include RAM. Flash memory and other
`types of ROM. U0 devices include voice. data and fax
`modems: network interface cards; and wireless communi-
`cations. There are three sizes of PCMCIA cards: type I
`which are used for memory devices: type 11 which are used
`for modems. LANs. etc.: and type III which are used for
`devices such as ATA hard drives whose miniaturization
`technology is not as advanced.
`However. while PCMCIA technology is rapidly
`advancing. a large number of desktop computers are still in
`use. These computers have an [BMm AT'H-type architeo
`ture and use a standard EAbus that is diflerent from the bus
`used in PCMCIA systems.
`As a result of the mixture of computer systems that are
`widely used. it is desirable to create softwardfirmwate that
`is capable of interfacing with both PCMCIA and AT sys-
`tems. Thus. it is desirable to create a controller that enables
`either type of host system to access a wireless local area
`network.
`
`35
`
`45
`
`55
`
`A number of controllers for accessing local area networks
`are known. For example. U.S. Pat. 5.237.659 discloses a
`gateway device which provides a link between a host
`module and an optical fiber token-ring network. (e.g.. an
`FDDI network). The gateway device includes a controller
`that manages the transfer of frames between the host module
`
`65
`
`5 365.027
`
`2
`and the network and having a control bus that carries control
`blocks coming to and from the host module and control
`characters of the FDDI frames coming to or from the storage
`memory. The controller interprets the control blocks to form
`contml characters and forms control blocks from control
`characters.
`Also. U.S. Pat. No. 5.159.634 discloses a data commu-
`nication interface integrated circuit with data-echoing and
`nonechoing communication modes which converts parallel
`data of a host module to serial data for transmission. e.g. in
`an Echoplex protocol tr RS—232 protocol communication
`system via a telephone line. and translates received serial
`data into parzdlel data readable by the host module.
`However. these references do not disclose a controller for
`interfacing with a radio frequency local area network that is
`compatible with host computers having a portable or a
`desktop (e.g.. a PCMCIA or AT) architecture.
`SWARY OF THE INVENTION
`
`10
`
`15
`
`The present invention relates to an apparatus and method
`for an application—specific integrated circuitlfield-
`programmable gate array (ASICJF'PGA) that will enable
`both host computers having a PCMCIA architecture and host
`computers having an AT architecture to communicate in a
`wireless radio frequency local area network. Embodiments
`of the present invention fun-thei- relate to a design for a
`controller which enables a host computer hating either a
`PCMCLAT“ or an AT“ ardritccture to communicate in a
`wireless local area network.
`
`Awirelcss LAN controller. according to embodiments of
`the present invention. includes a host interface for interfac-
`ing with a host computer having a desktop or a portable
`computer architccmre; a network interface for interfacing
`with a network communication module; a local processor;
`and a first communication circuit for enabling communica-
`tion between the host computer. the network interface and
`the looal processor. The first communication circuu includes
`a cirwit for communicating with the host computer via the
`host interface. a second conununicau'on circuit for commu-
`nicating with the network communication module via the
`network interface. a third communication circuit for com-
`municating with the local txocesscr. a desktop interpretation
`circuit for receiving and interpreting information from the
`host computer when the host computer has a desktop
`ardtitccture. and a portable interpretation circuit for receiv—
`ing and interpreting infonnalion from the host computer
`when the host computer has a portable architecuue.
`In another embodiment of the controller according to the
`present invention. the local processor is located within the
`first communication circuit.
`invention
`An ASICIFPGA according to the present
`includes a circuit for receiving control signals andfor data
`from a host computer having a desktop computer architec—
`ture via a host interface; a circuit for receiving control
`signals and/or data from a host computer having a portable
`computer ardtitccnire via the host interface: a n'ansmitterfor
`transmitting control signals and/or data to the host computa'
`via the host interface; a circuit for receiving control signals
`andlor data from a network communication module via a
`module interface: a transmitter for transmitting control sig-
`nals anchor data to the network communication module via
`the module interface; a circuit for receiving control signals
`andz‘or data from a local processor: and a transmitter for
`transmitting control signals audlor data to the local proces-
`30:.
`
`Another ASICJFPGA according to the present invention
`includes a circuit for receiving control signals andJ'or data
`
`Toshiba_Apricorn 1019-0019
`Toshiba_Apricorn 1019-0019
`IPR2018-01067
`|PR2018—01067
`
`

`

`5.765.027
`
`3
`from a host computu' via a host interface: a transmitter for
`transmitting control signals andlor data to the host computer
`via the host interface: a circuit for receiving control signals
`andior data from a network communication module via a
`network interface; a transmitter for transmitting control
`signals andJor data to the network communication module
`via the network interface; a cirwit for receiving control
`signals andlor data from a local processor; a transmitter for
`transmitting control signals andr‘or data to the local [tones-
`sor; and a throttle circuit for enabiing the local processor to
`have greater access to a memory within the controller than
`the host computa' in response to a throttle signal.
`A method of enabling communication between a host
`computer having a deskmp or a portable architecture and a
`local area network via a connotler according to the present
`invention includes the steps of transmitting identification
`data from a host computer via a host interface to a controller.
`the identification data identifying the architecture of the host
`computer. and tltcreby configuring the controller; writing
`data to be tr'anstnittcdfrom the host oornptter onto a network
`to the coon-otter: forwarding the data to be transmitted from
`the controller to a network communication module via a
`network interface: and transmitting the data to be n-ansmit-
`ted onto the network.
`The foregoing and other features. aspects. and advantages
`of the present invention will become more apparent from the
`following detailed description when read in conjunction
`with the accompanying drawings.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 provides a system level block diagram of the
`controller or card.
`including an ASIC'JFPGA. a local
`trocessor. a host interface. an RF interface. an SRAM and
`a FLASH ROM.
`FIG. 2 provides a functional block diagram of the ASIC!
`H‘GA according to the present invention.
`FIG. 3 provides a circuit schematic of the host decode
`circuit of the ASICI'FPGA acornding to the present inven-
`tion.
`
`10
`
`15
`
`25
`
`35
`
`FIG. 4 Fovides a circuit schematic of the first part of the
`mode register in the ASIO’FPGA according to the present
`invention.
`
`FIG. 5 provides a circuit schematic of the second part of
`the mode register used in the ASICIFPGA according to the
`present invention.
`FIG. 6 provides a circuit schematic of the first part of the
`timing control circuit and the bus request used in the
`ASICJFPGA according to the present invention.
`FIG. 7 provides a circuit schematic of a first part of the
`throttle circuit and a second part ofthe timing conn-ol circuit
`of the ASICIFPGA according to the present invention.
`FIG. 8 provides a circuit schematic of a second part of the
`throttle circuit in the ASICI'FPGA according to the present
`invention.
`
`45
`
`SS
`
`FIG. 9 provides a circuit schematic of a second part of the
`address compare register and a third part of the throttle
`circuit used in the ASICIFPGA according to the present
`invention.
`
`FIG. 10 provides a schematic of a first part of the address
`compare register used in the ASIOFPGA according to the
`present invention.
`FIG. 11 provides a schematic of the reset circuit used in
`the ASICJ'FPGA according to the present invention.
`FIG. 12 provides a diagram of the PCMCINhost interface
`signals.
`
`4
`FIG. 13 provides a diagram of the KUhost
`signals.
`FIG. 14 provides a diagram of the RF interface signals.
`FIG. 15 illustrates a method contemplated by embodi-
`ments of the present invention.
`DETAILED DESCRIPTION
`
`interface
`
`The data communication interface integrated circuit for a
`Wireless local area network (IAN) controller and a wireless
`LAN controller according to the present invention will now
`be described with reference to the drawings.
`As illustrated in FIG. 1. a wireless local area network
`controller is shown as an adapter card 100 which can be for
`a desktop or a portable host computer. In the embodiments
`described below. adapter card 100 is particularly (though not
`exclusively) contemplated to be either a PCMCIA card or an
`KI' card. having a number of components. The controlla'
`100 comprises an application-specific integrated circuit
`{ASICVfield-programrmble gate array (FPGA) 101. a local
`processor 102. a host interface 103. a radio frequency
`interface 104. a FLASH ROM 105. and an SRAM 106.
`These components comprise the network controller 100
`which enables a host computu 110 to interface with a
`wireless local area network. for example. a radio frequency
`local area network. The host interface 103 interfaces with
`the host computer 110. The radio frequency (RF) interface
`104 interfaces with an RF communication module 120.
`The ASICJFPGA 101 is designed to include all control
`glue circuits on the controller 100. The SRAM 106 is a
`readfwrite communication buffer accessible by both the host
`and local processor. The FLASH ROM 105 is a program
`memory accessible by both the host computer 110 and the
`local prooessor 102. Writing to the FLASH ROM 105 may
`only be accomplished dtn'ing a special program mode con-
`trolled by a mode register within ASICJ'FPGA 101: however.
`reading from the FLASH ROM 105 is allowed at any time
`by both the host 110 and the local processor 102.
`Briefly. operation of the wireless local area network
`controller according to the present invention is as follows.
`When data is to be transmitted by a host computer 1.10 on to
`the network. the host computer 110 writes the transmit data
`to the SRAM 106 via host interface 103 and ASICJ'FPGA
`101 and commands the local processor 102 via the ASIC!
`FPGA 101 to forward the transmitted data to the RF com-
`munication module 120 Via the RF interface 104. Under the
`control of the ASICIFPGA 101. the local processor 102 then
`forwards the n-ansmit data Erorn the SRAM 106 through the
`local processor 102 to the RF interface 104 and then to the
`RF communication module 120. When data is received from
`the RFcommunication module In. the local processor 102
`receives the data from the RF interface 104 and stores the
`received data in the SRAM 106. The [coal processor 102
`also generates an acknowledge signal which is transmitted
`onto the network by the RF communication module 120 via
`RFintcrfncc 104.111: received data is then forwarded to the
`host computer 110 via the ASICJ'FPGA 101.
`As a result. the ASICIFPGA 101 enables communication
`between the host computer 110. the local processor 102 and
`the RF communication module 120. The ASIOFPGA 101
`enables transmission of control signals between these three
`components and controls host computer 110 and local pro-
`cessor 102 access to the SW 106 and the FLASH ROM
`105.
`
`The controller 100 according to the present invention
`includes both PCMCLA and AT fort-n factra-s. When the
`controller 100 is coupled to a PCMCIA host computer 110.
`
`Toshiba_Apricorn 1019-0020
`Toshiba_Apricorn 1019-0020
`IPR2018-01067
`|PR2018—01067
`
`

`

`5.765.027
`
`S
`the controller 100 is referred to as a PCMCIA card. When
`the controller 100 is coupled to anAT host computer 110. the
`controller 100 is referred to as an AT card.
`
`According to one embodiment of the present invention.
`the PCMCIA card is designed to comply with the PCMCIA 5
`2.1 type 11 standard in a physical dimension of 85.6
`mrmd4.0 mmx5.0 mm. This card is designed to work with
`a radio frequency communication module 120 which is
`connected through a 15-wire serial interface cable. One
`possible RF communication module 120 is a PCMCIA 915
`RF Modern manufactured by NCR Corporation of Dayton.
`Ohio. The PCMCIA card is also coupled to notebook
`computers through a standard 68-pin interface.
`According to another embodiment of the present
`invention. the AT card has the same functionality as the
`PCMCIA card except that the host interface is a standard
`16-bit ISA interface. The AT card may be coupled to an RF
`communication module 120. for example. an NCR WAVE-
`LANT" modem. through a lS-wire serial interface cable or
`through a 34-pin wire interface for 2.4 GHz.
`The components of the controller according to the present
`invention will now be described in detail.
`
`15
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`10
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`25
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`35
`
`45
`
`55
`
`FIG. 2 provides a functional block diagram of the A510
`FPGA 101 shown in FIG. 1. The function block diagram
`shown in FIG. 2 is drawn to illustrate the host interface 103
`between the ASICI’FPGA 101 and host computer 110 on the
`left-hand side of the figure and the interface between the
`ASICIFPGA 101 and the local procmsor 102. the memories
`(the SRAM 106 and FLASH ROM 105) and the RF interface
`104 on the right-hand side of the figure. As shown in FIG.
`2. the ASICJ'FPGA 101 contains a control module 201 which
`converts memory access control signals from the host com—
`puter 1.10 format to the local processor 102. format. Bus
`request module 202 generates bus arbitration handshahing
`signals When the host comth 110 is accessing the SRAM
`106 andior FLASH ROM 105. Bus request module 202 also
`assigns higher priority to the local processor 102 in response
`to a throttle (TIMI) signal 203 generated by the address
`compare module 215. The throttle feature will be discussed
`in detail below.
`
`The control module 201 and bus request module 202 also
`include a timing control circuit which syndrronizes accessto
`the FLASH ROM 105 and SRAM 106 by the host 110 and
`the local processor 102. both of which access these local
`memories. The timing control circuit as shown in FIG. 6
`provides an optimal design which provides timing for the
`host to access the looal memories 105 and 106. This timing
`control circuit operates once a bus request from the host 11.
`has been granted by bus request module 201
`The relationship of the throttle 203.
`the bus request
`module 202 and the timing control cimut of FIG. 6 is as
`folloWs. The throttle 203 affects the bus request module 202
`by preventing the bus request module 202 from granting bus
`requests from the host 110 during periods when the local
`Inocessor 102 has primity access to the local memories.
`Once the bus request module 202 has granted a bus request
`from the host 110. the timing control circuit then provides
`the timing for the host 110 to access the local memtn'ies 105
`and 106.
`
`The decode module 20:! decodes addreSS signals in host
`format for register access and memory access by the host
`110. The decode module 204 tells the ASICJ'FPGA 101 what
`the host 110 wants to access. for example the SW 106.
`the FLASH ROM 1.05. or a register in the AS