5 343,482
`
`73
`
`STAPLE-S 127:0
`lli‘ZStTllll’ilflN
`
`D
`1
`2
`3
`4
`5
`ti
`?
`
`8
`9
`
`‘ll
`12
`r3
`l4
`15
`lb
`1?
`18
`19
`20
`21
`'3',
`
`:3
`
`25
`26
`27
`38
`29
`311
`
`31
`
`33—
`127
`
`Lever 802 status signal for slot 363 (PlN[0]t
`lever 802 status signal for slot 36h [PINI 1])
`Levcr 802 status signal for slot 36c (Pl'Nfllt
`lever 803 status signal for slot 36d [PINE];
`[ever no: status signal to: slot 36E (PINHIJ
`Lever 802 status signal for slol 36f (P[N[5]t
`Reserved for lever tilt: status signal
`to: additional hot-plug
`slot
`Reserved for lever 802 status signal for additional hotvplug
`slot
`PRSN'l‘Erfi signal for slot 36:: [PINIG];
`PRSNT2# signal for slot 36b (PINITll
`PRSNT2#
`gnal [01' slot 36c (PIMSD
`PRSN‘Dfi signal for slot 36d [PINIQD
`PRSNTM signal for slot 36c (PINUDD
`PRSNI‘3# signal for slot 36f (PtNIt 1]]
`Reserved for PRSNW}, signal for additional hot-plug slot 36
`Reserved for PRS’.\T#2 signal for additional hot-plug slot 35
`PRSNTIH signal [or $101 36!! [PIN] l3])
`PRSNI'W signal [or slot 36b [PINIJSIJ
`PRSN'l‘lrl signal for slot 36c [PINIHJJ
`PRSNTM signal for slot 36d (Pl-NIH];
`PRSNI‘HF signal for slot 36:: [PINIIBJJ
`PRSNTM signal for slot 36f (PL-“[17],!
`Reserved for PRSE\T1# signal l'or additional hot—plug slot 36
`Reserved for PRSNI‘H! signal for additional hot-plug slot 36
`Power fault status for slot 36a (PlN[18]t
`Power [nult slams for slot 36b (Plh‘llgll
`Pow-c: [null statua for slot 365; (PINIEUIJ
`Power [nult status for slot 36d (FINISH!
`Power fault status for slot 3-6: (I’lNTESh
`Power fault status for slot 361‘ {Pith-123]]
`Reserved for power Fault status for additional hot-plug
`slot 36
`Reserved for power fault status for additional hot-plug
`slot 36
`Status signals that do not cause interrupt requests when their
`status changes
`
`As shown in FIGS. 2 and 30, when the $10 circuit 50
`asserts. or drives low, a register load signal CSlL_0_. the
`shill register 52 latches the status signals STATUS [127:32]
`and the shift register 82 latches the status signals STATUS
`[31:0]. When the $10 Circuit 50 negates, or drives high, the
`signal CSIL.
`.0.
`., both the registers 52 and 82 serially shift
`their data to the 510 circuit 50 on the positive edge of a clock
`signal CSlC_0 furnished by the $10 circuit 50. The clock
`signal CSIC 0 is synchronized to and one fourth the
`frequency of the PC! clock signal CLK.
`As shown in FIG. 29, for purposes of monitoring, or
`scanning, the status signals STATUS [31:0]. the 810 circuit
`50 uses a thirty-two bit
`interrupt register 800 whose hit
`positions correspond to the signals STA'IUS [31:0]. The S10
`circuit 50 updates the bits of the interrupt register 800 to
`equal the corresponding status signah; STATUS [31:0] that
`have been dcbounecd. as further described below. Two status
`signaLs S’l'A'l‘US [7:6] are reserved for additional hot-plug
`slots 36, and the seventh and eighth most significant bits of
`the interrupt register 80!] are also reserved for the additional
`slots 36, The interrupt register 800 is part of a register logic
`block 808 of the $10 circuit 50 which is coupled to the PC]
`bus 32.
`Serial scan input logic 804 of the $10 circuit 50 sequen—
`tially scans, or monitors, the status signals S'I‘AI'US [31:0].
`least significant signal first. for changes, as indicated by
`transitions in their logical voltage levels. If the status of one
`or more of the status signals S'I‘ATUS [5:0] associated with
`the levers 802 changes. the serial scan input logic 804 enters
`a slow scan mode such that the status signals S‘l'ATUS [5:0]
`
`74
`are scanned thirty-two times within a predetermined
`dcbouncc time interval. If one or more ol‘ the status signals
`STATUS [5:0] changes,
`the serial scan input
`logic 804
`updates the interrupt register 800 {and asserts the serial
`interrupt signal Sl_lNTR#) if the changed status signal
`STATUS [5:0] remains at the same logical voltage level for
`at least a predetermined debouncc time interval. The serial
`scan input logic 804 is coupled to programmable timers 806
`which generate and indicate the end of the dcbounce delay
`interval initiated by the serial scan logic 804. Requiring the
`status to remain stable for
`the debounce time interval
`minimizes the inadvertent powering down of one of the
`bot—plug slots 36 due to a false value (i.e.. a “glitch"}
`indicated by one of the status signals STATUS [5:0]. When
`all of the status signals S'IAI'US [5:0] remain at the same
`logical voltage level [or at least the debounce time interval,
`the serial scan input logic 804 then proceeds to once again
`scan all thirty-two status signals S'l'A'lUS [31:0] in the faster
`scan mode.
`
`[1‘ the serial scan input logic 804 detects a change in one
`of the status signals S'l‘ATUS [31:6], the serial scan input
`logic 804 instructs the timers 806 to measure another
`dcbounce delay interval, subsequently assure;
`the serial
`interrupt signal SI__ INTRll, updates the interrupt register
`800 with the signals S'l'ALl‘US [31:6] that have changed, and
`ignores further changes in the status signals S'I'A'I'US [31:6]
`until the debouncc time interval expires After expiration of
`the debounce time interval, the scrial scan input logic 804
`proceeds to recognize changes in the thirty-two status sig-
`nals S'l'A'l'US [31:0].
`When the serial interrupt signal Sl._lNTR# is asserted,
`the CPU 14 subsequently reads the interrupt register 800,
`determines which (may be more than one) status signals
`STATUS [31:0] caused the interrupt, and deasserts the serial
`interrupt signal Sl
`INTI-til by writing a "l” to the bit or hits
`ol‘ the interrupt register 800 that have changed.
`The CPU 14 may selectively mask interrupt requests
`caused by the status signals S‘l‘A’l‘US [31:0] by writing a "1“
`to a corresponding bit of a thirty—twu bit intcrmpl mask
`register 810. The CPU 14 can also Selectively read any byte
`of the status signals STATUS [47:0] by writing a byte
`number of the selected byte to a serial input byte register
`812, The $10 circuit 5|] then transfers the desired byte into
`a serial data register 815.
`For example, to read the third byte (byte number two) of
`the status signals STATUS [23:16], thc CPU 14 writes a "2"
`to the serial input byte register 812. The serial scan input
`logic 804 then serially shifts byte two of the status signals
`STATUS [23:16] into the serial data register 815. A busy
`status bit BS of the serial input byte register 812 is equal to
`"1" when the CPU 14 initially writes the desired byte
`number to the aerial input byte register 812. The bit BS is
`cleared by the 810 circuit 50 after the requested byte has
`been shifted into the serial data register 815.
`The CPU 14 can power up one of the slots 36 by writing
`a "1." lo a corresponding bit of a slot enable register 181'?I and
`disable the slot 36 by writing a "0" to this bit. Furthermore,
`the CPU 14 can reset one ofthc slots 36 by writing a “l" to
`a corresponding bit of a slot rcsct register 819. The contents
`of the slot enable 817 and slot reset 819 registers are
`represented by signals 51 .OT_EN [5:01] and SI .0T_RST_
`[5:0], respectively.
`To initiate the request indicated by the slot enable 817 and
`reset 819 registers. the CPU 14 writes a “l” to an SD bit of
`control register 814. After the SO bit is asserted (which
`asserts, or drives high, a G0_UPDA’1'13 signal),
`the $10
`
`10
`
`15
`
`2|)
`
`30
`
`411
`
`$5
`
`50
`
`55
`
`fit]
`
`as
`
`Toshiba_Apricorn 1010-0165
`Toshiba_Apricorn 1010-0165
`IPR2018-01067
`lPR2018-01067
`
`

`

`5 ,943 ,482
`
`Ill
`
`15
`
`2|)
`
`75
`circuit 50 initiates and controls the required power down
`andlor power up sequences.
`The serial scan input
`logic 804 is coupled to ONIOFF
`control logic 820 which controls the power up and power
`down sequences. The ONIOFF control logic 820 furnishes
`the signals BUSEN#[5:0], Cl-KJlN#[5:0], RS'I'#[5:0] and
`PWREN [5:0] to serial output logic 824.
`Each power up or power down sequence involves four
`shill phases during which another step of the power down or
`power up sequence is performed. During each shift phase.
`the ONIOFF control logic 820 instructs the serial output
`logic 824 to combine the control signals BUSENslIZSfl],
`CLKEN#[5:0], RS’I'#[5:0] and PWREN [5:0]; latch these
`signals; and serially furnish these signals (via a serial data
`signal CSOD_0) to the serial
`input of an output shift
`register 00. At end of each shift phase, the ONi‘OFF control
`logic 820 instructs the shift register 80 to update the control
`signaLs POUT [35:12].
`The ONIOI-‘l: control logic 820 is also interfaced to the
`register logic 808 and Light Emitting Diode (LED) control
`logic 822. The LED control logic 122 controls the onion"
`status of the six Hills 54, which visually indicate whether
`the corresponding levers 802 are latched or unlatched. The
`LED: 54 can be programmed to blink when tumed on
`through LED control registers (not shown) of the register *
`logic 808.
`As shown in FIG. 31A. the serial scan input logic 804
`includes a scan state machine 840 which controls the scan-
`ning of the status signals STATUS [31:0] for changes and
`controls the shifting of a selected byte of the status signals
`S’I‘AI'US [47:0] into the serial input byte register 815.
`The scan state machine 840 is clocked on the negative
`edge of a clock signal DIVZCLK, which is synchronized to
`a PCI clock signal CLK and one half of the frequency of the
`PCI clock signal CLK. The load and clock signals, CSlL_ :‘
`o_ and CSIC_O, respectively, are furnished by the scan
`state machine 840. The clock signal. when enabled.
`is
`synchronized to the clock signal (381C 0.
`A bittbytc counter 841. through a thirty-two bit signal
`BlT_AC'l'IVE [31:0].
`indicates which hit of the status
`signals S’IIA’I‘US [31:0] is currently represented by the serial
`data signal NEW_CSID. The asserted bit of the signal
`BlT_ACTlVE [31:0] has the same bit position as the status
`signal STATUS [31 :0] represented by the data signal NEW
`CSID.
`
`3t)
`
`:10
`
`4:1
`
`The counter 841 also furnishes a three bit signal BIT [2:0]
`which represents which hit of the current byte of the status
`signals S'I‘A'I'US [31:0] is currently being scanned by the
`scan state machine 840. The counter 841 is clocked on the
`negative edge of a signal SIlll"f_ENAl3LE. The outputs of
`the counter 841 are reset, or cleared, when the output of an
`AND gate 842, connected to the clear input of the counter
`841, is negated.
`'lhe scan state machine 840 furnishes a signal SCAN
`lN IDLE which when asserted, or high. indicates that the
`scan state machine 840 is in an IDLE state and not currently
`scanning any of the status signals S‘I‘A‘I‘US [127:0]. The
`signal SCAN__IN_IDI_E is deasserted othenvise.
`'lhe signal SCI-\N_lN_lDl..LT is furnished to one input of
`the AND gate 842. The other input of the AN lJ gate 842 is
`connected to the output of an (JR gate 843. One input of the
`OR gate 843 receives an inverted I-lOl.I)__OFF signal, and
`the other input of the OR gate 843 receives a signal
`GE'I'I'ING_BY'I'E.
`The signal HOI_D__ OFF, when assencd, or driven high.
`indicates that a change in one of the status signals S'l‘A'l‘US
`
`50
`
`55
`
`{ill
`
`{15
`
`76
`[5:0] has been detected, and the serial scan logic 304 has
`entered the slow scan mode. In the slow scan mode, the
`serial scan input logic 804 waits for a predetermined slow
`scan interval before traversing the status signals STATUS
`[31:0] again. The serial scan input
`logic 804 couan the
`number of times the serial scan signals S'I'ALI'US [5:0] are
`scanned during the slow scan mode and uses this count to
`determine when one of the status signal STATUS [5:0] has
`remain unchanged for the debounce delay interval, as further
`described below.
`Therefore, when the scan state machine 840 is in the
`IDLE state and the either the ”OLD. OFF signal is does—
`serted or the scan state machine 840 is reading in a selected
`byte (selected by the CPU 14) of the status signals STATUS
`[47:0]. all outputs ofthe counter 841 are cleared, or set equal
`to zero.
`
`The signal SI III'-'l‘__ENA]3Ll:L is furnished by the output
`of an AND gate 844. One input of the AND gate 844
`receives the clock signal CSIC 0. Another input of the
`AND gate 844 receives a signal DIVZCLKR. The signal
`DIVZCLK# is asserted. or driven low, on the negative edge
`ofthe signal CLKDW4. The third input ofthe AND gate 844
`receives a signal SCAN IN PROGRESS, which when
`asserted, or driven high, indicates that the scan state machine
`840 is currently scanning the status signals STATUS [127:0],
`and the signal SCAN _IN_ PROGRESS is. deasserled oth—
`crwisc.
`
`Therefore. when the scan state machine 840 is not shifting
`in the status signals S'I‘A'I‘US [127:0], the counter 841 is
`disabled. Furthermore. when enabled.
`the counter 841 is
`clocked on the negative edge of the clock signal DIVZCLK.
`The interrupt
`register 800 receives input signals
`[NPR REG [31.0] at
`its corresponding thirty-two
`1)
`inputs. The load enable inputs of the interrupt register 800
`receive corresponding load enable signals UPDATE [R0
`[31:0]. 'lhe interrupt register 800 is clocked on the positive
`edge of the PCI clock signal CLK.
`For purposes of keeping track of the status signals STA—
`TUS [5:0] after each scan, a multi-bit. D-type flip-flop 836
`furnishes status signals SCAN _SW [5:0]. 'lhe clear input of
`the tlip~flop 836 receives the reset signal RST, and the
`flip-flop 836 is clocked on the positive edge of the clock
`signal (TI .K. 'lhe input of the [lip-flop S36 is connected to the
`output of a multi-bil OR gale 850 which has one input
`connected to the output of a multi-bit AND gate 846 and one
`input connected to the output of a mulli—bil AND gate 847.
`One input of the AND gate 846 receives six bit enable
`signals BIT ENABLE [5:0] (described below) and the
`other input of the AND gate 846 receives the serial data
`signal NEW_CSID. One input of the AND gate 847
`receives inverted bit enable signals BIT ENABLE [5:0],
`and the other input of the AN D gate 847 receives the signals
`SCAN_SW [5:0].
`Only one of the bit enable signals Bl’f_.ENABLE [5:0] is
`asserted at one time (when the scan state machine 840 is
`scanning), and the asserted bit indicates which one of the
`corresponding status signals STATUS [31:0] is represented
`by the signal NEW (ISID. Thus. when the scan state
`machine 840 is scanning, on every positive edge of the clock
`signal CLK, the signals SCAN_SW [5:0] are updated.
`The bit enable signals BI'I‘ ENABLE [3110] are far-
`nished by the output of a multi-bit multiplexer 832 that
`receives the bio; lilT_AC.TlVE [31:0] at iLs one input. The
`zero input of the multiplexer 832 receives a thirty-two bit
`signal
`indicative of logic zero. The select
`input of the
`multiplexer 832 receives the signal SIlIl"l‘_[3NA]3Ll.Z.
`
`Toshiba_Apricorn 1010-0166
`Toshiba_Apricorn 1010-0166
`IPR2018-01067
`|PR2018—01067
`
`

`

`5 ,943 ,482
`
`ID
`
`15
`
`2t)
`
`3t)
`
`77
`For purposes of detecting a change in the status signals
`STATUS [5:0], a mulli—hit, Exclusive 0r (XOR) gate 848
`furnishes switch change signals SW CI-IG [5:0]. When one
`of the signals SW_CHG [5:0] is asserted, or high,
`the
`logical voltage of the corresponding status signal S’l'A’l'US
`[5:0] changed during successive scans. One input of the
`XOR gate 848 is connected to the input of the flip-flop 836.
`and the other input of the XOR gate 848 receives the signals
`SCAN_SW [5:0].
`As shown in FIG. 31 D, for purposes of indicating when
`the logical voltage level of a selected status signal STATUS
`[5:0] has remained at the logical voltage level for at least the
`duration of the dcbounce delay interval, the scan input logic
`804 has six signaLs LSWI'I‘CH [5:0]. The non-inverting
`input
`01‘ a D-type llip-tlop 900 furnishes the signal
`LSWI'I'CII
`[5] at
`its non-inverting output. The signal
`{SWITCH [S] is asserted, or driven high, to indicate the
`above—described condition and deasscrtet] otherwise. The
`flip-flop 900 is clocked on the positive edge of the clock
`signal CLK, and the clear input of the flip-flop 900 receives
`the RST signal.
`The input of the flip-flop 900 is connected to the output of
`a multiplexer 902 which furnishes a D .LSWI‘I'Cl-l
`[5]
`signal. The select input of the multiplexer 902 is connected
`to the output of an AND gate 903 that receives a MAX5 v
`signal and a SCAN END signal. 'lhe SCAN END signal,
`when asserted, indicates the scan state machine 840 has
`completed the current scan.
`[-‘ive signals (MAXS, MAX4,
`MAXS, MAX2, MAXI AND MAXO) indicate whether the
`corresponding status signal STATUS [5], STATUS [d], S'I‘Am
`TUS [3], STATUS [2], S'I‘A’I'US [l], or S’l'A'I‘US [0].
`respectively, has remained at the same logical voltage level
`for a least the duration of the debounce time interval. The
`zero input of the multiplexer 902 receives the signal
`LSWITCI-l [5], and the one input of the multiplexer 902 _~
`receives the signal SCAN_SW [5]. The signal SCAN_
`END is furnished by the output of an AND gale 851 (FIG.
`313). The AND gate 851 receives a signal STOP __SCAN
`and a signal SCAN_DONE. The signal STOI’_SCAN is
`asserted, or driven high, when conditions for ending the
`scanning by the scan state machine 840 are present, as
`further described below. The signal SCAN_END is a puLsed
`(for one cycle of the CLK signal) version of the STOP.
`SCAN signal. The signals LSWl'l'Cl-l [4]-LSWI'I'CI-l [0]
`and D_I.SWITCII [4]~D_I.SWITCII [0] are generated in a
`similar
`fashion from the respective SCAN SW [4]-
`SCAN SW [0] signals and the respective signals
`MAX4—MAXO.
`For purposes of updating the logical voltage level of the
`status signals S'I‘A'I'US [31:6] as these signals are scanned
`in, a multi-bit D-type [lip-llop 905 (FIG. 31D) furnishes
`twenty-six signals SCAN_NSW [31:6], One of the signals
`SCAN_ __NSW [31:6] is asserted, or driven high, to indicate
`this condition and deasserted otherwise. The [lip—flop 905 is
`clocked on the positive edge of the clock signal CLK, and
`the clear input of the flip-flop 905 receives the RST signal.
`The input of the llip-Ilop 905 is connected to the output of
`a multi-hit multiplexer 906.1'he select input of the multi-
`plexer 906 receives an inverted CI-IECK SWI’I‘Cll. ONLY
`signal. The CHECK_SWITCH_ONI.Y signal is aswrlcd,
`or driven high, when the scan state machine 840 is only
`scanning the status signals S’l‘A’l'US [5:0] or status signals
`S'I‘A’l'US [127:32] (i.e., ignoring changes in the signals
`STATUS [3115]) and deasserted otherwise. The xero input of
`the multiplexer 906 receives the signals SCAN NSW
`[31:6], and the one input ol‘the multiplexer 906 is connected
`to the output ofa multi-bit OR gate 90?. One input of the OR
`
`40
`
`4:1
`
`50
`
`55
`
`fit]
`
`{15
`
`78
`gate 907 is connected to the output of a multi-hit AND gate
`908, and the other input of the OR gate 907 is connected to
`the output of a multi-bit AND gate 872.
`One input of the AND gate 908 receives the signals
`BI'l‘_ENABLE [31:6]. The other input of the AND gate 908
`is connected to the output of a rnulti—hit multiplexer 909. II"
`the NEW CSlD signal is asserted, or high, the multiplexer
`909 furnishes a twenty-six hit signal equal to “h3Fl~‘FFI~'F."
`Otherwise, the multiplexer furnishes a twenty-six bit signal
`equal to "0." One input of the AND gate 872 is connected
`to the inverted output of the AND gate 908, and the other
`input of the AND gate 872 receives the signals SCAN_
`NSW [31:6].
`For purposes of storing the logical voltage level of the
`status signals STATUS [31:6] after every scan, a multi-bit,
`D—type flip—[lop 871 furnishes twenty—six signaLs I.NON_
`SW [31:6]. One of the signals LNON SW [31:6] is
`asserted, or driven high,
`to indicate this condition and
`deasserted otherwise. The flip-[lop 871 is clocked on the
`positive edge of the clock signal CLK, and the clear input of
`the flip—llop 871 receives the RST signal.
`The input ofthe flip—flop 871 is connected to the output of
`a multivhit multiplexer 870 which furnishes the signals
`D LNON SW [31:6]. The select input of the multiplexer
`870 receives the signal SCAN_END. The yero input of the
`mu Iliplexer 870 receives the signals LNON_SW [31:6], and
`the one input of the multiplexer 807 receives the signals
`SCAN_NSW [31:6].
`As shown in FIG. SIB, for purfxises of generating the
`MAXI), MAXI, MAX2, MAX3, MAX4, and MAXS
`signals,
`the serial
`input
`logic 804 includes six counters
`83lo—f, respectively, of common design 83]. Each counter
`83] is initialized (to a predetermined count value) when an
`AND gate 892 asserts, or drives high, its output. For the
`counter 3311:, the AND gate 892 receives the signal BIT__
`ENABLE [0], the signal SW (3116 [O] and an inverted
`signal QUICK_FII_TER. The signal QUICK_ FILTER,
`when asserted. or high. can he used to circumvent
`the
`dehourtce time interval. The QUICK _l«‘ILTl:‘.R signal
`is
`normally deasserted, or low. The clock input of the counter
`831 is connected to the output of an AND gate 893. For the
`counter 8310,
`the AND gate 893 receives the BIT
`ENABLE [a] signal, the inverted sw __CHG [0] signal, the
`inverted GIJ'I'l'ING_._llY’l'li signal. and the inverted MAXO
`signal. Therefore, for the counter 8310, once the logical
`voltage of the status signal STATUS [0] changes, each time
`the serial scan logic 804 scans the status signal STATUS [0].
`the counter 831:? is incremented. When the counter 831a
`reaches iLs maximum value, the signal MAXO is asserted
`which indicates the debounce time interval has elapsed. If
`the logical voltage of the status signal STATUS [0] changes
`during the count, the counter 831.” is reinitialized and the
`count begins again. The other counters 831b—f function in a
`similar fashion for their corresponding status signals STA-
`TUS [5:1].
`The llOI.D_0FF signal. when asserted, instructs one of
`the timers 806 to measure a predetermined slow scan
`interval which puts the serial scan state machine 840 in the
`slow scan mode. When the timer 806 Completes measuring
`this delay interval, the timer 806 asserLs, or drives high, a
`FTR__TIMEOUT signal which is otherwise dcasserted, or
`negated. The product of this slow scan interval and the
`number of counts for the counter 831 to reach its maximum
`value is equal to the dehounce time interval (8 ms).
`The HOLD____()FF signal is furnished by the output ol’a JK
`flip-[lop 885. The llip-llop 885 is clocked on the positive
`
`Toshiba_Apricorn 1010-0167
`Toshiba_Apricorn 1010-0167
`IPR2018-01067
`|PR2018—01067
`
`

`

`5 ,943 ,482
`
`10
`
`15
`
`2t)
`
`3t)
`
`79
`edge of the CLK signal, and the clear input of the flip-flop
`885 receives the RST signal. The J input is connected to the
`output of an AND gate 883, and the K input isconnected to
`the output of an AND gate 884. One input of the AND gate
`884 is connected to the output of a .IK-lype flip-flop 896, and
`the other input of the AND gate 883 receives the SCAN_
`END signal. One input of the AND gate 884 is connected to
`the inverted output of the AND gate 883, one input of the
`AND gate 884 receives the FTR_TIMEOUT signal. and
`another input ol'the AND gate 884 receives a SCAN IN
`tDLE signal, which is asserted when the scan state machine
`840 is in its IDLE state, as further described below.
`The flip-llop 895 is clocked on the positive edge of the
`CLK signal, and the clear input of the flip-flop 895 receives
`the RST signal. The J input is connected to the output of a
`NAN D gate 894 which receives the MAXO. MAXl, MAXZ,
`MAX3, MAX4 and MAXS signals. The K input
`is con-
`nected to the output of an AND gate 826 which is connected
`to the inverted .1 input of the flip-flop 895 and receives an
`inverted SCAN_IN_PROGRESS signal which is asserted
`when the scan state machine 840 is scanning the status
`signals STATUS [31:0].
`.
`For purposes of generating the CHECK. _.SW[‘l'(.‘ll.
`ONLY signal.
`the serial scan input
`logic 804 includes a
`JK—type flip—llop 864 which furnishes the CHECK
`SWt’I'CH ONLY signal at its non-inverting output and is
`clocked on the positive edge of the CLK signal. 'the clear
`input of the flip-[lip 864 receives the RST signal, and the .1
`input of the [lip-flop 864 receives a DEBOUNCE signal.
`which when asserted. or driven high. indicates that one of
`the logical voltage level of one or more of the status signals
`S‘I‘A’I'US [31:6] has changed. The K input of the flip-flop
`864 is connected to the output ol‘a AND gate 865. One input
`of the AND gate 865 receives the inverted DEBOUNCE
`signal. and one input of the AND gate 865 receives the _~
`SCAN_IN_IDLE signal.
`As shown in FIG. 31C. the dehounce signal DEBOUNCE
`is furnished by the non-inverting output of a JK-type flip-
`flop 860. The flip-flop 860 is clocked by the positive edge of
`the clock signal CLK. and the clear input ofthe [lipvllop 860
`receives the reset signal RST. The .1 input of the flip-flop 860
`receives a signal (IHANGE_ON_INPUT signal. The
`CIIANGE_ON_1NPUT signal is asserted, or driven high,
`when a change in one of the status signals S'I‘A'I‘US [31:6]
`is detected at the end of a scan by the serial input logic 804
`and deasserted othenvise. The K input is connected to the
`output of an AND gate 861 which receives a
`DB_TIMEOUT signal at one of its inputs. The other input
`ol'the AND gate 861 receives the inverted CI [ANGIE ON
`INPUT signal. The DB TI MEOU't' signal is asserted by the
`timers 106 for one cycle of the CLK signal when the
`dehounce time delay (initiated by the assertion of the
`DEBOUNCE signal) has expired. The assertion of the
`DB_TIMEOUT signal negates the DEBOUNCE signal on
`the next positive edge of the CLK signal.
`The CHANGE ON INPUT signal is furnished by the
`non-inverting output of a JK-type llip-llop 866 which is
`clocked on the positive edge of the CLK signal. The clear
`input of the flip-flop receives the RST signal. The .1 input of
`the flip—flop 866 is connected to the output of an AND gate
`869 which receives the SCAN. END signal, and another
`input ofthe AND gate 869 is connected to the output of an
`OR gate 867. The OR gate 357 logically Otts all ofa set of
`NSW_CIlG [31:6] signals. The hit positions of the signals
`NSW (THG [31:6] correspond to the bit positions of the
`status signals STATUS [31:6] and indicate, by their
`assertion, whether the corresponding status signal S'I‘A'I‘US
`
`40
`
`4:1
`
`50
`
`55
`
`(it!
`
`{15
`
`80
`[31:6] has changed after the last scan. The AND gate 869
`further receives the SCAN_END signal. The K input of the
`flip-flop 866 is connected to the output of an AND gate 868
`which receives the inverted SCAN_IN_PROGRESS signal
`and the inverted output of the AND gate 869. The signals
`NSW CHG [31:6] are furnished by the output of a multi-
`hil, XOR gate 862 which receives the signals D_LNON_
`SW [31:6] and I..NON_SW [31:6].
`The non-inverting output of a rnulIi-bit D-Iype [lip-flop
`912 furnishes bits SI DAI‘A [7:0] for the serial data register
`815. The clear input of the flip-llop 912 receives the signal
`RST, and the flip—flop 912 is clocked on the positive edge of
`the CLK signal. ’Ihe signal
`input of the flip-flop 912 is
`connected to the output of a multi—hit t'nultipICXer 916. The
`select input of the multiplexer 916 is connected to the output
`of an AND gate 914, and the zero input of the multiplexer
`916 receives the bits S]_DATA [7:0]. The AND gate 914
`receives the signals GETTING_I3YTE and SIIIFT_
`ENABLE.
`'l‘hus, when the serial scan logic 804 is not
`shifting in a requested byte of the status signals STAJUS
`[47:0], the values of the bits SI_DA‘I‘A [7:0] are preserved.
`The one input of the multiplexer 916 is connected to the
`output of a multi-bit multiplexer 910. The one input of the
`multiplexer 910 is connected to the output ofa multi—hit OR
`gate 9.11. and the zero input ol'the multiplexer is connected
`to the output of a multi-bil AND gate 915. The select input
`of the multiplexer 910 receives the signal NEW_CSI D.
`One input of the AND gate 915 receives the hits
`SI . DAJ‘A[7'.0], and an inverting input of the AND gate 915
`is connected to the output of a 3x8 decoder 913. The decoder
`913 receives the signal BIT [2:0]. One input of the OR gate
`911 receives the hits SI DATA [7:0], and the other input of
`the OR gate 911 receives the output of the decoder 913.
`The serial input logic 804 furnishes five signals RST_
`SWITCH [5:0] (corresponding to the hit positions of the
`status signals S'l‘A’l'US [5:0] to the ONtOl-‘F control logic
`820 which indicate. by their assertion. whether the corre—
`sponding slot 36a—f should be powered down. The ONIOFF
`control logic 820 indicates when the slot 36 (indicated by the
`RST_SWI'I‘CH [5:0] signaLs) has subsequently been pow-
`ered down by the subsequent assertion olone of five signals
`CLR SWITCH [5:0] signals whose hit positions corre-
`spond to the signaLs RST __SW[TC'H [5:0]. After receiving
`the indication that the slot 36 has been powered down. the
`serial logic 804 then deasserts the corresponding RST_
`SWITCH [5:0] signal.
`The signals RST_SWITCII [5:0] are Furnished hy the
`non-inverting output of a multi-bit, D-type Flip-flop 891
`(FIG. 311-1). The clear input of the liip-llop 891 receives the
`reset signal RST. and the flip-flop 891 is clocked on the
`positive edge of the clock signal (.TLK. The input of the
`flip-flop 891 is connected to the output of a multi-bit OR
`gate 857 which has one input connected to the output or a
`multi-hit AND gate 859 and one input connected to the
`output of a multi-hit AND gate 855. One input of the AND
`gate 859 is connected to the output of a multiplexer 853. and
`the other input of the AND gate 859 receives latched slot
`enable signals ISLOT EN [5:0] which indicate, by their
`assertion. whether the corresponding slot 36n—-f is powered
`up. One input of the AND gate 855 receives the signals
`CI_R__SWITCH_[5:0] signals. Another input 01‘ the AND
`gate 855 receives the signals RST_ SWITCH [5:0]. Another
`input of the AND gate 855 is connected to the inverted
`output of the multiplexer 853.
`The zero input of the multiplexer 853 receives a six hit
`signal indicative of zero. 'Ihe one input of the multiplexer
`
`Toshiba_Apricorn 1010-0168
`Toshiba_Apricorn 1010-0168
`IPR2018-01067
`|PR2018-01067
`
`

`

`5 ,943 ,482
`
`10
`
`15
`
`2|)
`
`81
`853 is connected to the output of a multi-hit AND gate 849.
`One input of the AND gate 849 receives the signals
`D LSWI'I'Cl-I [5:0], and the other input of the AND gate
`849 receives the inverted signals I._SWl'l‘(_‘H [5:0]. The
`select input of the multiplexer 853 receives the SCAN
`END signal.
`the
`For purposes of generating the SI_INTR# signal.
`serial scan logic 804 includes a D-Iype [lip-flop 882 which
`furnishes the serial intermpt signal SI_INTR# at its invert—
`ing output. The lIip—llnp 882 is clocked on the positive edge
`of the CLK signal, and the clear input of the tlip-llip 832
`receives the RST signal. The input of the llip—llop 882 is
`connected to the output of an OR gate 881 which receives
`thirty [\vo pending interrupt signals PENDING _lRQ [31:0],
`which indicate, by their assertion, or driving high, whether
`an interrupt
`is pending for the corresponding one of the
`status signals STATUS [31:0]. The signais PENDING_IRQ
`[31:0] are otherwise dcasserted.
`As shown in FIG. 31E, a multi-bit, D-type flip-flop 979
`furnishes the signals PENDINGJRQ [31:0] at
`iLs non—
`invening output. The flip-flop 979 is clocked on the positive
`edge of the signal CLK signal and receives the signal RST
`at its clear input. The input ol'the [lip-[lop 979 is connected
`to the output of a multi-hit AND gate 981 which receives
`inverted interrupt mask signals [NTR MASK [31:0] at one
`input. The signals IN'I‘R___MASK [31:0] are indicative of '
`corresponding bit of the interrupt mask register 810. The
`other input of the AND gate 981 is connected to the output
`ol'a multi—hil OR gate 835. One input ol'the OR gate 835 is
`connected to the output of a multi-bit AND gate 862, and the
`other input of the OR gate 835 is connected to the output of
`a multivbit AND gate 834.
`The AND gate 862 receives inverted PENDING .lRQ
`[31:0] signals and signals SET I’lRQ [31:0]. The signals
`SET_PIRO [3120] are asserted to indicate an interrupt
`request should be generated for the corresponding one of the
`status signals STATUS [31:0]. Therefore.
`the signals
`l’ENDING_IRQ [31:0] are updated with the signals SET_
`PIRQ [31:0] it‘ not masked by the signals lN'I'R_MASK
`[31:0].
`The AND gate 834 receives the signals PENDING_IRQ
`[31:0],
`inverted signals SET_PIRO [31:0] and inverted
`WR INTR REG [31:0] signals. The signals WP.
`INTR
`REG [31:0] indicate the write data furnished by the CPU 14
`to the interrupt register 800. The CPU clears an interrupt by
`writing a "l" to the corresponding bit of the interrupt register
`800. Therefore, if this occurs, and no new interrupt requests
`are indicated for the corresponding one of the status signals
`STA'I'US [31:0],
`the corresponding one of the signals
`PENDING_IRQ [31:0] is cleared.
`The signals SET Pl R0 [31 :0] are furnished by the output
`ofa multi-bitAND gate 839. One input oftlte AND gate 839
`receives the signals UPDAI‘E_IRQ [31:0]. The other input
`ol'the AND gate 839 is connected to the output of a rnulti—bit
`XOR gate 837. One input of the XOR gate 837 receives the
`signals D INTR REG [31:0], the other input 01‘ the XOR
`gate 837 receives the signals INTR_REG [31:0]. Therefore,
`when the bits of the interrupt