`U5005922060A
`
`United States Patent
`
`[19]
`
`{11] Patent Number:
`
`5,922,060
`
`Goodrum
`
`[45] Date of Patent:
`
`Jul. 13, 1999
`
`[54] EXPANSION CARI) INSER’I‘ION ANI)
`REMUVAL
`
`[TS]
`
`Inventor: Alan L. Goodrum. Tomball. Tex.
`
`[T3] Assignee: Compaq Computer Corporation,
`Houston, Tex.
`
`5,6802% 1111199? Carey cl al.
`FOREIGN PATENT DOCUMENTS
`
`361.1115
`
`n 24] gas
`U 254 #56
`28 511-1411
`34 09 1121
`WO 93145459
`
`European Pal. on, _
`tttrl98‘t
`European Pat. OE.
`.
`IIIQBS
`strut") Germany.
`9.11935 Germany .
`Silt”?! WIPO.
`
`[2]] App]. No.: 031i775,133
`
`OTHER PUBLICATIONS
`
`[22
`[51]
`
`58
`
`I
`
`l
`
`[56]
`
`Film]:
`Int Cl6
`
`Dec. 31’ [9%
`
`(1MP 13m
`
`Maintenance St Service Guide. Compaq Deskpm XI. Series
`nfl’crson31C0mputch:1113-3-1815-34fl‘0mpaq Cornputcr
`
`1‘ Id
`'e
`
`f S 11
`eurc
`
` 19—1,.”82, 283
`39?fl9}3(]5
`
`0
`
`.
`.
`.
`1101 Plug Receptacle Actuated Mechanical latch. [BM Tech—
`nical D1sclosure Bulletin, vol. 34, No. 6. Nov. 1991, pp.
`363—364.
`
`Refwerm,5 Cited
`'
`US. PATENT DOCUMENTS
`
`3,763,974 [WWI-'3 Donovan. Jr. at al.
`” 31711111
`3.853.339 1211934 Goodman et a1.
`.
`_ 339,75
`
`4.t1?9,44l'l
`331938 ()hnuma el al.
`361.1424
`4.559.456 [21"1985 Yamamoto ct :11.
`
`. 3071456
`4.5963]?
`(131986
`[aGrcCo et al.
`. 2011150
`
`4.628.413
`12’1986 Speraw ........
`3614413
`
`3fi41‘JlK1
`4.335.337
`53'1989 He rrig cl Eli.
`4.8?S.867 111.11%!)
`[-100
`439““
`364,514
`4,909,145?
`3II‘JUI McNally-clzit
`
`5313.431
`311991
`[ntsdahL
`. 361.1415
`5,010,426
`431991 Krenz
`"BNWIUI
`
`5,101,930
`31993 Brockway cl
`:11.
`.. 200535
`3953313
`5,247,619
`931993 Mutoh ct a1.
`
`5,309,031
`51'1904 Stewart ct al.
`_ 30W)
`5.3lU,998
`534994 Okuno
`..
`1'
`.
`
`$320”;
`5.313.482
`5,'1994 Bujtas .
`5.317.483
`51"1994 Swindler _
`36118111
`
`$380,567
`”1995 Lien et a1.
`..
`.. 3951653
`
`5.428.307
`GII‘JQS Chatcl el all.
`.. 3o11798
`395,233
`5.454.080 W190i? Fasig et a1
`5.4?3,4‘J9
`12.31905 Weir
`
`, 3151.153
`5.504.636
`411996 Joist
`3511754
`
`5.5l3,329
`434996 Pcconc
`
`3951281
`
`2211:1141
`233992 33ml” “L a -
`I
`”MP”! cl :1 ‘
`
`.3951'283
`[2.119% [Icrrman ........
`43'1'49? Madnick el al.
`34II1'82"[B
`
`.. 307E147
`4111997 Ady el al.
`
`
`531997 Wrighl
`........
`.. 301.055
`
`§é3flr¥lfi
`”’3‘”?
`5,581,712
`5.617.081
`5.625.238
`5.629.83fi
`
`Don Anderson, PCMCIA System Architecture. PC System
`Architecture Series, Second Edition, pp. 21—83, 113—141,
`145—162. 229—309. 321—332. Copyright © 1995. by Mind-
`Shar. [nc.. Richardson, TX.
`Don AndersonfTom Shanley, CardBus System Anitr‘tecture,
`PC System Architecture Series. pp. 17—29, 39—58. 223—236,
`321-361. Copyright ® 1996 by MindShare. Inc.. Richard-
`son, ']‘x,
`Industrial Computers,
`CompactPCI'm Specfication, PCI
`,
`-
`‘
`t
`RLVISIOH 10. Nov. 1, 19)5, pp. 14, 36 and 50.
`.
`,
`,
`.
`.
`,
`,
`Primari- anmmcr—(slenn A. Auvu.
`Assistant Examiner—Paul R. Myers
`Artomqt‘, Agent. or firm—Sharp. Comfort & Merrell. RC.
`.
`.
`.. .
`ABS] mu
`157]
`The invention features a circuit card for use with a computer
`system having a card slot elemrically connected to a bus. The
`.
`,
`..
`_
`.
`.
`_
`card slot has elcclncal contacts corresponding lo [mas of the
`bus. The circuit card has a first pin positioned to extend inlo
`the card slot when the card is inserted into the slot and
`contact a first electrical contact of the slot corresponding to
`a communication line of lhe bus. The circuit card also has a
`second pin positioned to extend into the card slot when the
`card is inserted into the slot and contact a second electrical
`contact of the slot corres ondin to a clock line of the bus
`p
`g
`betore the first pin contacts the first electncal contact.
`
`9 Claims, 11 Drawing Sheets
`
`PCI-vKT
`BRIDGE CIRCUIT
`
`
`
`
`liPMSIcN MD SLUIS
`
`Toshiba_Apricorn 1008-0001
`Toshiba_Apricorn 1008-0001
`IPR2018-01067
`|PR2018—01067
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`
`
`US. Patent
`
`Jul. 13, 1999
`
`Sheet 1 of 11
`
`5,922,060
`
`:96“Sam5%h.0th$55528EEG
`
`
`
`mamQ522%
`
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`
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`
`Toshiba_Apricorn 1008-0002
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`
`
`
`
`US. Patent
`
`Jul. 13,1999
`
`Sheet 2 of 11
`
`5,922,060
`
`
`GND PIN 114
`
`EXPANSION CARD
`
`Vcc PIN 112
`
`110
`
`RSTI‘ PIN
`
`
`
` 104 PRESENCE PIN
`
`106 PCI CLOCK PIN
`
`
`CIIZICImCl
`=u=l
`I
`PC! BUS
`:
`COMMUNICATION PINS “-108
`
`
`|
`
`1102 PRESENCEI F'IN|
`I
`I
`I
`I
`I
`I
`I
`I
`.
`
`101
`
`i
`
`||
`
`130 CLOCK CONTACT
`I 123
`
` EXPANSION
`
`CARD SLOT
`
`
`
`
`OTHER PCI BUS
`RSTfl
`Vac 7
`50
`
`Pm SIGNAL LINE CONTACTS K132
`CONTACT
`CLOCK
`LINE
`
`F]C. 2
`
`PRIMARY PCI BUS
`
`22
`
`PC]
`SLAVE
`
`PCI
`MASTER
`
`BUFFERS
`
`BUFFER
`CONTROL
`
`INTERRUPT
`ROUTING
`
` 56
`
`GRANT SICNALS
`To 31223321“
`
`6‘
`
`ARBITER
`
`REOUEST SICNALS
`53 FROM MONITORING
`CIRCUITS
`
`60
`
`PCl
`MASTER
`
`PCI
`SLAME
`
`SECONDARY PCI BUS
`FIG. 3
`
`30
`
`/
`
`PCI—PCl
`BRIDGE
`CIRCUIT
`
`
`
`52
`
`Toshiba_Apricorn 1008-0003
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`US. Patent
`
`Jul. 13, 1999
`
`Sheet 3 of 11
`
`5,922,060
`
`PRESENCE
`CONTACT
`
`
`
`PRESENCE
`: CONTACT
`
`51
`
`Toshiba_Apricorn 1008-0004
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`US. Patent
`
`Jul. 13,1999
`
`Sheet 4 of 11
`
`5,922,060
`
`51
`
`Toshiba_Apricorn 1008-0005
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`US. Patent
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`Jul. 13,1999
`
`Sheet 5 of 11
`
`5,922,060
`
`250
`
`CARD
`
`INSERTION/
`REMOVAL OF
`
`
`
`
`
`
`REQUEST
`MASTER
`
`
`
`
`CPU
`
`
`
`Toshiba_Apricorn 1008-0006
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`US. Patent
`
`Jul. 13,1999
`
`Sheet 6 of 11
`
`5,922,060
`
`VCC PIN
`VOLTAGE
`
`I 12
`
`PC1
`CLOCK PIN
`VOLTAGE
`
`105
`
`1
`
`1
`
`FIG. 6
`
`REMAINING PCI BUS
`SIGNALS CONNECTED
`
`112
`
`‘05
`
`110
`
`VCC PIN
`VOLTAGE
`
`PCI
`CLOCK PIN
`VOLTAGE
`
`RSTII PIN
`VOLTAGE
`PRESE
`
`NCE
`
`PIN E104
`
`VOLTAGE
`
`FIG. 7
`
`t
`
`1
`
`i
`
`t
`
`1
`
`Toshiba_Apricorn 1008-0007
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`TA
`.
`|
`I
`:
`:
`|
`|
`:
`I
`
`T3
`
`_._
`SIGNAL LINES
`DISCONNECTED
`
`T1
`
`5
`i
`i
`:
`i
`
`T2
`
`
`
`US. Patent
`
`Jul. 13,1999
`
`Sheet 7 of 11
`
`5,922,060
`
`DURATION SET
`BY TIMER 224
`
`Toshiba_Apricorn 1008-0008
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`US. Patent
`
`Jul. 13,1999
`
`Sheet 8 of 11
`
`5,922,060
`
`BEING
`INSERTED
`11110
`SLOT 50
`
`CARD 100
`FULLY
`INSERTED
`11110
`SLOT 50
`
`AND
`POWERED UP
`
`—
`
`
`
`PRESENCE Pm
`
`2 g
`
`—
`
`'f
`
`500
`\1.
`5
`cL
`3
`
`125
`
`123
`
`GOINGHDOWN = H
`111515 =L
`INSZ =H
`TIMEOUT =L
`GOINSHUP = L
`
`EXPANSION wen
`m
`
`1 U4 PRESENCE PIN
`
`PRESENCE Pm
`102
`
`125
`
`123
`
`GOING_DOWN = L
`"4315 = L
`
`INSZ = L
`TIMEOUT = H
`
`FIG. 9
`
`comc_up = L
`
`Toshiba_Apricorn 1008-0009
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`US. Patent
`
`Jul. 13,1999
`
`Sheet 9 of 11
`
`5,922,060
`
`EXPANSION CARD
`m
`
`PRESENCE PIN
`
` E
`
`CARD 100
`BEING
`PARTIALLY
`INSERTED
`INTO
`SLOT so
`
`1
`
`26
`
`1
`
`28
`
`GOING_ DOWN = H
`
`INSTg = L
`[st =11
`TIMEOUT =L
`OOINO_UP = L
`
`EXPANSION CARD
`100
`—
`
`PRESENCE PIN
`
`[NSERTION
`
`CAFRUDLLLOO
`REMOVED
`FROM
`SLOT 50
`AFTER
`PARTIAL
`
`
`
`125
`
`123
`
`GOING_DOWN = L
`
`[N515 = H
`
`{st = H
`TIMEOUT = L
`
`FIG. 10
`
`GOINO_UP =1
`
`Toshiba_Apricorn 1008-0010
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`E
`E
`E
`I
`
`1‘
`z
`Q
`:3
`g
`‘3
`
`502
`\
`ELI
`E-L‘
`
`I 3
`
`
`
`US. Patent
`
`Jul. 13, 1999
`
`Sheet 10 Of 11
`
`5,922,060
`
`EXPANSION CARD
`100
`_
`
`Z
`E
`(“"3
`%
`
`PRESENCE PIN
`
` f
`
`CARD 100
`BEING
`REMOVED
`FROM
`SLOT 50
`
`504
`\«
`“4
`
`g
`
`125
`
`128
`
`GOING_DDwN = L
`
`INS1§ = L
`msz = H
`TIHEOUT= L
`
`GOIMD_UP = H
`
`EXPANSION CARD
`100
`—
`
`PRESEEE PIN
`
`DOWN
`
`CAFRUDLLTOO
`REMOVED
`FROM
`SLOT 50
`AND
`POWERED
`
`
`
`126
`
`128
`
`F10.
`
`1 1
`
`GOINGWDOWN =L
`lNSIf = H
`1st; = H
`TIMEOUT = L
`OOIMO_UP=L
`
`Toshiba_Apricorn 1008-0011
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`US. Patent
`
`Jul. 13, 1999
`
`Sheet 11 of 11
`
`5,922,060
`
`EXPANSION CARD
`LQQ
`
`E
`E
`a:
`5
`
`PRESENCE PIN
`
` I
`
`505
`\
`53-}
`PL
`E
`
`125
`
`123
`
`GOINO_DowN=L
`11151.1: L
`mszg = H
`TIMEOUT=L
`GO]NG_UP = H
`
`EXPANSION CARD
`IOO
`“
`
`CARD 100
`BEING
`PARTIALLY
`REMOVED
`FROM
`SLOT 50
`
`CARD 100
`FULLY
`
`INSERTED
`INTO
`SLOT 50
`AND
`BEING
`
`RENOIIAL
`
`PRESENCE PiN
`
`POWERED UP
`AFTER
`PARTIAL
`
`125
`
`123
`
`FIG. 12
`
`GO]NG_DOWN = L
`mmg=L
`[NS2# = L
`TIMEOUT = L
`GOINc_UP =1
`
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`5 ,922,060
`
`1
`EXPANSION CARD INSERTION AND
`REMIWAL
`
`BACKGROUND
`
`The invention relates to inserting and removing expansion
`cards.
`
`Computer systems typically have expansion card slots for
`receiving and electrically coupling expansion cards to an
`expansion bus of the computer system. The expansion bus
`may be one of several types, such as an Industry Standard
`Architecture (ISA) bus, an Extended Industry Standard
`Architecture (EISA) bus, or a Peripheral Component lnlcr-
`connect (PCI) bus.
`
`SUM MARY
`
`In general, in one aspect, the invention features a circuit
`card for use with a computer system having a card slot
`electrically connected to a bus. The card slot has electrical
`contacts corresponding to lines of the bus. The circuit card
`includes a first pin positioned to extend into the card slot
`when the card is inserted into the slot and contact a first
`electrical contact of the slot corresponding to a communi-
`cation Iine of the bus. The circuit card also has a second pin
`positioned to extend into the card slot when the card is
`inserted into the slot and contact a second electrical contact
`ofthc slot corresponding to a clock line of the bus before the
`first pin contacts the first electrical contact.
`Implementations of the invention may include one or
`more of the following. The circuit card may have a third pin
`positioned to extend into the card slot when the card is
`inserted into the slot and contact a third electrical contact of
`the slot corresponding to a power supply line before the first
`pin contacts the first electrical contact. The position of the
`third pin may allow the third pin to contact
`the third
`electrical contact before the Second pin contacts the second
`electrical contact when the card is inserted into the slot. The
`position of the third pin may permit the third pin and the
`second pin to concurrently contact the second and third pins
`when the card is inserted into the slot. The circuit card may
`have a third pin positioned to extend into the card slot when
`the card is inserted into the slot and contact a third electrical
`contact of the slot used to indicate presence of the circuit
`card in the slot. This third pin may contact the third electrical
`contact before the first and second pin contacLs the lirsl and
`second electrical contacts when the card is inserted into the
`slot. The first pin may be shorter than the second pin.
`In general,
`in another aspect,
`the invention features a
`computer system having a bus, a card slot connected to the
`bus, and an arbiter. The arbiter is configured to receive
`requests for access to the bus and selectively grant access to
`the bus. The computer system also has a circuit connected to
`the card slot and configured to interact with the arbiter to
`request access for the bus when a card is inserted into the
`slot.
`Implementations of the invention may include one or
`more of the following. The computer system may have a
`central processing unit and another circuit connected to the
`card slot configured to detect insertion of a card into the card
`slot and provide an indication to the central processing unit
`when the card is inserted into the slot. The circuit configured
`to interact with the arbiter may hold access to the bus when
`granted by the arbiter until the card is fully inserted into the
`slot.
`
`the invention features a
`in another aspect,
`In general,
`computer system having a bus. a card slot connected to the
`
`2
`bus, and an arbiter. The arbiter is configured to receive
`requests for access to the bus and selectively grant access to
`the bus The computer system also has a circuit connected to
`the card slot and configured to interact with the arbiter to
`request access for the bus when the card is removed from the
`slot.
`
`Implementations of the invention may include one or
`more of the following. The computer system may have a
`central processing unit and another circuit connected to the
`card slot configured to detect removal of a card from the card
`slot and provide an indication to the central prowssing unit
`when the card is removed from the slot. The circuit config—
`ured to interact with the arbiter may hold access to the bus
`when granted by the arbiter until the card is fully removed
`from the slot.
`
`the invention features a
`in another aspect,
`in general,
`computer system having a central procefiing unit, a bus, a
`card slot connected to the bus, and a circuit. The circuit is
`connected to the card slot and configured to provide an
`indication to the central processing unit when the card is
`inserted into the slot.
`
`It)
`
`15
`
`2|)
`
`the invention features a
`in another aspect,
`In general,
`computer system having a central pmcessing unit, a bus, a
`card slot connected to the bus, and a circuit. The circuit is
`connected to the card slot and configured to provide an
`indication to the central processing unit when the card is
`removed from the slot.
`
`the invention features a
`in another aspect,
`In general,
`method for use in a computer system having a bus and a card
`slot connected to the bus. The method includes detecting
`insertion of the card into the slot and arbitrating for control
`of the bus when insertion is detected.
`
`the invention features a
`in another aspect,
`in general,
`method for use in a computer system having a bus and a card
`slot connected to the bus. The method includes detecting
`removal of the card from the slot and arbitrating for control
`of the bus when removal is detected.
`
`the invention features a
`in another aspect,
`In general,
`method for use in a computer system having a card slot
`connected to the bus. The method includes detecting partial
`insertion of a card into the card slot and holding the card in
`reset between a time when the card is partially inserted into
`the card slot and a time when the card is more fully inserted
`into the card slot.
`
`Implementation of the invention may include the com-
`puter system having a central processing unit, and the
`method may include indicating to the central processing unit
`when the card has been inserted into the slot.
`
`the invention features a
`in another aspect,
`[11 general,
`method for use in a computer system having a card slot
`connected to a bus, The method includes detecting removal
`of a card from the card slot and holding the card in reset
`between a time when the card is partially removed from the
`card slot and a time when the card is more fully removed
`from the card slot.
`
`Implementation of the invention may include the coni-
`puter system having a central processing unit, and the
`method may further include indicating to the central pro—
`cessing unit when the card has been removed from the slot.
`In general,
`in another aspect, the invention features a
`method for use in a computer system having a card slot
`connected to a bus and a central processing unit. The method
`includes detecting removal of the card from the slot and
`indicating to the central processing unit when the card has
`been removed front the slot.
`
`4U
`
`50
`
`fill
`
`05
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`3
`the invention features a
`in another aspect,
`In general,
`method for use in a computer system having a card slot
`connected to a bus and a central processing unit. The method
`includes detecting insertion of the card into the slot and
`indicating to the central processing unit when the card has
`been inserted into the slot.
`
`10
`
`DESCRIPTION
`
`FIG. 1 is a block diagram of a computer system.
`FIG. 2 is a schematic diagram of an expansion card and
`an expansion card slot.
`FIG. 3 is a block diagram of a bridge circuit of FIG. 1.
`FIGS. 4A—B are schematic diagrams of expansion card
`circuitry.
`FIG. 5 is a state diagram showing a three—level arbitration
`scheme.
`
`FIGS. 6—8 are waveforms from the computer system
`illustrating power up and power down sequences.
`FIGS. 9—42 are illustrations of an expansion card being
`inserted into and removed from a slot.
`
`In the following description. the suffix “a" and the prefix
`"!“ indicate negative logic.
`As shown in FIGS. 1 and 2, a computer system 10 has six
`conventional expansion card slots SOn—f in which expansion
`cards 100 can be inserted (i.e., "hot-plugged“) and removed
`while the computer system 10 remains powered up. Each
`slot 50 has spring-like contacts 120-132 for physically
`securing the card. 100 and for electrically connecting (via
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`the invention features a
`In general, in another aspect,
`computer system having a bus having lines for communi-
`cation and having a clock line; a central processing unit
`capable of accessing the bus; and a card slot electrically
`connected to the bus. The card slot has electrical contacts
`corresponding to the lines of the bus. The computer system
`also has a circuit card inserted into the slot having a first pin
`positioned to extend into the card slot when the card is
`inserted into the slot and contact a first electrical centact of
`the slot corresponding to one of the communication lines of
`the bus. The computer system also has a second pin posi-
`tioned to extend into the card slot when the card is inserted
`into the slot and contact a second electrical contact of the
`slot cormsponding to the clock line ot‘thc bus before the first
`pin contacts the first electrical contact.
`In general,
`in another aspect,
`the invention features a
`circuit card for use with a bus having communication lines.
`The circuit card includes a communication pin for electri—
`cally connecting to one of the communication lines of the '
`bus and a clock pin being longer than the communication
`pin.
`the invention features a
`in another aspect,
`In general,
`computer system having a central processing unit and a bus
`having communication lines. The computer system also has
`a circuit card including a communication pin for electrically
`connecting to one of the communication lines ofthe bus and
`a clock pin being longer than the communication pin.
`Among the advantages of the invention are one or more
`of the following. Operations on a card inserted into Ihe slot
`are powered up in an orderly fashion. Operations on a card
`removed from the slot are halted in an orderly fashion. A
`current transaction on the bus is halted in an orderly fashion
`when a card is inserted into or removed from the slot. A
`conventional slot may be used.
`Other advantages and features will become apparent from
`the following description and from the claims.
`
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`pins 102—114 of the card 100} the card 100 to a secondary
`Peripheral Component Interconnect (PCI) bus 32 when the
`card 100 is fully inserted.
`For purposes of coordinating the insertion and removal of
`the card 100 with operations on the bus 32, monitoring
`circuits Sta—f [one for each of the expansion card slots
`50n—j), of design 51. interact with a PCl-FCI bridge circuit
`30 to request control of (i .e., arbitrate for) the secondary PCI
`bus 32 when one of the monitoring circuits Sln—f senses
`insertion or removal of the expansion card 100 into or from
`its slot 50. Because of the relatively long time (e.g., tenths
`of a second as compared to microseconds) required for
`someone to insert or remove the card 100. before PCI
`communication pins 108 of the card 100 are electrically
`disconnected from (upon removal of the card 100} or
`connected to (upon insertion of the card 100) corresponding
`communication lines (c.g., addresstdata lines) of the PCI bus
`32, the bridge circuit 30 grants control of the PCI bus 32 lo
`the monitoring circuit 51,
`thereby excluding other bus
`masters from using the bus 32. Therefore. when electrical
`connections are being made or broken. resultant glitches on
`the PCI bus 32 do not disturb operations of other bus devices
`connected to the bus 32 (cg. other cards 100 that are
`inserted and powered up).
`The cards 100 are powered up through a power up
`sequence and powered down through a power down
`sequence. Portions of the power up sequence {card 100 is
`inserted) and the power down sequence [card 100 is
`removed) are governed by the relative lengths of the pins
`102-414 of the card 100 and the movement of the pins
`102—114 within the slot 50 during insertion and removal, as
`described below.
`
`As shown in FIG. 7. in the power down sequence, the card
`100 being removed is first placed in reset (at time T,) by
`asserting a reset pin 110 of the card 100. Next, the PCI bus
`communication signals {c.g.. the signals from the address;r
`data lines of the bus 32) are disconnected (at time T2) from
`the card 100. The PCI clock signal is subsequently discon-
`nected (at time T3) from a PC] clock pin 106 ofthe card 100
`before power from the card 100 is removed at time T4. The
`power down sequence reduces the propagation of false
`signals from the card 100 being removed to the bus 32
`because circuitry on the card 100 remains functional (due to
`the connection of power and the clock signal to the card 100)
`until the PCI bus communication signals are removed.
`As shown in FIG. 6. in the power up sequence, the card
`100 is first configured to be in reset when power is supplied
`(at time T.). Thereafter, a PCI clock signal ( from the PCI bus
`32) is furnished {at time T2) to the card 100 being inserted.
`Remaining PCI bus communication signals of the card 100
`are then coupled (at time 1'3) to corresponding lines of the
`PCI bus 32. The card 100 being inserted is brought out of
`reset (at time T..]. Lastly. the monitoring circuit 51 and the
`PCI—PCI bridge circuit 30 interact to release control of the
`secondary PCI bus 32 and allow other has masters to carry
`out transactions on the bus 32.
`
`In addition to the PCl—PCTI bridge circuit 30, the com-
`puter system 10 includes a central processing unit (CPU) 12,
`a level two (I2) cache 14. and a system memory 20, all of
`which are coupled to a local bus 16. Asystem controllcn’host
`bridge circuit 18 interfaces the local bus 16 to a primary PCI
`bus 22 and furnishes an interface to the system memory 20.
`The PCl—PCI bridge circuit 30, a video controller 26, and
`a PCI-Industry Standard Architecture (I’CI-ISA) bridge cir-
`cui124 are all coupled to the primary I’Cl bus 22. The video
`controller 26 interfaces the PCI bus 22 lo a display 28, and
`
`Toshiba_Apricorn 1008-0014
`Toshiba_Apricorn 1008-0014
`IPR2018-01067
`|PR2018—01067
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`5 £22,060
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`5
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`10
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`2t)
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`the bridge circuit 24 interfaces the l’Cl bus 22 to an [SA bus
`34. An intelligent Drive Electronics (IDE) interface 36 and
`an inputt’output (IIU) chip 38 are both coupled to the ISA bus
`34. The IDE interface 36 controls operation of a CD-ROM
`drive 46 and a hard disk drive 48. The ItO chip 38 receives
`input data from a mouse 40 and a keyboard 42. The NO chip
`38 also controls operation of a Iloppy disk drive 44.
`As shown in FIG. 2, for purposes of establishing the
`connectionfdisconneclion order in the power up and power
`down sequences, the expansion card 100 takes advantage of
`the fact that the receiving ends of the contacts 120—132 are
`equidistant from an opening 53 of the slot 50 that receives
`the card 100. Therefore, as the card 100 is inserted into the
`slot 50 (assuming the card 100 is inserted with the bottom
`edge [01 generally parallel to the top edge of the slot 50),
`a portion of the power up sequence is established by the
`relative lengths ollhe pins oil the card 100, as the longer pins
`make contact first. Similarly, as the card 100 is removed
`from the slot 100 (which establishes a portion of the power
`down sequence),
`the shorter pins of the card 100 break
`electrical contact with the contaCLs 120—132 llI'Sl.
`In order to reset the card 100 during the power up and
`power down sequences, the reset pin 110 of the card 100
`(corresponding to the contact 120) extends as far as any of
`the other pins 102—114 toward the bottom 101 of the card _
`100. For purposes of establishing a common ground for the
`power up and power down sequences, a ground pin 114 of
`the card 100 (corresponding to the contact 124) extends as
`far down as the reset pirt 110. The voltage supply pin 112 of
`the card 100 (corresponding to the contact 122) extends
`toward the bottom 101 of the card 100 but does not extend
`as far as the reset pin 110. The PCl clock pin 106
`(corresponding to the contact 130) extends toward the
`bottom 101 of the card 100 but does not extend as far as the
`voltage supply pin 112. The PC! bus communication pins
`108 (corresponding to contacts 132) extend toward the
`bottom 101 of the card 100 but do not extend as far as the
`clock pin 106. The pins 102—1 14 and corresponding contacts
`120—132 are shown aligned sidc‘by—side [or
`illustrative
`purposes.
`For purposes of requesting control of the bus 32 and
`placing the card 100 in reset before the beginning of the
`power up and power down sequences, the monitoring circuit
`51 senses partial insertion of the card 100 into the slot 50 and
`partial
`removal of the card 100 from the slot 50. For
`purposes of sensing partial insertion of the card 100 into the
`slot 50, a presence sensing pin 102 (corresponding to the
`contact I26) extends toward the bottom 101 of the card 100
`and is ol‘
`the same length as the ground pin 114. The
`presence sensing pin 102 is electrically connected to the
`ground pin 114, and when the expansion card 100 is first
`inserted into the expansion card siot 50, the ground pin 114
`of the expansion card 100 contacLs the corresponding ground
`pin contact 124 ot‘ the expansion card slot 50 (which is
`coupled to ground of the computer system 10). Because the
`presence sensing pin 102 is of the same length of the ground
`pin 104 and electrically connected to the ground pin 104, the
`presence sensing pin 102 is connected to ground when the
`expansion card slot 100 is partially inserted into the card slot
`50. Thus. the grounding of the presence sensing pin 102
`indicates (by the transition of the voltage level of the pin
`102) when the card 100 is first inserted into the slot 50 and
`indicates when the card 100 has entirely left the slot 51}.
`Similarly, for purposes of detecting when the expansion
`card 100 has been partially removed from the slot 50, the
`ground pin [14 is aLso electrically connected to a presence
`sensing pin 104 which is shorter than the PC] communica-
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`tion pins 108. Therefore, the disconnection of the presence
`sensing pin 104 I'rom ground indicates [by the transition of
`the voltage level of the pin 104) the initial removal of the
`card 100 and indicates when the card 100 is fully inserted.
`Partial
`insertion of the card 100 into the slot 50 may
`indicate someone has initiated insertion of the card 100 into
`the slot 50. However. partial
`insertion may alternatively
`indicate insertion of the card 100 has been aborted. The
`monitoring circuit 51 detects both scenarios. As shown in
`FIG. 9, in one example 500, the slot 50 is initially empty, and
`the card 100 is then partially inserted into the slot 50 (as
`indicated by the grounding ol'the presence sensing pin 102).
`The card 100 is then fully inserted into the slot 50 (as
`indicated by the grounding of the presence sensing pin 104)
`and powered up. Ilowever, in another example 502 (FIG.
`10}, instead of fully inserting the card 100 into the slot 50,
`the card 100 is subsequently removed from the slot 50 after
`partial insertion (as indicated by the disconnecting of ground
`from the presence sensing pin 102).
`Similarly, besides recognizing when someone has initi-
`ated a removal of the card 100 from the slot 50,
`the
`monitoring circuit 51 also detects when a removal of the
`card 100 has been aborted. As shown in FIG. 11.
`in one
`example 504-, a fully inserted card 50 is partially removed
`(as indicated by the disconnecting of ground from the
`presence sensing pin 104). The card 100 is
`then I'ully
`removed from the slot 50 as indicated by the disconnecting
`ot‘ ground from the presence sensing pin 102 and powered
`down. However,
`instead of being Fully removed from the
`slot 50, the card 100 may subsequently be fully inserted
`(FIG. 12) into the slot 50 after partial removal. The full
`insertion of the card 100 back into the slot 50 is indicated by
`the subsequent grounding of the presence sensing pin 104
`after the detected partial removal of the card 100 (indicated
`by disconnection of ground from the presence sensing pin
`102).
`As shown in FIG. 3. for purposes of controlling access to
`the PCI bus 32, the PCl—PCI bridge circuit 30 includes an
`arbiter 60. The arbiter 60 receives PC] request signals (via
`request lines 63 separate from request lines of the bus 32)
`front
`the monitoring circuits 51n—f and furnishes corre-
`sponding grant signals (via grant lines 61 separate from
`grant lines of the bus 32) to the monitoring circuits Sin—f.
`Although the arbiter 60 has a programmable grant
`timer
`(programmed via configuration registers 56) to govern the
`maximum duration a bus master may hold the bus 32, the
`arbiter 60 allows the monitoring circuit 51 to hold access to
`the bus 32 until the monitoring circuit 51 releases the bus (at
`the completion of the power up or power down sequence),
`as described below.
`As shown in FIG. 5, the arbiter 60 has three levels 250,
`252, and 254 of arbitration. 1n the first level 250 (the highest
`priority level),
`the arbiter 60 arbitrates in a round-robin
`fashion between a request from the second levei 252 (the
`level with the second highest priority) and a request 256
`from one of the monitoring circuits Sin—f. For the second
`level 252, the arbiter 60 arbitrates in a round-robin fashion
`between requests 260 from a retrying master on the bus 32,
`a third level request 254 (lowest priority level), and a CPU
`10 delayed request 258. For the third level 254, the arbiter
`60 arbitrates in a round-robin fashion between requesting
`masters 262—274 on the bus 32. 'lherefore. at most, only one
`transaction is performed when either the card 100 is first
`partially inserted or removed, and alter the one transaction,
`the arbiter 60 grants control to the monitoring circuit 51
`requesting the bus 32.
`For transactions on the primary PCI bus 22, the bridge
`circuit 30 includes a PCl stave 54 and a PC] master 52, both
`
`Toshiba_Apricorn 1008-0015
`Toshiba_Apricorn 1008-0015
`IPR2018-01067
`|PR2018—01067
`
`
`
`5 £22,060
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`7
`of which are coupled to the primary PCI bus 22. For
`transactions on the secondary PCI bus 32. the bridge circuit
`30 includes a PC] master 62 and a PCI slave 64, both of
`which are coupled to the secondary PCI bus 32. Butlers 58
`interact with buffer control logic 66 to control the flow of
`transactions between the buses 22 and 32 and preserve the
`PCI transactional ordering rules. Interrupt routing logic 68
`directs the flow of interrupt requests from the bus 32 to the
`bus 22.
`For purposes of indicating to the CPU 10 when the card
`100 has been partially inserted or removed, the monitoring
`circuit 51 furnishes an interrupt
`request signal
`INTER—
`RUI’I‘tt‘ which is asserted, or driven low.
`to indicate a
`detected insertion or removal and deassertcd, or driven high,
`otherwise. As shown in FIG. 4A,
`in order to furnish the
`signal [N'I'ERRUPI'#, the monitoring circuit 51 includes. an
`interrupt circuit 154. The signal IN'I‘ERRUl’l‘ttt is furnished
`by the inverting output of a D-type flip-flop 155 which is
`clocked on the positive edge of a PCI clock signal CLK
`(from the bus 32). The input of the flip-flop 155 is connected
`to the output of an OR gate 157 which has one input
`connected to the output of an AND gate 161. The AND gate
`161 receives a signal tINSlttI and a signal GOING___UP. The
`signal GOING UP is asserted, or driven high, to indicate
`when the card 100 is being removed from the Blot 50. The
`signal [N81# is indicative of the voltage level of the Contact
`126 (corresponding to the pin 102). Therefore, when the card
`100 is removed from the slot 50, the signal IN'I‘ERRUI’Ttt'
`is asserted.
`Another input of the OR gate 15'? is connected to the
`output of an AND GATE 159. The AND gate 159 receives
`a signal GOING DOWN that is asserted, or driven high, to
`indicate when the card 100 is being inserted into the slot 50.
`The AND gate 159 also receives a signal IlNSZil‘ a nd a signal
`TIMEOUT. The signal 1N82# is indicative of the voltage
`level ot‘ the contact 128 (corresponding to the pin 104). The
`signal TIMEOUT is asserted, or driven high,
`to indicate
`when the card 100 has powered up and stabilized. Therefore,
`when the card 101} is inserted into the slot 50 and powered
`up,
`the signal
`INTERRUPT# is asserted. The signals
`GOING UP and GOING DOWN are otherwise
`deasserted, or driven low.
`For purposes of generating the signal GOING_DOWN.
`the monitoring circuit 51 includes a circuit 150. The signal
`GOING_DOWN is furnished by the output of a J-K flip-
`flop 160 which is clocked on the positive edge of the signal
`CLK. The .1 input of the flip-flop 160 is connected to the
`output of an OR gate 162. One input of the OR gate 162 is
`conne