Analysis and Software Implementation of a
`Robust Synchronizing PLL Circuit
`
`Luís Guilherme B. ROLIM, Member, IEEE, Diogo R. COSTA, Jr.,
`
`and Maurício AREDES, Member, IEEE
`
`Federal University of Rio de Janeiro (UFRJ), Electrical Engineering (COPPE and POLI)
`
`P.O.Box 68504, 21945-970 – Rio de Janeiro – Brazil
`
`e-mail: [rolim | diogo | aredes]@coe.ufrj.br
`
`
`
`
`
`Abstract—This paper presents the analysis and software implementation of a robust syn-
`
`chronizing circuit – PLL circuit – designed for using in the controller of active power line con-
`
`ditioners. The basic problem consists in designing a PLL circuit that can track accurately and
`
`continuously the positive-sequence component at the fundamental frequency and its phase an-
`
`gle, even when the system voltage of the bus, to which the active power line conditioner is
`
`connected, is distorted and/or unbalanced. The fundaments of the PLL circuit are discussed.
`
`It is shown that the PLL can fail in tracking the system voltage during the startup, under some
`
`adverse conditions. Moreover, it is shown that oscillations caused by the presence of sub-
`
`harmonics can be very critical and can pull the stable point of operation synchronized to that
`
`sub-harmonic frequency. Oscillations at the reference input are also discussed, and the solu-
`
`tion of this problem is presented. Finally, experimental and simulation results are shown and
`
`compared.
`
`
`
`Index Terms—Phase locked loops (PLL), Phase synchronization, Power systems.
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`I. INTRODUCTION
`
`Most applications of static converters connected to the utility power grid require synchroni-
`
`zation between the grid voltage and the voltage or current synthesized by the converter. As
`
`examples of such applications can be pointed out:
`
`• converters that inject energy coming from alternative supplies into the grid;
`
`• Active Power Line Conditioners, FACTS and Custom Power devices (e.g. DVR,
`
`STATCOM, active filters [1]-[3]).
`
`In many cases, the reference signal obtained from the grid voltage is contaminated by har-
`
`monics, which may have been produced by the power converter itself or generated elsewhere.
`
`Additionally, the voltages in a three-phase system may contain unbalances from negative-
`
`and/or zero-sequence components, which could cause improper synchronization between con-
`
`verter and grid.
`
`The most widely accepted solution to provide synchronization between time-varying signals
`
`is the use of a phase-locked-loop (PLL) system [4] that can be described by the basic structure
`
`shown in block diagram form in Fig. 1. This simplified PLL structure comprises a phase detec-
`
`tor (PD), a loop filter (LF) and a controlled oscillator (VCO), each of which can be imple-
`
`mented in several different forms. If the signal to be tracked (reference input) is an analog sig-
`
`nal, then the most suitable type of PD to be used is the product-type one. The use of a prod-
`
`uct-type PD plus a linear LF causes the PLL to behave linearly for small variations on input,
`
`
`
`
`reference
`input u1(t)
`
`
`
`
`
`phase
`detector
`(PD)
`
`phase
`error ud(t)
`
`loop filter
`(LF)
`
`VCO
`output u2(t)
`
`controlled
`oscillator
`(VCO)
`
`VCO
`input uf(t)
`
`
`
`Fig. 1 Block diagram of basic PLL structure
`
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`yielding a linear PLL.
`
`II. FUNDAMENTALS OF THE THREE-PHASE PLL CIRCUIT
`
`In the case of three-phase input signals, traditional (single input) PLL system analysis [4] can
`
`still be applied if small modifications are introduced in the simplified structure of Fig. 1. In
`
`view of that, in this work, the reference input is represented by a space vector, as well as the
`
`VCO output:
`
`(
`=
` )( twjeUtu
`1
`1
`
`
`
`1
`
`)1
`f+
`
` and
`
`(
`=
`
` )( twjeUtu
`2
`2
`
`2
`
`f+
`
`)2
`
`
`
`(1)
`
`In stationary (ab) reference frame, both signals can be written in the form u(t) = ua + jub ,
`
`where the a
`
` and b
`
` components are ua(t)=Ucos(wt+f) and ub(t)=Usin(wt+f). Three-phase in-
`
`put signals can be easily converted to this form through the Clarke Transformation. Alterna-
`
`tively, these signals can be represented in a synchronously rotating reference frame (through
`
`the Park Transformation) as shown in [5], with similar results.
`
`The angular frequency w2 of the VCO output signal is related to its input uf(t) by:
`
`w2 = w0 + uf(t) ,
`
`(2)
`
`where w0 is called the center frequency.
`
`The phase detector’s operation is based on the product of both space vectors u1(t) and u2(t).
`
`For this reason it is often called a vector-product phase detector (VP-PD). Its output can be
`
`obtained from the operation:
`
`ud(t) = u1(t) . u2(t)* = U1U2 ej(w1-w2)t ej(f1-f2),
`
`(3)
`
`where the asterisk denotes the complex conjugate. Alternatively, the phase error signal can
`
`be expressed in rectangular form as
`
`ud(t) = (u1a u2a+ u1b u2b) + j(u1b u2a - u1a u2b).
`
`(4)
`
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`It is evident from (4) that the real and imaginary components of ud(t) have, respectively, the
`
`same form as the p and q power components from Akagi’s instantaneous power theory [7],[8].
`
`Hereafter, two different approaches can be adopted: if the real part of ud(t) is used as feedback
`
`error signal, then we have the so-called p-type PLL system, or p-PLL for short. Using the
`
`imaginary part of ud(t) yields the so-called q-PLL [9]. The latter approach will be used in the
`
`analysis presented next, but the results are applicable to p-PLL systems as well.
`
`Now, considering that w1 = w2 = w0 (i.e. the PLL is nearly locked at the center frequency),
`
`then the phase error signal given by (3) can be further simplified to ud(t) = Im{U1U2 ej(f1-f2)},
`
`which yields:
`
`
`
`ud(t) = U1U2.sin(f1 - f2) ,
`
`(5)
`
`For small phase deviations, this relationship can be approximated linearly by:
`
`ud(t) » Kd.fe(t) ,
`
`(6)
`
`where Kd = U1U2 and fe(t) = f1(t) – f2(t).
`
`If the amplitudes U1 and U2 are both normalized to unity, then (6) further simplifies to ud(t) »
`
`fe(t). As a result, the linearized behavior of the PLL can be described by the simplified block
`
`diagram shown in Fig. 2.
`
`In the block diagram shown in Fig. 2, the center frequency appears as a term added to the
`
`output of the PI loop filter. This produces the same effect as a non-zero initial condition at the
`
`integrator’s output. For a proportional plus integral (PI-type) loop filter, as the one shown in
`
`Fig. 2, the linearized loop transfer function between f1(t) and f2(t) is given by:
`
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`
`
`(7)
`
`(8)
`
`f2(t)
`
`s1
`
`
`VCO
`
`uf
`
`w0
`
`+
`
`sK
`
`i
`
`+
`
`K
`P
`
`loop filter
`
`fe(t)
`
`f1(t)
`
`+ -
`f2(t)
`
`
`
`Fig. 2 Small-signal block diagram.
`
`.
`
`+
`KsK
`P
`i
`+
`+
`KsK
`P
`
`i
`
`2
`
`s
`
`=
`
`ss
`
`)(
`)(
`
`12
`
`FF=
`
`
`
`sH )(
`
`H(s) can be rewritten in the form:
`
`
`
` )(sH
`
`=
`
`xw
`s
`2
`n
`+
`xw
`2
`
`+
`2
`w
`n
`+
`w
`s
`
`n
`
`2
`n
`
`
`
`2
`
`s
`
`.
`
`i
`
`K
`
`P K
`
`2
`
`K=w
`where
`
`n
`
`i
`
`and
`
`=x
`
`Well-designed PLL systems should meet the following design criteria:
`
`• x » 0.7 for optimum transient response (ITAE sense);
`
`• narrow bandwith (low wn) for improved noise rejection, in order to produce a purely si-
`
`nusoidal output signal even in the presence of input harmonics.
`
`The PLL lock range is defined as the maximum initial frequency deviation between reference
`
`80
`
`70
`
`60
`
`50
`
`40
`
`30
`
`20
`
`10
`
`0
`
`f(Hz)
`
`0.5
`
`1
`
`1.5
`
`2
`
`2.5
`
`3
`
`3.5
`
`-10
`0
`
`t(s)
`
`4
`
`
`
`0.5
`
`1
`
`1.5
`
`2
`
`2.5
`
`3
`
`3.5
`
`t(s)
`
`4
`
`
`
` (a)
`
`(b)
`
`Fig. 3 Simulation results for sub-harmonic disturbances at 1Hz:
`(a) 7% in magnitude and (b) 10% in magnitude
`
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`80
`
`70
`
`60
`
`50
`
`40
`
`30
`
`20
`
`10
`
`0
`
`-10
`0
`
`f(Hz)
`
`
`
`

`

`input and VCO output, which will still cause the PLL to get locked in a single beat. It can be
`
`shown to be approximately equal to the natural frequency wn:
`
`DwL » wn.
`
`(9)
`
`Thus, a narrow-bandwith PLL may fail to lock at some desired frequency during the start-up
`
`transient, if following conditions are met:
`
`•
`
`•
`
`•
`
`the input signal contains harmonic components;
`
`the initial PI output is more distant from the desired frequency than the lock range;
`
`the initial PI output (or the center frequency) is close to some harmonic.
`
`It is however very difficult to predict the behavior of the PLL under the above conditions, be-
`
`cause it depends on the relative amplitude of the harmonic components. Sub-harmonic oscilla-
`
`tions at the reference input can cause the PLL to lock at the lower sub-harmonic frequency,
`
`even if the relative magnitude is very low. This fact is illustrated by the simulation results pre-
`
`sented in Fig. 3a and Fig. 3b. For both simulations, the frequency of interest is 60Hz (with
`
`normalized amplitude of 1 p.u.) and a disturbance at 1Hz has been added. The initial condition
`
`at the PI loop filter output is zero, what means that the VCO starts from zero frequency or DC
`
`conditions. If the disturbance is slightly increased beyond 7% of the main component, the PLL
`
`fails to lock at the desired center frequency of 60Hz. Fig. 3a shows a critical situation where
`
`7% of disturbance at 1Hz is introduced and the PLL still locks at the center frequency (60Hz).
`
`However, it locks at 1Hz instead, as shown in Fig. 3b, if the disturbance is increased to 10% at
`
`1Hz.
`
`As the frequency of interest for grid-connected applications is essentially constant (50Hz or
`
`60Hz), an obvious solution to the above problem would be tuning the PLL by adjusting its
`
`center frequency to the nominal grid frequency. However, an even safer solution is the intro-
`
`duction of limits to the PI output, so that the VCO frequency variation is confined to the center
`
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`

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`frequency (chosen equal to the grid frequency) plus or minus the lock range. A potential risk
`
`introduced by this approach is the chance of occurring so-called reset windup problems in the
`
`controller [6], which can lead to undesired oscillations, numerical overflow problems and even
`
`to instability. To avoid these difficulties, some anti windup strategy should be used for imple-
`
`mentation of the control algorithms. This solution has been implemented by software in a
`
`TMS320LF2407 DSP. Some implementation details are given in the next section.
`
`III. IMPLEMENTATION DETAILS
`
`The proposed PLL system was
`
`implemented with fixed-point arithmetic
`
`in
`
`the
`
`TMS320LF2407 DSP, using a 10 kHz sampling frequency. The algorithm is executed as an
`
`interrupt service routine (ISR), which is triggered by one of the general-purpose timer circuits
`
`available on-chip. The same timer also triggers the acquisition of input signals, simultaneously
`
`with the interrupts. As the on-chip A/D converters are fast (approximately 500ns conversion
`
`time), input data is made available at the beginning of the ISR with negligible time delay.
`
`A simplified block-diagram representation of the implemented algorithm is shown in Fig. 4
`
`(compare to the block diagram of Fig. 1). The line voltages vab and vbc are converted to the a b
`
`
`
`reference frame through the Clarke Transformation, immediately after A/D conversion. The
`
`feedback signals corresponding to VCO output (labeled i´a and i´b in Fig. 4) are generated in
`
`a´i
`
`sin(w
`
`t)
`
`tw
`
`s1
`
`w
`
`PI Controller
`
`vab
`
`vbc
`
`av
`
`bv
`
`X
`
`X
`
`a-b
`Transf.
`
`f3´p
`
`cos(w
`
`t)
`
`b´i
`
`
`
`Fig. 4 Block-diagram representation of the implemented algorithm
`
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`S
`

`

`real time by table interpolations, which give the sine and the cosine of the output angle w
`
`t. The
`
`vector product between the reference input signals and VCO outputs (va + j vb and i´a + j i´b
`
`respectively) is calculated as the sum of products of the individual components. The resulting
`
`quantity can be also interpreted as the real power, according to Akagi´s pq theory ([7],[8]) and
`
`it is the input error signal for the PI-Controller. Hence, in this case a p-type PLL has been im-
`
`plemented. The output signal produced by its phase detector (VP-PD) is called p´3f and can be
`
`written as:
`
`p´3f = 3.V.I.cos(f1 - f2) ,
`
`(10)
`
`for the PLL in the locked state at the center frequency.
`
`In steady state, the VCO outputs (i´a + j i´b ) lead the reference input signals (v´a + jv´b ) by
`
`90°. This fundamental characteristic should be reminded when the PLL circuit is applied.
`
`IV. EXPERIMENTAL RESULTS
`
`The experimental results obtained by the PLL algorithm, which has been implemented with
`
`fixed point arithmetic in the TMS320LF2407 DSP, were compared with simulations carried
`
`out in MATLAB®. The input signals used in the simulations were the same ones acquired dur-
`
`ing the experimental tests. The sampling frequency used in the simulations was also 10 kHz.
`
`The chosen LF parameters were kP = 50 and kI = 5000, yielding a lock range of approximately
`
`wn = 70rad/s (11Hz) and a damping coeficient of nearly x = 0.35.
`
`A. Unbalanced input signals
`
`In this case, in all experimental tests, as well as in the simulations, the PI output values were
`
`limited to a minimum of 0.5 (corresponding to 30Hz) and a maximum of 1.5 (corresponding to
`
`90Hz), since the center frequency (60Hz) was normalized to 1 p.u.
`
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`Six test cases have been carried out, with different initial conditions at the PI’s output and
`
`different input signals (balanced and with negative-sequence unbalance). In the first test case,
`
`balanced input signals were applied and the initial value for the PI’s output was set equal to
`
`one (i.e. the resulting initial frequency deviation is inside the lock range). In the second test
`
`case, unbalanced input signals were applied, containing 12.5% of negative-sequence compo-
`
`nent at the fundamental frequency, and the initial value for the PI’s output was also equal to
`
`one. The results of these cases are shown in Fig. 5 and Fig. 6 respectively, where the dynamic
`
`response of the PLL circuit can be observed. In both cases, where the PI’s output was initial-
`
`Simulation
`Experimental
`
`0.05
`
`0.1
`
`0.15
`(a)
`
`0.2
`
`0.25
`
`0.3
`
`t(s)
`
`Simulation
`Experimental
`
`0.05
`
`0.1
`
`0.15
`(b)
`
`0.2
`
`0.25
`
`t(s)
`
`0.3
`
`
`
`1
`
`0.5
`
`0
`
`-0.5
`
`-1
`
`0
`
`1.3
`
`1.2
`
`1.1
`
`1
`
`0.9
`
`0
`
`error
`
`f(pu)
`
`Fig. 5 Experimental and simulation results for signal balanced and
`the initial value for the PI’s output equal to 1: (a) error (b)PI output
`
`Simulation
`Experimental
`
`0.05
`
`0.1
`
`0.15
`(a)
`
`0.2
`
`0.25
`
`0.3
`
`t(s)
`
`Simulation
`Experimental
`
`0.05
`
`0.1
`
`0.15
`(b)
`
`0.2
`
`0.25
`
`t(s)
`
`0.3
`
`
`
`0.5
`
`0
`
`-0.5
`
`error
`
`-1
`
`0
`
`1.2
`
`1.1
`
`1
`
`0.9
`
`0.8
`
`0
`
`f(pu)
`
`Fig. 6 Experimental and simulation results for signal unbalanced
`and the initial value for the PI’s output equal to 1:(a) error (b)PI out-
`put
`
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`

`

`ized with 1.0, the PLL circuit locks to the desired frequency in approximately 170ms. The ex-
`
`pected settling time would lie between approximately four to five units divided by the product
`
`x (cid:215) wn (i.e. 160–200ms). In the second test, the output frequency presents ripples smaller than
`
`two percent.
`
`The third test case comprises balanced input signals and the PI initial value is equal to 0.5
`
`(i.e. outside the lock range). The results are shown in Fig. 7. In the fourth test case, input sig-
`
`nals with 12.5% negative-sequence imbalance at the fundamental frequency were used, and the
`
`initial value for the PI’s output was set to 0.5. The results of this test case are shown in Fig. 8.
`
`Simulation
`Experimental
`
`0.05
`
`0.1
`
`0.15
`(a)
`
`0.2
`
`0.25
`
`0.3
`
`t(s)
`
`Simulation
`Experimental
`
`1
`
`0.5
`
`0
`
`-0.5
`
`-1
`
`0
`
`1.4
`
`1.2
`
`1
`
`0.8
`
`0.6
`
`0.4
`
`0
`
`0.05
`
`0.1
`
`0.15
`(b)
`
`0.2
`
`0.25
`
`0.3
`
`t(s)
`
`
`
`Fig. 7 Experimental and simulation results for signal balanced and
`the initial value for the PI’s output equal to 0.5: (a) error (b)PI output
`
`error
`
`f(pu)
`
`error
`
`f(pu)
`
`Simulation
`Experimental
`
`0.1
`
`0.2
`
`0.3
`(a)
`
`0.4
`
`0.5
`
`0.6
`
`t(s)
`
`Simulation
`Experimental
`
`1
`
`0.5
`
`0
`
`-0.5
`
`-1
`
`0
`
`1.4
`
`1.2
`
`1
`
`0.8
`
`0.6
`
`0.4
`
`0
`
`0.1
`
`0.2
`
`0.3
`(b)
`
`0.4
`
`0.5
`
`t(s)
`
`0.6
`
`
`
`Fig. 8 Experimental and simulation results for signal unbalanced
`and the initial value for the PI’s output equal to 0.5: (a) error (b)PI
`output
`
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`

`In these cases, where the PI’s output is initialized to 0.5, the PLL takes more time to lock in
`
`the desired frequency (~250ms for balanced signals and ~430ms for unbalanced signals) than
`
`the previous ones. This occurs because the initial frequency deviation is well outside the lock
`
`range. The ripple presents in the output frequency in the fourth test is smaller than three per-
`
`cent.
`
`The fifth test case has balanced input signals and the initial value for the PI’s output is equal
`
`to 1.5 (also outside the lock range). The results are shown in Fig. 9. The sixth test uses input
`
`signals unbalanced by 12.5% of negative-sequence component at the fundamental frequency
`
`1
`
`0.5
`
`0
`
`-0.5
`
`-1
`
`0
`
`1.6
`
`1.4
`
`1.2
`
`1
`
`0.8
`
`0.6
`
`error
`
`f(pu)
`
`Simulation
`Experimental
`
`0.05
`
`0.1
`
`0.15
`(a)
`
`0.2
`
`0.25
`
`0.3
`
`t(s)
`
`Simulation
`Experimental
`
`0
`
`0.05
`
`0.1
`
`0.15
`(b)
`
`0.2
`
`0.25
`
`0.3
`
`t(s)
`
`
`
`Vestas Ex 1036-p. 11
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`
`Fig. 9 Experimental and simulation results for signal balanced and
`the initial value for the PI’s output equal to 1.5: (a) error (b)PI output
`
`Simulation
`Experimental
`
`0.1
`
`0.2
`
`0.3
`(a)
`
`0.4
`
`0.5
`
`0.6
`
`t(s)
`
`Simulation
`Experimental
`
`0.1
`
`0.2
`
`0.3
`(b)
`
`0.4
`
`0.5
`
`0.6
`
`t(s)
`
`
`
`1
`
`0.5
`
`0
`
`-0.5
`
`-1
`
`0
`
`1.6
`
`1.4
`
`1.2
`
`1
`
`0.8
`
`0
`
`error
`
`f(pu)
`
`Fig. 10 Experimental and simulation results for signal unbalanced
`and the initial value for the PI’s output equal to 1.5: (a) error (b)PI
`output
`
`

`

`and the initial value for the PI’s output is equal to 1.5. The results are shown in Fig. 10. For
`
`the PI’s output initialized to 1.5, the time the PLL takes to lock to the desired frequency is ap-
`
`proximated the same one as when the PI’s output is initialized to 0.5. The frequency ripple
`
`present in the sixth test is smaller than two percent.
`
`In all of the above tests, the PLL algorithm has successfully locked to the desired frequency,
`
`even in the presence of strong negative-sequence unbalances in the input voltages. With more
`
`than 10% of negative-sequence unbalance, the frequency jitter caused by this same unbalance
`
`remains around 1%. Based on the results obtained from the tests presented above, it can be
`
`Simulation
`Experimental
`
`0.5
`
`1
`
`1.5
`
`2
`(a)
`
`2.5
`
`3
`
`3.5
`t(s)
`
`4
`
`0.5
`
`1
`
`1.5
`
`2
`(b)
`
`2.5
`
`3
`
`Simulation
`Experimental
`
`3.5
`t(s)
`
`4
`
`
`
`1
`
`0.5
`
`0
`
`-0.5
`
`error
`
`-1
`0
`
`1.5
`
`1
`
`0.5
`
`0
`
`-0.5
`0
`
`f(pu)
`
`Fig. 11 Experimental and simulation results for 7% of sub-harmonic
`disturbance at 1Hz and the initial value for the PI’s output equal to
`zero: (a) error (b)PI output.
`
`Simulation
`Experimental
`
`0.25
`
`error
`
`0
`
`-0.25
`
`-0.5
`
`0
`
`0.1
`
`0.2
`
`0.3
`
`0.4
`
`0.5
`(a)
`
`0.6
`
`0.7
`
`0.8
`
`1
`
`0.9
`t(s)
`
`Simulation
`Experimental
`
`0.1
`
`0.2
`
`0.3
`
`0.4
`
`0.6
`
`0.7
`
`0.8
`
`0.5
`(b)
`
`0.9
`t(s)
`
`1
`
`
`
`1.1
`
`1.05
`
`1
`
`0.95
`
`0.9
`0
`
`f(pu)
`
`Fig. 12 Experimental and simulation results for 7% of sub-harmonic
`disturbance at 1Hz and the PI’s output is limited: (a) error (b)PI out-
`put
`
`Vestas Ex 1036-p. 12
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`
`

`

`said that the implemented PLL algorithm is very robust against negative-sequence unbalances
`
`coming from the three-phase input signals, up to an amount of 12.5% at least. The resulting
`
`VCO output signal will then always lock to the positive-sequence component of the input sig-
`
`nals, thus indicating that this very algorithm can be used as a positive-sequence voltage or cur-
`
`rent detector.
`
`
`
`Simulation
`Experimental
`
`0.5
`
`1
`
`1.5
`
`2
`(a)
`
`2.5
`
`3
`
`3.5
`t(s)
`
`4
`
`Simulation
`Experimental
`
`0.5
`
`1
`
`1.5
`
`2
`(b)
`
`2.5
`
`3
`
`3.5
`t(s)
`
`4
`
`
`
`1
`
`0.5
`
`0
`
`-0.5
`
`-1
`0
`
`0.2
`
`0.1
`
`0
`
`-0.1
`
`-0.2
`0
`
`error
`
`f(pu)
`
`Fig. 13 Experimental and simulation results for 10% of sub-
`harmonic disturbance at 1Hz and the initial value for the PI’s output
`equal to zero:
`(a) error (b)PI output
`
`Simulation
`Experimental
`
`0.1
`
`0.2
`
`0.3
`
`0.4
`
`0.5
`(a)
`
`0.6
`
`0.7
`
`0.8
`
`1
`
`0.9
`t(s)
`
`Simulation
`Experimental
`
`0.1
`
`0.2
`
`0.3
`
`0.4
`
`0.6
`
`0.7
`
`0.8
`
`0.5
`(b)
`
`0.9
`t(s)
`
`1
`
`
`
`1
`
`0.5
`
`0
`
`-0.5
`
`-1
`0
`
`1.4
`
`1.2
`
`1
`
`0.8
`0
`
`error
`
`f(pu)
`
`Fig. 14 Experimental and simulation results for 10% of sub-
`harmonic disturbance at 1Hz and the PI’s output is limited: (a) error
`(b)PI output
`
`Vestas Ex 1036-p. 13
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`
`

`

`B. Sub-harmonics
`
`Four tests have been carried out to verify the performance of the PLL control software in the
`
`presence of sub-harmonic oscillations at very low frequency (1Hz), under different initial con-
`
`ditions and limiting or not the PI controller’s output. The results of these tests are shown from
`
`Fig. 11 to Fig. 14.
`
`Fig. 11 and Fig. 12 show the results of the tests, which have used 7% of sub-harmonic distur-
`
`bance at 1Hz. In Fig. 11, the system starts from zero initial condition and the PI’s output is
`
`not limited. In Fig. 12, the PI’s output is limited and the initial value is within the limits.
`
`Simulation and experiments show that the PLL locks to the desired frequency in both cases.
`
`For the test results presented in Fig. 13 and Fig. 14, the sub-harmonic disturbance was 10% at
`
`1Hz. In Fig. 13 the initial value for PI’s output is zero and the output is not limited. In this
`
`case, the PLL fails to lock. This problem can be corrected if limits are introduced to the PI’s
`
`output, as shown in Fig. 14. The PLL output frequency then locks to the desired frequency,
`
`with only a few percent of frequency ripple.
`
`Simulation
`
`ExperimentalExperimental
`
`0.05
`
`0.1
`
`0.15
`(a)
`
`0.2
`
`0.25
`
`0.3
`
`t(s)
`
`Simulation
`
`ExperimentalExperimental
`
`1
`
`error
`
`0.5
`
`0
`
`-0.5
`
`0
`
`1.3
`1.2
`1.1
`1
`
`0.9
`
`f(pu)
`
`0
`
`0.05
`
`0.1
`
`0.15
`(b)
`
`0.2
`
`0.25
`
`0.3
`
`t(s)
`
`
`
`Fig. 15 Experimental and simulation results for harmonic distur-
`bance and the PI’s output is limited: (a) error (b)PI output
`
`Vestas Ex 1036-p. 14
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`
`

`

`C. Harmonics
`
`This test was accomplished to verify the performance of the PLL circuit in the presence of
`
`harmonic distortion. In this case, the line voltage signals were acquired from a common bus,
`
`to which a three-phase, full-bridge rectifier is also connected. These signals were contaminated
`
`by a fifth-order harmonic component of approximately 10% and an eleventh-order harmonic
`
`component of nearly 5%. The THD is approximately of 15% and the waveform of this voltage
`
`vab,ref
`
`vab,gen
`
`can be seen in
`
`Fig. 16 with the label of vab,ref.
`
`
`
`Fig. 15 shows the simulation and the experimental results obtained from the present test. In
`
`this case, the PI’s output is limited and the initial value for its output is equal to 1.0. The ex-
`
`perimental results agree very well to the simulation results.
`
`The application of this PLL circuit in the control of a power electronics device was also dem-
`
`onstrated in this test, with the correct switching of a PWM inverter supplying a resistive load.
`
`Vestas Ex 1036-p. 15
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`
`

`

`vab,ref
`
`vab,gen
`
`In
`
`
`
`Fig. 16, the distorted signal labeled vab,ref is the reference signal for the PLL circuit and the
`
`voltage labeled vab,gen is the (filtered) voltage generated by PWM switching of the inverter.
`
`The PLL circuit has successfully locked, and the inverter is synchronized with the fundamental
`
`component of the line voltage.
`
`V. CONCLUSIONS
`
`This paper describes a robust synchronizing PLL circuit, which has been analyzed and im-
`
`plement by software. The experimental results obtained from several tests have been com-
`
`vab,ref
`
`vab,gen
`
`Fig. 16 Experimental results for harmonic disturbance of
`the switching of an inverter PWM
`
`
`
`Vestas Ex 1036-p. 16
`Vestas v GE
`
`

`

`pared to MATLAB® simulations, showing good agreement. Some aspects related to the sys-
`
`tem’s ability to maintain synchronism in the presence of sub-harmonics, harmonics and nega-
`
`tive-sequence unbalances have been investigated, and the implemented algorithm revealed to
`
`be robust even under such circumstances. When the input signals are contaminated with nega-
`
`tive-sequence components, the implemented PLL is able to produce output signals locked to
`
`the positive sequence components only. This makes this PLL circuit suitable for positive-
`
`sequence detection of voltages and/or currents in power electronics equipment.
`
`VI. ACKNOWLEDGEMENTS
`
`The authors are grateful to Brazilian Research Council (CNPq) for the financial support.
`
`VII. REFERENCES
`
`[1] L.N. Arruda, S.M. Silva and B.J.C. Filho, “PLL structure for utility connected systems”,
`
`Conference Record of the Thirty-Sixth IEEE-IAS Annual Meeting (2001), Volume 4,
`
`Page(s): 2655-2660.
`
`[2] C. Zhan, C. Fitzer, V.K. Ramachandaramurthy, A. Arulampalam, M. Barnes and N. Jen-
`
`kins, “Software phase-locked loop applied to dynamic voltage restore (DVR)”, IEEE
`
`Power Engineering Society Winter Meeting, 2001, Volume 3, Page(s): 1033-1038.
`
`[3] S. Chung, “A phase tracking system for three phase utility interface inverters”, IEEE
`
`Transactions on Power Electronics, Volume 15 Issue 3, May 2000 Page(s): 431-438.
`
`[4] R.E. Best, “Phase Locked Loops – Theory, Design and Applications”, ISBN 0-07-005050-
`
`3, McGraw-Hill, 1984.
`
`[5] V. Kaura and V. Blasko, “Operation of a phase locked loop system under distorted utility
`
`conditions”, IEEE Transactions on Industry Applications, Volume 33 Issue 1, Jan.-Feb.
`
`1997 Page(s): 58–63.
`
`Vestas Ex 1036-p. 17
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`
`

`

`[6] K.J. Åström and B. Wittenmark, “Computer-Controlled Systems Theory and Design”, 3rd
`
`Edition, ISBN 0-13-314899-8, Prentice-Hall, 1984
`
`[7] H. Akagi, Y. Kanagawa e A. Nabae, “Instantaneous Reactive Power Compensator Com-
`
`prising Switching Devices Without Energy Storage Components”, IEEE Trans. Industry
`
`Applications, vol. IA-20, May-June, 1984.
`
`[8] E.H. Watanabe, R.M. Stephan e M. Aredes, “New Concepts of Instantaneous Active and
`
`Reactive Powers in Electrical Systems with Generic Loads,” IEEE Trans. Power Delivery,
`
`vol. 8, No. 2, April 1993, pp. 697-703.
`
`[9] E.M. Sasso, G.G. Sotelo, A.A. Ferreira, E.H. Watanabe, M. Aredes, P.G. Barbosa, “Inves-
`
`tigação dos Modelos de Circuitos de Sincronismo Trifásicos Baseados na Teoria das
`
`Potências Real e Imaginária Instantâneas (p-PLL e q-PLL)”, Proceedings of the XV CBA,
`
`Natal-RN, Brazil, September 2002, pp. 480-485 (in portuguese).
`
`BIOGRAPHIES
`
`Diogo Rodrigues da Costa Junior was born in Rio de Janeiro State, Brazil, on June 12, 1980. He received the
`B.Sc. degree from Federal University of Rio de Janeiro, in 2003. He is involved in research projects of the
`Power Electronic Laboratory from the COPPE/UFRJ, since 2001. He is enrolled in M.Sc. at COPPE/UFRJ in
`Power Electronics and, with Dr. Rolim and Dr. Aredes, is developing the digital control of a prototype of a
`Dynamic Voltage Restorer.
`Luís Guilherme Barbosa Rolim was born in Niterói, Brazil, in 1966. He received the B.S. and M.S. degrees
`from the Federal University of Rio de Janeiro (UFRJ), Rio de Janeiro, Brazil, and the Dr.-Ing. degree from the
`Technical University Berlin, Berlin, Germany, in 1989, 1993, and 1997, respectively, all in electrical enginee-
`ring. Since 1990, he has been a Faculty Member of the Electrical Engineering Department, Escola Politécnica,
`UFRJ, where he teaches and conducts research on power electronics, drives, and microprocessor control. He is
`a member of the Power Electronics Research Group at COPPE/UFRJ and has authored more than 20 papers
`published in brazilian and international conference proceedings and technical journals.
`Maurício Aredes (S’94, M’97) was born in São Paulo State, Brazil, on August 14, 1961. He received the
`B.Sc. degree from Fluminense Federal University, Rio de Janeiro State in 1984, the M.Sc. degree in Electrical
`Engineering from Federal University of Rio de Janeiro in 1991, and the Dr.-Ing. Degree (magna cum laude)
`from Technische Universität Berlin in 1996. From 1985 to 1988 he worked at the Itaipu HVDC Transmission
`System and from 1988 to 1991 in the SCADA Project of Itaipu Power Plant. From 1996 to 1997 he worked wi-
`thin CEPEL – Centro de Pesquisas de Energia Elétrica, Rio de Janeiro, as R&D Engineer. In 1997, he became
`an Associate Professor at the Federal University of Rio de Janeiro, where he teaches Power Electronics. His
`main research area includes HVDC and FACTS systems, active filters, Custom Power and Power Quality Issu-
`es. Dr. Aredes is a member of the Brazilian Society for Automatic Control and the Brazilian Power Electronics
`Society.
`
`Vestas Ex 1036-p. 18
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`
`

`

`List of Figure Captions
`
`Fig. 1 Block diagram of basic PLL structure
`
`Fig. 2 Small-signal block diagram.
`
`Fig. 3 Simulation results for sub-harmonic disturbances at 1Hz:
`
`Fig. 4 Block-diagram representation of the implemented algorithm
`
`Fig. 5 Experimental and simulation results for signal balanced and the initial value for the PI’s output equal to
`
`1: (a) error (b)PI output
`
`Fig. 6 Experimental and simulation results for signal unbalanced and the initial value for the PI’s output equal
`
`to 1:(a) error (b)PI output
`
`Fig. 7 Experimental and simulation results for signal balanced and the initial value for the PI’s output equal to
`
`0.5: (a) error (b)PI output
`
`Fig. 8 Experimental and simulation results for signal unbalanced and the initial value for the PI’s output equal
`
`to 0.5: (a) error (b)PI output
`
`Fig. 9 Experimental and simulation results for signal balanced and the initial value for the PI’s output equal to
`
`1.5: (a) error (b)PI output
`
`Fig. 10 Experimental and simulation results for signal unbalanced and the initial value for the PI’s output
`
`equal to 1.5: (a) error (b)PI output
`
`Fig. 11 Experimental and simulation results for 7% of sub-harmonic disturbance at 1Hz and the initial value
`
`for the PI’s output equal to zero: (a) error (b)PI output.
`
`Fig. 12 Experimental and simulation results for 7% of sub-harmonic disturbance at 1Hz and the PI’s output is
`
`limited: (a) error (b)PI output
`
`Fig. 13 Experimental and simulation results for 10% of sub-harmonic disturbance at 1Hz and the initial value
`
`for the PI’s output equal to zero: (a) error (b)PI output
`
`Fig. 14 Experimental and simulation results for 10% of sub-harmonic disturbance at 1Hz and the PI’s output is
`
`limited: (a) error (b)PI output
`
`Fig. 15 Experimental and simulation results for harmonic disturbance and the PI’s output is limited: (a) error
`
`(b)PI output
`
`Fig. 16 Experimental results for harmonic disturbance of the switching of an inverter PWM
`
`
`
`Vestas Ex 1036-p. 19
`Vestas v GE
`
`