United States Patent [19J
`Harari et al.
`
`I IIIII IIIIIIII Ill lllll lllll lllll lllll lllll lllll lllll lllll 111111111111111111
`US005887145A
`[11] Patent Number:
`[45] Date of Patent:
`
`5,887,145
`Mar. 23, 1999
`
`[54]
`
`[75]
`
`REMOVABLE MOTHER/DAUGHTER
`PERIPHERAL CARD
`
`Inventors: Eliyahou Harari, Los Gatos; Daniel C.
`Guterman, Fremont; Robert F.
`Wallace, Sunnyvale, all of Calif.
`
`[73] Assignee: SanDisk Corporation, Sunnyvale,
`Calif.
`
`[21]
`
`Appl. No.: 781,539
`
`[22]
`
`Filed:
`
`Jan. 9, 1997
`
`5,457,590
`5,475,441
`5,488,433
`5,584,043
`5,611,057
`5,615,344
`
`10/1995 Barrett et al. ........................... 360/133
`12/1995 Paralski et al. ......................... 348/552
`1/1996 Washino et al. ........................ 395/722
`12/1996 Burkart ................................... 395/882
`3/1997 Pecone et al. .......................... 395/282
`3/1997 Corder .................................... 395/309
`
`FOREIGN PATENT DOCUMENTS
`
`W09300658
`
`1/1993 WIPO .
`
`Primary Examiner-Meng-Ai T. An
`Assistant Examiner-Walter D. Davis, Jr.
`Attorney, Agent, or Firm-Majestic, Parsons, Siebert &
`Hsue
`
`Related U.S. Application Data
`
`[57]
`
`ABSTRACT
`
`[63]
`
`[51]
`[52]
`
`[58]
`
`[56]
`
`Continuation of Ser. No. 462,642, Jun. 5, 1995, abandoned,
`which is a continuation of Ser. No. 398,856, Mar. 6, 1995,
`abandoned, which is a continuation of Ser. No. 151,292,
`Nov. 12, 1993, abandoned, which is a continuation-in-part of
`Ser. No. 115,428, Sep. 1, 1993, abandoned.
`Int. Cl.6
`...................................................... G06F 12/00
`U.S. Cl. .......................... 395/282; 395/833; 395/882;
`711/103; 711/115
`Field of Search ..................................... 395/800, 282,
`395/283, 309, 800.01, 800.37, 500, 833,
`821, 882; 711/2, 103, 115; 365/52, 99
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`4,837,628
`5,018,017
`5,293,236
`5,343,319
`5,438,359
`
`6/1989 Sasaki ..................................... 358/209
`5/1991 Sasaki et al.
`........................... 358/209
`3/1994 Adachi et al. .......................... 348/231
`8/1994 Moore ..................................... 359/152
`8/1995 Aoki ........................................ 348/207
`
`A peripheral card having a Personal Computer ("PC") card
`form factor and removably coupled externally to a host
`system is further partitioned into a mother card portion and
`a daughter card portion. The daughter card is removably
`coupled to the mother card. In the preferred embodiment, a
`low cost flash "floppy" is accomplished with the daughter
`card containing only flash EEPROM chips and being con(cid:173)
`trolled by a memory controller residing on the mother card.
`Other aspects of the invention includes a comprehensive
`controller on the mother card able to control a predefined set
`of peripherals on daughter cards connectable to the mother
`card; relocation of some host resident hardware to the
`mother card to allow for a minimal host system; a mother
`card that can accommodate multiple daughter cards; daugh(cid:173)
`ter cards that also operates directly with hosts having
`embedded controllers; daughter cards carrying encoded data
`and information for decoding it; and daughter cards with
`security features.
`
`22 Claims, 9 Drawing Sheets
`
`HOST SYSTEM 1
`
`200
`"-.......
`
`100
`
`Removable
`42 Mother card
`
`rh
`212 u
`
`.-~- •
`
`12 41 14
`
`10
`
`Removable
`Daughter card
`
`P. 24
`
`HOST SYSTEM n
`
`200'
`"-.......
`
`42'
`
`..,._ ----) - - - - ____ _j
`
`41' 14'
`
`1
`
`KINGSTON 1004
`
`

`

`U.S. Patent
`
`Mar. 23, 1999
`
`Sheet 1 of 9
`
`5,887,145
`
`200
`~
`
`r-----------------
`'
`
`2121
`
`HOST SYSTEM
`
`100
`
`Removable
`Mother card
`
`Removable
`Daughter
`
`.. ,..
`
`12
`
`14
`
`10
`
`4
`
`\._ 20
`
`FIG. 1
`
`40
`
`MOTHER CARD
`
`10
`
`DAUGHTER CARD
`30
`
`20
`
`--,
`~
`I I , ,
`
`---,
`~ -
`~ ---,
`
`I I
`I
`--,
`
`Memory
`Interface
`
`ROM
`
`---------------------'
`
`I
`
`Mem
`
`_,
`-, =, _,
`=' CJ CJ
`_,
`I -, CJ CJ
`=, _, -,
`
`I
`I
`I
`
`I
`I
`I
`
`L - -
`
`2
`
`14
`
`4
`
`FIG. 3
`
`2
`
`

`

`U.S. Patent
`
`Mar. 23, 1999
`
`Sheet 2 of 9
`
`5,887,145
`
`16
`
`MOTHER CARD
`
`10
`
`DAUGHTER CARD
`
`20
`
`,----------------------- -
`I ,_ ,_
`
`r - - - - - - .
`I
`
`I
`
`- - - - - - - .
`I
`!
`I
`I
`1 ______ 1
`
`r1
`I
`I
`I
`I
`
`'------~
`-------
`'
`
`- - - - - - -
`I
`I
`l _ ___ __ j
`
`r1
`I
`I
`I
`I
`
`'
`
`I
`
`28
`
`...
`
`_I
`
`28
`
`,-,-,= ,-,-,, ,, ,, ,_
`
`--<
`--,
`::::i
`--<
`--,
`::::i
`I I
`I
`I
`I
`I
`-------
`I
`r1
`:::::!
`I
`I
`._-t-ii~-i-t-+-----"~--~~-
`
`12 14
`
`19
`
`4
`
`FIG. 2A
`
`16
`
`10
`
`18
`
`14
`
`FIG. 28
`
`3
`
`

`

`U.S. Patent
`
`Mar. 23, 1999
`
`Sheet 3 of 9
`
`5,887,145
`
`56
`
`Flash Memory
`
`,--------
`
`Control/Clock
`
`1
`
`I
`I
`I
`ChipN I
`I
`I
`Program Voltage
`_______ _J
`
`Flash
`Chip 1
`
`Flash
`
`Erase Voltage
`
`24
`
`\
`20
`
`Flash System Controller
`
`,--------
`
`Host Interface
`
`Memory .
`Interface
`
`r - - - - - -,
`1 Buffer ,
`.._._.._~' SRAM :
`I
`I
`
`, ______ .J
`
`54
`
`55
`
`Processor
`
`Power
`Converter
`
`I EPROM I
`
`~ - - - - - - _1
`
`5
`
`12
`
`L -
`
`-
`
`-
`
`52
`
`-
`
`-
`
`58
`
`I
`I
`- - \ - _J
`
`40
`
`FIG. 4
`
`4
`
`

`

`U.S. Patent
`
`Mar. 23, 1999
`
`Sheet 4 of 9
`
`5,887,145
`
`41
`
`MOTHER CARD
`
`10
`
`r.:---::-i
`I Host Interface JI
`~ I Processor
`~ I Daughtercard j
`
`j
`
`j
`
`Interface
`
`j
`
`::i
`: :
`I I ROM I I
`I I j
`~ I
`I
`Power
`Converter
`L ___ _J
`
`r----------------------
`
`1
`
`I
`I - - - - - - - - - - - - - - - - - - - - - -1
`
`_,
`-, =, _,
`-,
`... ~._--.... ~:
`I -, =, _,
`
`I
`I
`
`I
`I
`
`-::,
`
`DAUGHTER CARD
`
`20
`
`MAGNETIC
`HARD DISK
`
`=: COMMUNICATION
`..,.~.,__--1 ... .- : :
`DEVICE
`
`I
`
`I
`I
`
`FIG. 5A
`
`5
`
`

`

`U.S. Patent
`
`Mar. 23, 1999
`
`Sheet 5 of 9
`
`5,887,145
`
`MOTHER CARD
`
`10
`
`/
`r----------------------
`
`-
`
`41
`l
`\
`
`Comprehensive
`Controller
`
`- '
`--I
`--,
`~
`--I
`--,
`~
`I I
`I I
`I I
`I
`--,
`~ Functional
`--I
`--,
`- -
`Module(s)
`
`\
`
`L 42
`
`-
`
`I
`- - - - - - - - - - - - - - - - - - - - - - -
`
`I
`
`FIG. 58
`
`6
`
`

`

`U.S. Patent
`
`Mar. 23, 1999
`
`Sheet 6 of 9
`
`5,887,145
`
`41
`
`MOTHER CARD
`
`10
`
`- -
`
`,
`
`...... --,
`...... --,
`
`:::::J
`
`:::::J
`I I
`I I
`I I
`I
`--,
`:::::J
`
`...... --,
`
`Comprehensive
`Controller
`
`r
`
`- - - - - - - - - - - - - - - - - ,
`
`I
`
`"Main"
`Memory
`
`I ~----------------------
`
`2
`
`60
`
`FIG. 6
`
`100
`
`HOST
`
`MOTHER CARD
`41
`
`I ROM I
`COMPREHENSIVE
`CONTROLLER
`
`OMA
`
`"MAIN" MEMORY
`
`212, 1
`
`14, 24
`
`(DRAM/SRAM/
`ROM/FLASH)
`32KB TO 32MB
`
`FIG. 7
`
`DAUGHTER CARD
`
`20
`
`REMOVABLE
`MEDIA
`
`(FLASH EEPROM,
`HARD DISK,
`ROM,
`FLOPPY,
`TAPE,
`
`7
`
`

`

`U.S. Patent
`
`Mar. 23, 1999
`
`Sheet 7 of 9
`
`5,887,145
`
`10
`
`14 82
`
`70
`
`80
`
`FIG. BA
`
`10
`
`14
`
`70
`
`FIG. BB
`
`8
`
`

`

`U.S. Patent
`
`Mar. 23, 1999
`
`Sheet 8 of 9
`
`5,887,145
`
`HOST SYSTEM 1
`
`I
`
`1
`
`-
`
`2121
`
`Removable
`42 Mother card
`
`200 "'
`..... -~-.
`
`- - - - - - - - -
`
`12 41 14
`
`10
`
`HOST SYSTEM n
`
`200'
`
`100
`
`Removable
`Daughter card
`
`\.
`20
`
`24
`
`~~ i-•
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`42'
`
`Com
`Ctrl
`
`I
`._ : __ __ __ _ _J
`
`I
`
`I
`
`I
`
`I
`I
`I
`__________ J
`
`41' 14'
`
`FIG. 9
`
`9
`
`

`

`U.S. Patent
`
`Mar. 23, 1999
`
`Sheet 9 of 9
`
`5,887,145
`
`200"
`
`HOST SYSTEM
`
`I
`1
`
`- - - - - - - -
`
`21(~
`
`42'
`
`Com
`Ctrl
`
`41' 14'
`
`100
`
`Removable
`42 Mother card
`
`Removable
`Daughter card
`
`Com
`Ctrl
`
`+
`
`_ _.
`,-.
`
`12 41
`
`14
`
`10
`
`I
`
`I
`
`I
`
`I
`I
`
`\.
`20
`
`24
`
`I
`+--:---------_J
`
`I
`
`I
`
`FIG. 10
`
`220
`
`24
`
`FIG. 11
`
`\_ 20
`
`10
`
`

`

`5,887,145
`
`1
`REMOVABLE MOTHER/DAUGHTER
`PERIPHERAL CARD
`
`This is a continuation of application Ser. No. 08/462,642,
`filed Jun. 5, 1995, now abandoned, which is a continuation
`of application Ser. No. 08/398,856, filed Mar. 6, 1995, now
`abandoned, which is a continuation of application Ser. No.
`08/151,292 filed Nov. 12, 1993, now abandoned, which is a
`continuation-in-part of application Ser. No. 08/115,428 filed
`Sep. 1, 1993, now abandoned.
`
`BACKGROUND OF THE INVENTION
`
`This invention relates generally to host computer systems
`and peripherals. More specifically, the peripherals have a
`Personal Computer ("PC") card form factor, the card being 15
`externally and removably coupled to a host system. The
`invention relates to structures and configurations of such a
`card, particularly for implementing mass storage peripherals
`such as electrically erasable programmable read-only(cid:173)
`memories (EEPROM) or Flash EEPROM system.
`Computer systems typically use high speed semiconduc(cid:173)
`tor random access memory (RAM) for storing temporary
`data. However, RAM is volatile memory; that is, when
`power to the computer system is disconnected, data stored in
`RAM is lost.
`For long-term, non-volatile storage, two types of memory
`are typically employed. One type is magnetic disk memory
`intended for mass storage with practically unlimited number
`of write operations. The other type is semiconductor
`memory, traditionally intended for storing a relatively small
`amount of data (e.g. system parameters) with no or limited
`number of write operations.
`When mass storage is desired, magnetic disk drives,
`whether fixed or removable, are generally more economical
`and more amenable to write operations than solid-state
`memory. Typically, a computer system employs a combina(cid:173)
`tion of fixed and removable (floppy) magnetic disks.
`However, they are relatively slow, bulky and require high
`precision moving mechanical parts. Consequently, they are 40
`not rugged and are prone to reliability problems, as well as
`being slower and consuming significant amounts of power.
`The undesirable features of magnetic disks become even
`more acute with the advent of portable and mobile comput(cid:173)
`ing. Disk drives are obstacles in the quest towards greater 45
`portability and lower power consumption of computer sys(cid:173)
`tems.
`Non-volatile semiconductor or solid-state memories have
`the advantage of being speedy, light-weight and low-power.
`Examples are ROM, EEPROM and Flash EEPROM which 50
`retain their memory even after power is shut down.
`However, ROM and PROM cannot be reprogrammed.
`UVPROM cannot be erased electrically. EEPROM and
`Flash EEPROM do have the further advantage of being
`electrically writable ( or programmable) and erasable. 55
`Traditionally, these semiconductor memories has been
`employed in small amount for permanent storage of certain
`computer system codes or system parameters that do not
`change.
`There is currently underway an effort to apply non- 60
`volatile Flash EEPROM memory systems for mass storage
`applications. For example, they are intended to replace
`either of the existing fixed or removable floppy magnetic
`disk systems, or both. Such systems are disclosed in com(cid:173)
`monly assigned and copending U.S. patent application Ser. 65
`No. 07/684,034, filed Apr. 11, 1991, COMPUTER
`MEMORY CARD HAVING A LARGE NUMBER OF
`
`2
`EEPROM INTEGRATED CIRCUIT CHIPS AND
`MEMORY SYSTEMS WITH SUCH CARDS, now aban(cid:173)
`doned and Ser. No. 07/736,732 filed Jul. 26, 1991, COM(cid:173)
`PUTER MEMORY CARDS USING FLASH EEPROM
`5 INTEGRATED CIRCUIT CHIPS AND MEMORY(cid:173)
`CONTROLLER SYSTEMS, now abandoned, a continua(cid:173)
`tion thereof being granted as U.S. Pat. No. 5,663,901.
`Relevant portions of these disclosures are incorporated
`herein by reference. It is now becoming possible to fabricate
`10 a few megabytes of Flash EEPROM on a single semicon(cid:173)
`ductor integrated circuit chip. As a result, several megabytes
`to tens of megabytes of memory can readily be packaged in
`a physically compact memory card, the size of an ordinary
`credit card.
`Indeed, a series of industry "PC Card Standards" are now
`being promulgated by the Personal Computer Memory Card
`International Association (PCMCIA), Sunnyvale, Calif.,
`U.S.A. Excerpts of the current PCMCIA Standards, Edition
`Release 2, dated November 1992 are incorporated herein by
`20 reference. These standards set mechanical (Types I, II and
`III) and technical (Revision 1.0, 2.0) specifications for a
`memory card and its connection to a host.
`The PCM CIA card has the form factor approximately the
`size of a credit card and is externally connectable to a host
`25 computer system via the. PCMCIA interface. Originally,
`these cards were intended as memory card add-ons for
`portable or mobile computing systems. Soon thereafter their
`standards were expanded to accommodate other peripherals
`such as modems, network adapters, and hard disks. Thus,
`30 PCMCIA Type I card is 3.3 mm in overall outside thickness,
`less than 5.5 cm in width, and less than 9.0 cm in length.
`Types II and III have similar dimensions, except Type II card
`is 5 mm thick and Type III card is 10.5 mm thick. Revision
`1.0 of the technical specification dated September 1990, is a
`35 memory-only standard for memory card applications. Revi(cid:173)
`sion 2.0, dated September 1991, is a standard with added
`input/output (1/0) capabilities and software support suitable
`for other non-memory types of peripherals.
`In memory card applications, such PC cards have been
`commercially implemented primarily using either ROM or
`SRAM, with SRAM made non-volatile through backup
`battery. These solid-state memories operate and function
`under similar conditions as RAM, in that they are directly
`connected to the host's bus and addressable by the host's
`processor. Thus, similar to RAM, they can be simply added
`to a host computer system without additional hardware or
`software.
`On the other hand, PC cards using EEPROM and Flash
`EEPROM have quite different properties and operating
`requirements that make their incorporation into a host com(cid:173)
`puter system not as straight forward. Typically, additional
`hardware such as a controller and software are required to
`control the operations of the EEPROM or Flash EEPROM.
`The controller generally provides the necessary voltage
`conditions for the various memory operations. In more
`sophisticated implementations, it can communicate with a
`host via a standard disk drive interface, store the data under
`a prescribed file structure in the Flash memory (e.g. com(cid:173)
`patible with a standard disk operation system), and handle
`any errors that may arise.
`The requirement for additional support hardware (e.g.
`controller) and software (e.g. microcode or firmware and
`drivers) in these devices poses issues of cost and inflexibility
`in memory configuration as well as system updating and
`upgrading. For example, when Flash EEPROM PC cards are
`used to replace magnetic floppies or other removable
`
`11
`
`

`

`5,887,145
`
`3
`storage, the additional support hardware to implement the
`control functions may contribute significantly to the cost and
`other overhead of the product relative to the memory capac(cid:173)
`ity they provide.
`Similar considerations also apply to other types of
`peripherals, such as hard disks, modems and network adapt(cid:173)
`ers. Their support hardware and software tend to add cost,
`overhead and inflexibility to the final products.
`Accordingly, it is a general object of the invention to
`provide a peripheral in the form of a PC card that can be
`removably connected to a host system from the external of
`the host system, and that is cost-effective and flexible in
`configuration.
`It is an object of the invention to provide such a PC card
`with a specific type of semiconductor memory system
`having non-volatility, ease of erasing and rewriting, speed of
`access, and further being compact, light-weight, low power,
`low cost, reliable, and flexible in configuration.
`It is another object of the invention to provide a remov(cid:173)
`able memory card that is removably coupled externally to a
`host system via a standard interface such as a PCMCIA
`interface.
`It is another object of the invention to provide a compre(cid:173)
`hensive PC card that is adapted for use in a number of 25
`peripheral applications.
`It is a particular object of the invention to provide low cost
`Flash EEPROM memory cards, for example to replace
`floppy disks, magnetic tapes, or photographic recording
`films.
`It is another object of the invention to provide a remov(cid:173)
`able PC card that can accommodate components off-loaded
`from the host system in order to minimize the size and cost
`of the host system and to provide flexibility in system
`configuration.
`It is yet another object of the invention to provide a
`removable card that can interface either directly to a host
`system via an interface native to the card or indirectly via a
`standard interface to the host system.
`It is yet another object of the invention to provide a 40
`removable card that stores encoded data that can be decoded
`when the card is relocated from one host system to another.
`
`SUMMARY OF THE INVENTION
`
`These and additional objects are accomplished by the
`various aspects of the present invention, either alone or in
`combination, the primary aspects being briefly summarized
`as below.
`The externally removable PC card is constituted from a
`mother card portion and a daughter card portion. The
`daughter card portion is removably coupled mechanically
`and electrically to the mother card by means of a mother/
`daughter interface. The mother card portion can be remov(cid:173)
`ably coupled to a host system externally by means of a
`standard interface that provides both mechanical and elec(cid:173)
`trical connection. In operation, the mother card portion and
`the daughter card portion are coupled by the mother/
`daughter interface to form an integral PC card, and the
`integral PC card is removably coupled to the host system.
`Partitioning the externally removable PC card into a
`mother card and daughter card portion allows the functional
`components of a peripheral implemented on a PC card to be
`advantageously partitioned.
`According to one aspect of the invention, the peripheral
`implemented on the PC card is a flash EEPROM system,
`comprising flash EEPROM chips and supporting hardware
`
`4
`circuits that form a controller for controlling the operations
`of the flash EEPROM and for interfacing to the host system.
`The flash EEPROM system is partitioned such that the
`controller resides on the mother card and the flash EEPROM
`5 chips reside on the daughter card.
`In this way, a more cost-effective memory system is
`possible, especially in applications where magnetic floppy
`disks are to be replaced. This is because each daughter card
`containing only flash EEPROM acts essentially like a semi-
`10 conductor flash EEPROM "floppy disk", and need not have
`a controller on it. The one controller on the mother card can
`then serve any number of these flash EEPROM "floppy
`disks". The cost of each flash EEPROM "floppy disk" is
`therefore significantly reduced by elimination of the con-
`15 troller on the "floppy disk" itself. The other advantage is an
`increase in system flexibility. The user can add or decrease
`memory capacity by choosing among daughter cards with
`various amount of installed memory chips. Also, with each
`update or upgrade of the controller, only the mother card
`20 need be replaced, the daughter card "floppy disk" being fully
`usable with the new mother card.
`According to another aspect of the invention, a PC card is
`implemented with a comprehensive mother card portion
`containing the common functional components of a number
`of peripherals. Each peripheral then has the rest of the
`functional components residing on a daughter card. For
`example, a magnetic hard disk, a modem, and a network
`adapter all have common functional components similar to
`that of a flash EEPROM system, such as a host interface, a
`30 processor, and a ROM. By moving these common functional
`components to a comprehensive mother card, each indi(cid:173)
`vidual peripheral will have less components on the daughter
`card, thereby reducing cost.
`According to another aspect of the invention, some of the
`35 hardware originally residing in the host system is relocated
`to the mother card. One example of such a hardware is
`system memory (DRAM, SRAM, or flash) or even the host
`microprocessor. The relocation is advantageous because
`most small palmtop/notebook computers will not have suf-
`ficient room (i.e. Motherboard space) to include a lot of
`system memory. Furthermore, these units are too small for
`users to open up and upgrade with memory SIMM modules.
`Also, most manufacturers prefer to ship out the lowest cost
`base unit with minimum memory. This can be accomplished
`45 by using the Mother/daughter PC card, with the mother card
`carrying the controller and main memory ( capacities can be
`e.g. 0.5 MB, 1 MB, 2 MB, 4 MB, 8 MB, etc.), and the
`daughter card carrying either flash memory "floppy drive" or
`a small form factor magnetic hard disk (e.g. just the head,
`50 disk and motor assembly portions of a 1.8" or 1.3" hard disk
`without its controller logic), or a microfloppy, or even a
`miniature tape backup drive. Essentially, the Mother/
`daughter PC card contains all the memory requirements of
`the host system, i.e. the palmtop/notebook computer, which
`55 will free up precious space on the computer motherboard.
`According to another aspect of the invention, the mother
`card is adapted to removably receive a plurality of daughter
`cards. In this case, more than one mother/daughter connector
`may be provided on the mother card for removably receiving
`60 a plurality of daughter cards. The same controller on the
`mother card controls and services any number of daughter
`cards that are coupled to it. In one embodiment where the
`daughter cards are flash EEPROM, they are all controlled by
`the same controller on the mother card. This is similar to
`65 having a multiple floppy drive capability. In another embodi(cid:173)
`ment where the daughter cards are a mixture of peripherals,
`such as flash memory and a modem or other communication
`
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`5,887,145
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`5
`
`10
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`6
`FIG. 2B is a partial cross-sectional view of the mother
`card along the line 2B-2B shown in FIG. 2A;
`FIG. 3 illustrates a partitioning of the functional compo(cid:173)
`nents of a flash EEPROM system between the mother card
`and the daughter card;
`FIG. 4 is a system block diagram illustrating in more
`detail the functional components of a flash EEPROM system
`and related data and control paths, according to a preferred
`embodiment;
`FIG. SA illustrates schematically an integrated controller
`on the mother card for controlling a variety of peripherals on
`daughter cards that may be connected to it;
`FIG. SB illustrates a comprehensive mother card with
`additional functionalities provided by one or more func(cid:173)
`tional modules;
`FIG. 6 illustrates schematically the relocation of host
`"main memory" onto the mother card;
`FIG. 7 is a system block diagram illustrating the memory
`20 partition and related data and control paths among a host,
`mother card and daughter card;
`FIG. SA is an exploded view showing the mother card
`removably connectable to a daughter card, according to one
`aspect of the invention;
`FIG. SB is an exploded view showing the mother card
`removably connectable to a plurality of daughter cards,
`according to another aspect of the invention;
`FIG. 9 illustrates a removable daughter card that can
`30 interface either directly to a host system via an interface
`native to the daughter card or indirectly via a mother card
`removably coupled to a standard interface of the host
`system;
`FIG. 10 illustrates a host system having both an interface
`native to the daughter card for receiving the daughter card
`directly, and a standard interface for receiving the daughter
`card via a mother card; and
`FIG. 11 illustrates schematically a removable daughter
`card containing identifying data.
`
`5
`peripherals such as LAN adapter, or wireless fax modem.
`The same controller acts as a coprocessor or a sub-host
`system services the mixture of peripherals coupled to it. For
`example, the controller can receive fax data through a fax
`modem daughter card and store it in a flash memory daugh-
`ter card.
`According to another aspect of the invention, the remov(cid:173)
`able daughter card has the option of working with a host
`system in conjunction with a mother card externally coupled
`to the host system. The mother card serves to furnish support
`components, such as a comprehensive controller and
`optional functional components, necessary for the operation
`of the peripheral device implemented on the daughter card.
`At the same time, it adapts the native interface of the
`daughter card to the standard interface of the host system. At 15
`the same time, the daughter card has the option of working
`directly with a host system via the native interface of the
`daughter card if the support components are built into the
`host system.
`In this manner, a comprehensive, removable daughter
`card functions with a host system either directly when the
`host system is customized with the support components or
`indirectly via a mother card having the support components
`thereon, the mother card being connectable to the host
`system via a standard interface. This provides flexibility and
`system compatibility on the one hand and economy and
`convenience on the other.
`According to another aspect of the invention, when the
`support components includes data encoding and decoding
`processing functions such as compression and
`decompression, encryption and decryption, the key or algo(cid:173)
`rithm for recovering the data is stored with the daughter
`card. In this way, irrespectively of how the data is encoded
`by one host system, when the daughter card is relocated to
`another host, the information for decoding it is always 35
`available.
`According to another aspect of the invention, the remov(cid:173)
`able daughter card has identifying data that is readable by
`the mother card or the host system coupled thereto. The 40
`identifying data includes information that identifies what
`type of peripheral device is implemented on the daughter
`card. In another embodiment, the identifying data includes
`an identity code assignable to the daughter card for opera(cid:173)
`tional expediency and security applications. The device type 45
`identification allows the support components such as a
`comprehensive controller as well as the host system to
`configure and adapt accordingly. It further provides a form
`of acknowledge signal in a connection protocol for the
`native interface of the daughter card. The unique identity 50
`code provides a basis for matching each removable daughter
`card to a specific host system or mother card, for managerial
`or security reasons.
`Additional objects, features and advantages of the present
`invention will be understood from the following description
`of the preferred embodiments, which description should be
`taken in conjunction with the accompanying drawings.
`
`25
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENT
`Semiconductor "Floppies"
`There are applications where a very low cost memory
`card is required, for example to replace floppy disks or tape
`or film. At the same time it is important that the memory card
`preserve the PCMCIAstandard interface to the host system.
`The present invention is to integrate a memory controller
`chipset on the memory card in a configuration that mini-
`mizes cost and provides maximum flexibility. To reduce the
`cost of the memory card to meet the cost requirements of a
`floppy card, it is necessary to either integrate the controller
`chips with the memory chip, which require greater simpli(cid:173)
`fication of the control functionality, or performing most of
`55 the control functions by the host CPU which makes this
`approach host dependent. To solve this problem a lower cost
`approach is proposed in which the memory card is made up
`of a mother card and a daughter card.
`FIG. 1 is a schematic representation of the mother/
`60 daughter PC card 100 that can be removably coupled
`externally to a host system 200, according to a general
`aspect of the invention.
`The PC card 100 comprises a mother card portion 10 and
`a daughter card portion 20. The mother card portion 10 is a
`65 PCMCIA form-factor PC card with the standard 68-pin
`connector 12 on one side and a native interface connector 14
`(typically less than 68 pins) on the other side. The mother
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a schematic representation of the mother/
`daughter PC card that can be removably coupled externally
`to a host system, according to a general aspect of the
`invention;
`FIG. 2A illustrates, according to one embodiment, a
`mother card having an integral back-to-back connector with
`one side serving as the standard connector and the other side
`being the native interface connector;
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`5,887,145
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`7
`card 10 can be removably connected to the host system 200
`by plugging the connector 12 to a connector 212 of the host
`system.
`The daughter card 10 has an edge connector 24 and it
`directly plugs into the mother card by mating with the
`connector 14 on the mother card.
`FIG. 2A illustrates, according to one embodiment, a
`mother card 10 having an integral, back-to-back, connector
`16 with one side serving as the standard connector 12 and
`the other side being the native interface connector 14. The 10
`integral connector 16 is formed in one step to reduce the cost
`of manufacturing. A PC board 18 provides a platform for
`mounting the integral connector 16 and mother card cir(cid:173)
`cuitry 19.
`FIG. 2B is a partial cross-sectional view of the mother 15
`card along the line 2B-2B shown in FIG. 2A. The PC board
`and the mounted mother card circuitry 19 such as a con(cid:173)
`troller chipset take up about half of the mother card's
`thickness. This leaves the other half for the integral connec-
`tor 16 and an inlay 21 for a daughter card to dock in. The 20
`integral connector 16 is mounted on the back side to one
`edge of the PC board 18. A daughter card can removably
`dock into the inlay 21.
`FIG. 3 illustrates a preferred partitioning of the functional
`components of a flash EEPROM system between the mother 25
`card and the daughter card. As discussed earlier, a flash
`EEPROM system typically requires additional hardware
`such as processor-based circuits forming a memory control-
`ler with software to control the operations of the Flash
`EEPROM.
`The daughter card 20 contains essentially flash EEPROM
`memory chip(s) 30 and associated decoupling capacitors.
`The daughter card is preferably a low cost molded card for
`mounting the flash EEPROM chips. The edge connector 24
`has a minimum of pin-count since communication with a
`peripheral is normally in serial form.
`The mother card 10 contains a memory controller 40 but
`does not contain any substantial amount of flash EEPROM
`mass storage. Preferred memory controllers are disclosed in
`and commonly assigned U.S. patent application, FLASH 40
`EEPROM SYSTEM, Ser. No. 07/963,837, filed Oct. 20,
`1992, now abandoned, a continuation thereof being granted
`as U.S. Pat. No. 5,671,229, and DEVICE AND METHOD
`FOR CONTROLLING SOLID-STATE MEMORY
`SYSTEM, Ser. No. 07/736,733, filed Jul. 26, 1991, now U.S.
`Pat. No. 5,430,859. Relevant portions of both disclosures are
`incorporated herein by reference.
`The controller 40 is typically composed of functional
`components such as a processor 50, driven by microcodes
`stored in a ROM 52. The small amount of ROM 52 could
`also be replaced by other types of non-volatile memory such
`as EEPROM or flash EEPROM. The controller interfaces
`with the host system via a host interface 54, and with the
`flash memory via a memory interface 56. In the preferred
`embodiment, the host interface 54 communicates with the
`host system 200 in accordance with the PCMCIA specifi(cid:173)
`cations or any other standard card interface. The controller
`may also include other functional components such as a
`power converter 58 for providing the necessary voltage
`conditions for the various memory operations. The func(cid:173)
`tional components are interlinked by an internal bus (not
`shown in FIG. 3). In practice, these functional components
`are implemented as a controller chipset.
`FIG. 4 is a system block diagram illustrating in more
`detail the functional components of a flash EEPROM system 65
`and related data and control paths, according to a preferred
`embodiment. The controller 40 is a flash system controller
`
`8
`on a mother card and controls flash memory on a daughter
`card. The flash system controller 40 interfaces with the host
`by means of the host interface 54 via the host connector 12.
`The host interface 54 typically includes a buffer memory for
`s buffering data between the host and the peripheral. In one
`embodiment it may also emulate a disk drive interface, so
`that the flash memory system appears like a magnetic disk
`drive to the host. An internal bus 55 interconnects the
`proces