AGILENT TECHNOLOGIES, INC.
`LegalhDepartment, DL429
`Intellectual Property Administration
`P- 0. Box 7599
`Loveland, Colorado 805370599
`
`,
`
`.
`
`'
`
`PATENT APPLICATION
`
`ATTORNEY DOCKET NO. 700302594
`
`'
`
`‘
`
`IN THE U.S. PATENT AND TRADEMARK OFFICE
`Patent Application Transmittal L tter
`
`COMMISSIONER FOR PATENTS
`PO Box 1450 .
`AI xandria, VA 22313-1450
`.
`Sir:
`Transmitted herewith for filing under 37 CFR 1.53(b) is a(n): (X) Utility
`
`(
`
`) DeSign
`
`.
`fl. _
`0
`E {I J.‘
`m 73‘0" i
`
`(x) original patent application,
`(
`) continuation-in—part application
`
`13 ES}.
`‘5\—"
`
`INVENTORlSl: Kong Weng Lee et al.
`
`I
`
`\
`
`TITLE:
`
`PACKAGING DEVICE FOR SEMICONDUCTOR DIE. SEMICONDUCTOR DEVICE
`INCORPORATING SAME AND METHOD OF MAKING SAME
`
`Enclosed are:
`
`(XI The Declaration and Power of Attorney.
`
`lx ) signed
`
`l
`
`l unsigned or partially signed
`
`’
`
`I sheets of drawings (one set)
`8
`(X)
`(
`) Form PTO-1449
`(
`)
`
`l Associate Power of Attorney
`(
`Information Disclosure Statement and Form PTO-1449
`
`I
`
`) Priority document(s)
`
`(
`
`)lOrherl
`
`(fee $
`
`)
`
`(1)
`FOR
`
`CLAIMS AS FILED BY OTHER THAN A SMALL ENTITY
`(2)
`(3)
`(4’
`NUMBER FILED
`NUMBER EXTRA
`RATE
`
`TOTAL CHARGES TO DEPOSIT ACCOUN
`
`TOTAL CLAIMS
`
`20 — 20
`
`INDEPENDENT
`CLAIMS
`ANY MULTIPLE
`DEPENDENT CLAIMS
`
`BASIC FEE: DesignI
`
`$330.00
`
`X$18
`
`X $84
`
`$280
`);Utility( $750.00 )
`
`TOTAL FILING FE.
`
`OTHER FEES
`
`this
`At any time during the pendency of
`to Deposit Account 50-1078.
`25;;
`Charge $
`application, please charge any fees required or credit any over payment to Deposit Account 50-1078
`pursuant to 37 CFR 1.25. Additionally please charge any fees to Deposit Account 50-1078 under 37
`CFR 1.16, 1.17,1.19, 1.20 and 1.21. A duplicate copy of this sheet is enclosed.
`
`"Ex ress Mail" label no.
`p
`
`2 2 717 905 US
`M—‘—
`
`I hereby certify that this is being deposited with the
`United States Postal Service "Express Mail Post
`Office to Addressee" service under 37 CFR 1.10 on
`the date indicated above and is addressed to:
`Commissioner
`for
`Patents,
`PO
`Box
`1450,
`Alexandria, VA 22313—1450.
`
` Date of Deposit June 27 2003
`
`-
`Respectfully ubmltted,
`
`BY
`
`Ian Han astle
`
`Bv
`Typed Name: Linda A. Iimura
`
`.
`
`'
`
`Attorney/Agent for ApplicantIsl
`Reg. No.
`34,075
`
`Date: June 27. 2003
`
`Telephone NO-i (650) 485-3015
`
`Nichia Exhibit 1004
`
`Page 1
`
`Nichia Exhibit 1004
`Page 1
`
`

`

`AGILENT TECHNOLOGIES, INC.
`LegalhDepartment, DL429
`Intellectual Property Administration
`P- 0. Box 7599
`Loveland, Colorado 805370599
`
`7
`
`ATTORNEY DOCKET NO. 700302594
`
`.
`
`'
`
`PATENT APPLICATION
`
`'
`
`‘
`
`IN THE U.S. PATENT AND TRADEMARK OFFICE
`Patent Application Transmittal L tter
`
`COMMISSIONER FOR PATENTS
`PO Box 1450 .
`AI xandria, VA 22313-1450
`
`Sir:
`Transmitted herewith for filing under 37 CFR 1.53(b) is a(n): (X) Utility
`
`(
`
`) DeSign
`
`.
`
`0
`fl.
`I—
`9"
`9"” gm i
`
`(x) original patent application,
`
`(
`
`) continuation-in—part application
`
`‘5\—"
`
`INVENTORlSl: Kong Weng Lee et al.
`
`I
`
`\
`
`TITLE:
`
`PACKAGING DEVICE FOR SEMICONDUCTOR DIE. SEMICONDUCTOR DEVICE
`INCORPORATING SAME AND METHOD OF MAKING SAME
`
`Enclosed are:
`
`(XI The Declaration and Power of Attorney.
`
`lx ) signed
`
`l
`
`l unsigned or partially signed
`
`’
`
`I sheets of drawings (one set)
`8
`(X)
`(
`) Form PTO-1449
`(
`)
`
`l Associate Power of Attorney
`(
`Information Disclosure Statement and Form PTO-1449
`
`I
`
`) Priority document(s)
`
`(
`
`)lOrherl
`
`(fee $
`
`)
`
`(1)
`FOR
`
`CLAIMS AS FILED BY OTHER THAN A SMALL ENTITY
`(2)
`(3)
`(4’
`NUMBER FILED
`NUMBER EXTRA
`RATE
`
`TOTAL CHARGES TO DEPOSIT ACCOUN
`
`TOTAL CLAIMS
`
`20 — 20
`
`INDEPENDENT
`CLAIMS
`ANY MULTIPLE
`DEPENDENT CLAIMS
`
`BASIC FEE: DesignI
`
`$330.00
`
`X$18
`
`X $84
`
`$280
`);Utility( $750.00 )
`
`TOTAL FILING FE.
`
`OTHER FEES
`
`this
`At any time during the pendency of
`to Deposit Account 50-1078.
`25;;
`Charge $
`application, please charge any fees required or credit any over payment to Deposit Account 50-1078
`pursuant to 37 CFR 1.25. Additionally please charge any fees to Deposit Account 50-1078 under 37
`CFR 1.16, 1.17,1.19, 1.20 and 1.21. A duplicate copy of this sheet is enclosed.
`
`"EXDress Mail" label ”0' _—_EV262 717 905 US'
`
`Date of Deposit June 27 2003
`
`I hereby certify that this is being deposited with the
`United States Postal Service "Express Mail Post
`Office to Addressee" service under 37 CFR 1.10 on
`the date indicated above and is addressed to:
`Commissioner
`for
`Patents,
`PO
`Box
`1450,
`Alexandria, VA 22313—1450.
`
`Bv
`Typed Name: Linda A. Iimura
`
`.
`
`Respectfully ubmitted
`
`
`
`BY
`
`Ian Han astle
`
`Attorney/Agent for ApplicantIsl
`Reg. No.
`34,075
`
`Date: June 27, 2003
`
`Telephone NO-i (650) 485-3015
`
`Nichia Exhibit 1004
`
`Page 2
`
`Nichia Exhibit 1004
`Page 2
`
`

`

`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`APPLICATION FOR PATENT
`
`Packaging Device for Semiconductor Die, Semiconductor Device Incorporating Same
`
`and Method of Making Same
`
`Inventors:
`
`Kong Wen g Lee
`Kee Yean Ng
`Yew Cheong Kuan
`Cheng Why Tan
`Gin Ghee Tan
`
`[0001]
`
`- This application is related to a simultaneously-filed United States patent
`
`Related Application
`
`application serial number lO/xxx,xxx entitled Method for Fabricating a Packaging
`
`Device for Semiconductor Die and Semiconductor Device Incorporating Same of
`
`inventors Kong Weng Lee, Kee Yean Ng, Yew Cheong Kuan, Chcng Why Tan and
`Gin Ghee Tan, attorney docket number 70030260—1.
`I
`
`[0002]
`
`Many types of conventional semiconductor device are c0mp0sed of a
`
`Background of the Invention
`
`semiconductor die mounted in a packaging device. One type of packaging device
`
`widely used in the industry includes a metal lead frame. A metallization layer of 7
`
`aluminum located on the bottom surface of the Semiconductor die is bonded to a
`
`conductive surface that forms part of the lead frame to attach and electrically connect
`
`the die to the lead frame. Additionally, electrical connections are made between
`
`bonding pads on the top surface of the die and other leads of the lead frame to provide
`
`additional electrical connections to the die. The lead frame and semiconductor die are
`
`then encapsulated to complete the semiconductor device. The packaging device
`
`protects the semiconductor die and provides electrical and mechanical connections to
`
`the die that are compatible with conventional printed circuit board assembly
`
`A~ 70030259
`
`2003-06—26 09:14
`
`Nichia Exhibit 1004
`
`Page 3
`
`Nichia Exhibit 1004
`Page 3
`
`

`

`A—70030259—1
`
`-
`
`’
`
`PATENT
`
`processes.
`
`[0003]
`
`In such conventional semiconductor devices, the bottom surface of the die is
`
`typically bonded to the conductive surface of the lead frame using a silver epoxy
`
`adhesive that cures at a relatively low temperature, typically about 120 0C. The curing
`
`temperature of the silver epoxy adhesive is compatible with the other materials of the
`
`packaging device.
`
`[0004]
`
`The volume of the packaging device used in such conventional semiconductor
`
`devices, i.e., the lead frame and the encapsulant, is typically many times that the
`semiconductor die. This makes such conventional semiconductor devices unsuitable
`
`for use in applications in which a high packing density is required. A high packing
`
`density allows miniaturization and other benefits. Therefore, what is needed is a
`
`semiconductor packaging device that is comparable in volume with the semiconductor
`
`die and that is compatible with conventional printed circuit board assembly processes.
`
`[0005]
`
`Recently, semiconductor die having a substrate surface metallization layer of a
`
`gold-tin alloy (80 % Au:20 % Sn approximately) have been introduced in light-
`
`emitting devices. Such semiconductor die typically have a substrate of sapphire,
`
`silicon carbide or a Group III-V semiconductor material, such as gallium arsenide.
`
`Semiconductor devices having substrates of the first two substrate materials have
`
`layers of Group III-V semiconductor materials, such as gallium nitride, deposited on
`
`their substrates. The die attach process for such semiconductor die uses a gold-tin
`
`eutectic, which has a melting point of about 280 °C. Temperatures as high as about
`
`350 °C can be encountered in the die attach process for such die. Such high
`
`temperatures are incompatible with the. materials of many conventional packaging
`
`devices. Thus, what is also needed is a packaging device for semiconductor die that
`use a high-temperature die attach process.
`
`[0006]
`
`Many printed circuit assembly processes and assembly equipment require the
`
`use of standard semiconductor device packages. Modifying such processes to use a
`
`new semiconductor device package can be expensive and can interrupt production.
`
`Therefore, what is additionally needed is a way to mount a semiconductor die that
`
`' requires a high—temperature die attach process ina conventional packaging device.
`
`Nichia Exhibit 1004
`
`Page 4
`
`Nichia Exhibit 1004
`Page 4
`
`

`

`A—70030259-1
`
`'
`
`_3_
`
`PATENT
`-
`
`[0007]
`
`The invention provides a packaging device for a semiconductor die. The
`
`Summary of the Invention
`
`packaging device includes a substrate, a mounting pad, a connecting pad and an
`
`interconnecting element. The substrate is substantially planar and has opposed major
`
`surfaces. The mounting pad is conductive and is located on one of the major surfaces.
`
`The connecting pad is conductive and is located on the other of the major surfaces.
`
`The conductive interconnecting element extends through the substrate and electrically
`
`interconnects the mounting pad and the connecting pad.
`
`[0008]
`
`The packaging device has a volume that is only a few times that of the
`
`semiconductor die and can be fabricated from materials that can withstand a high—
`
`temperature die attach process. The packaging 'device can be configured as the only
`
`packaging device of the semiconductor device. The packaging device can
`
`alternatively be configured as a submount for a semiconductor die that requires a
`
`high—temperature die attach process. The submount with attached semiconductor die
`
`can be handled as a conventional, albeit slightly larger, semiconductor die that is then-
`
`mounted in a conventional packaging device, such as a leadframe based packaging
`
`device, using a conventional semiconductor device assembly process, including
`conventional temperatures.
`I
`
`[0009]
`
`:
`‘The invention also provides a semiconductor device that includes a substrate, -
`a mounting pad, a connecting pad, an interconnecting element and a semiconductor
`
`die. The substrate is substantially planar and has opposed major surfaces. The
`
`mounting pad is conductive and is located on one of the major surfaces. The
`
`connecting pad is conductive and is located on the other of the major surfaces. The
`
`conductive interconnecting element extends through the substrate and electrically
`
`interconnects the mounting pad and the connecting pad. The semiconductor die is
`
`affixed to the mounting pad.
`
`[0010]
`
`The semiconductor device as just described can. be mounted in a conventional
`
`packaging device as described above. Alternatively, the semiconductor device may
`additionally include a bonding pad, an additional connecting pad, an additional
`
`interconnecting element and a bonding wire. The bonding pad is conductive and is
`
`located on the one of the major surfaces. The additional connecting pad is conductive
`
`and is located on the other of the major surfaces. The additional interconnecting
`
`Nichia Exhibit 1004
`
`Page 5
`
`Nichia Exhibit 1004
`Page 5
`
`

`

`A—70030259—1
`
`PATENT .
`
`_4_
`
`element is conductive and extends through the substrate and electrically interconnects
`
`the bonding pad and the additional connecting pad. The bonding wire extends
`
`between the semiconductor die and the bonding pad. Such a semiconductor device
`constitutes a stand—alone semiconductor device that has a low profile and that can be
`
`used in high packing density applications. The semiconductor device may additionally
`
`include an encapsulant that encapsulates the semiconductor die and at least a portion
`
`of the major surface of the substrate on which the mounting pad is located.
`
`[0011]
`
`Figures 1A, 1B, 1C, 1D, 1E and IF are respectively an isometric view, a side
`
`Brief Description of the Drawings
`
`View, a front View, a top view, a bottom View and a cross-sectional view of a first
`embodiment of a packaging device in accordance with the invention. The cross—
`
`sectional view of Figure 1F is along the section line lF—lF in Figure 1D.
`
`Figures 2A, 2B, 2C, 2D, 2E and 2F are respectively an isometric View, a side
`
`View, a front View, a top view, a bottom view and a cross-sectional view of a first
`
`embodiment of a semiconductor device in accordance with the invention. The cross—
`
`sectional view of Figure 2F is along the section line 2F—2F in Figure 2D.
`
`Figures 3A, 3B, 3C, 3D, 3E and 3F are respectively an isometric view, a side
`
`view, a front view, a top view, a bottom View and a cross-sectional view of a second
`
`embodiment of a packaging device in accordance with the invention. The cross-
`
`sectional View of Figure 3F is along the section line 3F—3F in Figure 3D.
`
`Figures 4A, 4B, 4C, 4D, 4E and 4F are respectively an isometric View, a side
`
`View, a front view, a top view, a bottom View and a cross—sectional View of a second
`
`embodiment of a semiconductor device in accordance with the invention. The cross-
`
`sectional view of Figure 4F is along the section line 4F-4F in Figure 4D.
`
`Figures 5A—5C are side views illustrating a method in accordance with the
`
`invention for fabricating a packaging device for a semiconductor die.
`
`Figure 5D is a side view illustrating an optional additional process that may be
`
`included in the method illustrated in Figures SA-SC.
`
`Figures 6A—6D are side views illustrating a method in accordance with the
`
`invention for fabricating a semiconductor device.
`
`Nichia Exhibit 1004
`
`Page 6
`
`Nichia Exhibit 1004
`Page 6
`
`

`

`A—70030259-1
`
`PATENT
`
`_5_
`
`[0012]
`
`Figures lA—1F are schematic diagrams illustrating a first exemplary
`
`Detailed Description of the Invention
`
`embodiment 100 of a packaging device for a semiconductor die in accordance with
`
`the invention. Packaging device 100Ais composed of a substrate 110, interconnecting
`elements 120 and 122, a mounting pad 130, a bonding pad 132 and connecting pads
`
`140 and 142 (Figure 1E).
`
`'
`
`[0013]
`
`Substrate 110 is substantially planar, has opposed major surfaces 112 and 114
`
`and defines through holes 116 and l 18 that extend through the substrate between
`
`major surfaces 112 and 114. lnterconnecting element 120 is electrically conductive
`
`and is located in through hole 116. Interconnecting element 122 is electrically
`
`conductive and is located in through hole 118. Mounting pad 130 and bonding pad
`
`132 are electrically conductive, are separate from one another and are located on the
`
`portions of the major surface 112 of substrate 110 in which through holes 116 and 118
`
`are respectively located. Connecting pads 140 and 142 are electrically conductive, are
`
`separate from one another and are located on the portions of the major surface 114 of
`
`substrate 110 in which through holes 116 and 118 are respectively located.
`
`[0014]
`
`Mounting pad 130 and connecting pad 140 are electrically connected to
`
`opposite ends of interconnecting element 120. Thus, intcrconnectin g element 120
`
`extending through substrate 110 in through hole 116 electrically connects mounting;
`
`pad 130 to connecting pad 140. Bonding pad 132 and connecting pad 142 are
`
`electrically connected to opposite ends of interconnecting element 122. Thus,
`
`interconnecting element 122 extending through substrate 1 10 in through hole 118
`
`electrically connects bonding pad 132 to connecting pad 142.
`
`[0015]
`
`The material of substrate 110 is a thermally-conductive ceramic such as
`
`alumina or beryllia. In an embodiment, the material of the substrate was Kyocera®
`
`Type A440 ceramic sold by Kyocera Corp., of Kyoto, Japan. Typical dimensions of
`
`the substrate are in the range from about 0.5 mm square to about 2 mm square.
`Rectangular configurations are also possible. Alternative substrate materials include
`
`semiconductors, such as silicon, and epoxy laminates, such as those used in printed-
`
`circuit boards. Other materials that have a high thermal conductivity and a low
`
`electrical conductivity can be used instead of those exemplified above. The coefficient
`
`of thermal expansion of the substrate material relative to that of the semiconductor die
`
`Nichia Exhibit 1004
`
`Page 7
`
`Nichia Exhibit 1004
`Page 7
`
`

`

`A—70030259—1
`
`PATENT
`
`—6—
`
`to be mounted on packaging device 100 should also be considered in choosing the
`substrate material;
`
`[0016]
`
`As will be described in more detail below, substrate 110 is part of a wafer (not
`
`shown) from which typically several hundred packaging devices 100 are fabricated by
`
`batch processing. After fabrication of the packaging devices, the wafer is singulated
`
`into individual packaging devices. Alternatively, the packaging devices may be left in.
`
`wafer form after fabrication. In this case, singulation is not performed until after at
`
`least a die attach process has been performed to attach a semiconductor die to each
`
`mounting pad 130 on the wafer. In some embodiments, wafer—scale wire bonding,
`
`encapsulation and testing are also performed prior to singulation. Full electrical
`
`testing, including light output testing, may be performed on the wafer.
`
`[0017]
`
`The material of interconnecting elements 120, 122 is metal or another
`
`electrically-conductive material. In an embodiment, the material of the
`
`interconnecting elements is tungsten, but any electrically—conductive material capable
`
`of forming a low—resistance electrical connection with the pads, i.e., mounting pad
`
`130, bonding pad 132 and connecting pads 140, 142, and capable of withstanding the
`
`temperature of the die»attach process may be used. As noted above, packaging device
`
`100 may be subject to a temperature as high as about 350 °C when a gold-tin eutectic
`
`is used to attach a semiconductor die to the mounting pad 130 of the packaging
`
`device. Interconnecting elements 120, 122 may be located relative to mounting pad
`
`130 and bonding pad 132, respectively, elsewhere than the centers shown. Moreover,
`
`more than one interconnecting element may be located within either or both of the
`
`mounting pad and the bonding pad.
`
`[0018]
`
`The material of pads 130, 132, 140, 142 is metal or another electrically-
`
`conductive material. Important considerations in selecting the material of the pads are
`
`adhesion to substrate 110, an ability to form a durable, low-resistance electrical
`
`connection with interConnecting elements 120 and 122 and an ability to withstand the
`
`temperature of the die attach process. In an embodiment, the structure of the pads is a
`
`seed layer of tungsten covered with layer of nickel about 1.2 pm to about 8.9 pm
`
`thick that is in turn covered with a layer of gold about 0.75 pm thick. Other metals,
`
`alloys, conductive materials and multi—layer structures of such materials can be used.
`
`[0019]
`
`Packaging device 100 is used to package a semiconductor die. A
`
`Nichia Exhibit 1004
`
`Page 8
`
`Nichia Exhibit 1004
`Page 8
`
`

`

`A—70030259-1
`
`’
`
`PATENT
`
`_7_
`
`o
`
`semiconductor device in which a semiconductor die is packaged using packaging
`
`device 100 described above will be described next.
`
`[0020]
`
`Figures 2A—2F are schematic diagrams illustrating an exemplary embodiment
`
`200 of a semiconductor device in accordance with the invention. Semiconductor
`
`device 200 incorporates packaging device 100 in accordance with, the invention.
`
`Elements of semiconductor device 200 that correspond to elements of packaging
`
`device 100 described above with reference to Figures lA—lF are indicated using the
`
`same reference numerals and will not be described again in detail.
`
`[0021]
`
`Semiconductor device 200 is composed of packaging'device 100 described
`
`above with reference to Figures lA—lF, a semiconductor die 250, encapsulant 252 and
`
`a bonding wire 254. In the example shown, semiconductor die 250 embodies a light—
`
`emitting diode and has anode and cathode electrodes (not- shown) covering at least
`
`parts of its opposed major surfaces. Semiconductor die 250 is mounted on packaging-
`
`device 100 with the metallization, on its bottom major surface attached to mounting
`
`pad 130. Encapsulant 252 covers the semiconductor die and the part of the major
`
`surface 112 of substrate 100 where mounting pad 130 and bonding pad 132 are
`
`located. Bonding wire 254 extends between a bonding pad located on the top major
`
`surface of semiconductor die 250 and bonding pad 132.
`
`[0022]
`
`The bonding pad on the top major surface of semiconductor die 250 is
`
`typically part of or connected to the anode electrode of the light—emitting diode. The
`
`metallization 0n the bottom major surface of semiconductor die 250 typically
`constitutes the cathode electrode of the light-emitting diode. Thus, the anode electrode
`
`of semiconductor die 250 is electrically connected to connecting pad 142 by bonding
`wire 254, bonding pad 132 and interconnecting element 122, and the cathode ‘
`
`electrode of semiconductor die 250 is electrically connected to connecting pad 140 by
`
`mounting pad 130 and interconnecting element 120.
`
`[0023]
`
`Encapsulant 252 has a thickness greater than the maximum height of bonding
`
`wire 254 above major surface 112. In the example shown, the encapsulant is
`
`transparent to enable semiconductor device 200 to emit the light generated by
`
`semiconductor die 250.
`
`[0024]
`
`Semiconductor die 250 is composed of one or more layers (not shown) of any
`
`semiconductor material composed of elements from Groups 11, HI, IV, V and VI of
`
`Nichia Exhibit 1004
`
`Page 9
`
`Nichia Exhibit 1004
`Page 9
`
`

`

`A-70030259-1
`
`.
`
`PATENT
`
`_g_
`
`the periodic table in binary, ternary, quaternary or other form. Semiconductor dic 250
`may additionally include a non—semiconductor substrate material, such as sapphire,
`
`metal electrode materials and dielectric insulating materials, as is known in the art.
`
`[0025]
`
`In an embodiment of the above-described example in which semiconductor die
`
`250 embodies a light—emitting diode, semiconductor die 250 is composed of a
`
`substrate of silicon carbide that supports one or more layers of (indium) gallium
`
`nitride. Such a light-emitting diode generates light in a wavelength range extending
`
`from ultra—violet to green. The bOItom major surface (not shown) of the substrate
`
`remote from the layers of (indium) gallium nitride is coated with a'metallization layer
`of a gold-tin alloy. A gold-tin eutectic attaches the semiconductor die to mounting pad
`
`130, as described above, to provide a mechanical and electrical connection between
`
`the semiconductor die and the mounting pad.
`
`[0026]
`
`The material of bonding wire 254 is gold. A process known in the art as low—
`
`loop wire bonding is used to connect the bonding wire between the anode electrode of
`
`semiconductor die 250 and bonding pad 132. Using low—loop wire bonding minimizes.
`
`the maximum height of the bonding wire abovesubstrate 110, and, therefore, reduces
`
`the overall height of semiconductor device 200. Other processes for providing an
`electrical connection between a bonding pad on a semiconductor die and a bonding
`
`pad on a packaging device are known in the art and may be used instead, especially in
`applications in which device height is a less important consideration.
`
`[0027]
`
`The material of encapsulant 252 is clear epoxy. Alternative encapsulant
`
`materials include silicone. Embodiments of semiconductor device 200 that neither
`emit nor detect light can use an opaque encapsulant.
`In the example of semiconductor device 200 described above, semiconductor
`
`[0028]
`
`die 250 is embodied as a light—emitting diode. Semiconductor die 250 may
`
`alternatively embody another type of diode without modification to packaging device
`
`100. Versions of packaging device 100 may be used to package semiconductor die
`
`other than those that embody such electrical components as diodes that have only two
`
`electrodes. Versions of packaging device 100 may be used to package semiconductor
`
`die that embody such electronic circuit elements as transistors and integrated circuits
`Y that have more than two electrodes. Such versions of packaging device 100 have a
`
`number of bonding pads, interconnecting elements and connecting pads
`
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`A—70030259—1
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`PATENT g
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`corresponding to the number of bonding pads located on the top major surface of the
`
`semiconductor die. For example, a version of packaging device 100 for packaging a
`
`semiconductor die that embodies a transistor having collector, base and emitter
`
`electrodes, and in which the substrate metallization provides the collector electrode,
`
`has two bonding pads, two interconnecting elements and two connecting pads. Wire '
`
`bonds connect the emitter bonding pad on the semiconductor die to one of the
`
`bonding pads on the packaging device and the base bonding pad on the semiconductor
`
`die to the other of the bonding pads on the packaging device.
`
`[0029]
`
`The connecting pads, e.g., connecting pads 140 and 142', of embodiments of
`
`packaging device 100 having multiple connecting pads may be arranged to conform -
`
`with an industry standard pad layout to facilitate printed circuit layout. In such
`embodiments, the interconnecting elements may be offset from the centers of the
`
`respective mounting pads, bonding pads and connecting pads to allow the connecting
`
`pad layout to conform with such a standard pad layout. In some embodiments, one or
`
`more of the mounting pad, bonding pads and connecting pads may have a shape that
`
`differs from the regular shapes illustrated. Some irregular shapes include two main
`
`regions electrically connected by a narrow track. For example, an irregularly—shaped
`
`bonding pad includes a region to which the bonding wire is attached, a region
`
`connected to the interconnecting element and a narrow track interconnecting the two
`
`regions.
`
`[0030]
`
`Some versions of packaging device may accommodate two or more
`
`semiconductor die. In such versions, mounting pad 130 is sized large enough to'
`
`accommodate the two or more semiconductor die. Additionally, such versions include
`
`sufficient bonding pads, interconnecting elements and connecting pads to make the
`
`required number of electrical connections to the semiconductor die. Alternatively, the
`
`packaging device may include two or more mounting pads. The mounting pads may
`
`be electrically connected to one another and thence to a common interconnecting
`
`element and connecting pad. Alternatively, each mounting pad may be electrically
`
`connected to a corresponding connecting pad by a respective interconnecting element.
`
`[0031]
`
`Semiconductor device 200 is used by mounting it on a printed circuit board or
`
`other substrate using conventional surface—mount techniques or other techniques
`
`known in the art. Semiconductor device 200 is placed on a surface of the printed
`
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`circuit board with connecting pads 140 and 142 aligned with respective pads on the
`
`printed circuit board. The printed circuit board is then passed across a solder wave to
`
`form a solder joint between connecting pads 140 and 142 and the respective pads on
`
`the printed circuit board. Alternatively, semiconductor device 200 may be affixed to a
`
`printed circuit- board by a process known as infra—red reflow soldering in which a
`
`pattern of solder is applied to the printed circuit board using a stencil, semiconductor
`
`device 200 and, optionally, other components are loaded onto the printed circuit board
`
`and the printed circuit board assembly is irradiated with infra-red light to heat and
`
`reflow the solder. Other processes for attaching electronic components to printed
`
`circuit boards are known in the art and may alternatively be used. Packaging device
`100 and semiconductor device 200 may additionally include adhesive regions on the
`
`major surface 114 of substrate 110 external to connecting pads 140 and 142 to hold
`
`the semiconductor device in place on the printed circuit board during soldering.
`
`[003 2]
`
`In semiconductor device 200, packaging device 100 and encapsulant 252
`
`collectively have a volume that is only about 15 times the volume of semiconductor
`
`die 250. Thus, packaging device 100 is well'suited for use in high packing density
`
`applications. Moreover, packaging device 100 is fabricated from materials capable of
`
`withstanding the high temperatures involved in a die attach process that uses a gold-
`
`tin eutectic. Accordingly, packaging device 100 is well suited for packaging
`
`semiconductor die, such as the die of certain light-emitting devices, that require a die
`
`attach process that uses a gold-tin eutectic.
`
`[0033]
`
`As noted above, many printed circuit board assembly processes are designed
`
`to use standard device packages, but many standard device packages are incapable of
`
`withstanding the high temperatures involved in a die attach process that uses a gold-
`
`tin eutectic. Figures 3A-3F are schematic drawings showing a second embodiment
`
`300 of a packaging device in accordance with the invention. Packaging device 300
`
`takes the form of a submount that enables semiconductor die that are mounted using a
`
`gold-tin eutectic or other high-temperature die attach process to be mounted in
`
`conventional semiconductor device packages that are incapable of withstanding such
`
`high temperatures. Moreover, packaging device 300 with a semiconductor die
`
`mounted thereon can be mounted in a conventional semiconductor device package as
`
`if it were a conventional semiconductor die. This allows conventional die attach, wire
`
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`bond and encapsulation processes to be used to assemble the final semiconductor
`
`device that incorporates the submount.
`
`[0034]
`
`Figures 3A-3F are schematic diagrams illustrating a second exemplary
`
`embodiment 300 of a packaging device for a semiconductor die in accordance with
`
`the invention. Packaging device 300 takes the form of a submount for a
`
`semiconductor die. Packaging device 300 is composed of a substrate 310, an
`
`interconnecting element 320, a mounting pad 330 and a connecting pad 340 (Figure
`
`3E).
`
`'
`
`[0035]
`
`Substrate 310 is substantially planar, has opposed major surfaces 312 and 314
`
`and defines a through hole 316 that extends through the substrate between major
`
`surfaces 312 and 314. Interconnecting element 320 is electrically conductive and is
`
`located in through hole 316. Mounting pad 330 is electrically conductive and is
`
`located on a portion of the major surface 312 of substrate 310 in which through hole
`
`316 is located. Alternatively, mounting pad 330 may cover major surface 312.
`Connecting pad 340 is electrically conductive and is located on a portion of the major
`
`surface 314 of the substrate in which through hole 316 is located. Alternatively,
`
`connecting pad 340 may cover major surface 314.
`
`[0036] .
`
`Mounting pad 330 and connecting pad 340 are electrically connected to
`
`opposite ends of interconnecting element 320. Thus, interconnecting element 320
`
`extending through the substrate in through hole 316 electrically connects mounting:
`
`pad 330 to connecting pad 340.
`
`[0037]
`
`Materials and other details of substrate 310, interconnecting element 320,
`
`mounting pad 330 and connecting pad 340 are the same as those of substrate 110,
`
`interconnecting element 120, mounting pad 130 and connecting pad 140, respectively,
`
`of packaging device 100 described above with reference to Figures lA-lF and will
`
`[0038]
`
`therefore not be described again here.
`A semiconductor device in which a semiconductor die is packaged using
`
`packaging device 300 described above will be described next.
`
`[0039]
`
`Figures 4A—4F are schematic diagrams illustrating an exemplary embodiment
`
`400 of a semiconductor’device in accordance with the invention. Semiconductor
`
`device 400 incorporates packaging device 300 in accordance with the invention.
`
`Elements of semiconductor device 400 that correspond to elements of semiconductor
`
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`A—70030259-l
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`device 200 described above with reference to Figures 2A—2F and of packaging device
`
`300 described above with reference to Figures 3A-3F are indicated using the same
`
`reference numerals and will not be described again in detail.
`Semiconductor device 400 is composed of a semiconductor die 250 mounted
`
`[0040]
`
`on packaging device 300 described above with reference to Figures 3A—3F. In the
`
`example shown, semiconductor die 250 embodies a light—emitting diode and has
`
`anode and cathode electrodes (not shown) covering at least parts of its opposed major
`
`surfaces. Specifically, semiconductor die 250 is mounted on packaging device 300
`
`with the metallization on its bottom major surface attached to mounting pad 330. The
`
`metallization on the bottom major surface of