AVAGO TECHNOLOGIES, LTD.
`4380 Ziegler Road
`Fort Collins, Colorado 80525
`
`ATTORNEY DOCKET NO. 70030259-02
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`Patent Application Transmittal Letter
`
`COMMISSIONER FOR PATENTS
`P .0. Box 1450
`Alexandria VA 22313-1450
`
`Sir:
`Transmitted herewith for filing under 37 CFR 1.53(b) is a(n): 0 Utility D Design
`D Original patent application,
`0 Continuation-in-part
`
`INVENTOR(S}: Lee et al.
`
`TITLE: SEMICONDUCTOR DEVICE WITH A LIGHT EMITTING SEMICONDUCTOR DIE
`
`Enclosed are:
`0
`The Declaration and Power of Attorney
`...1Q_ sheets of drawings (one set)
`Form PT0-1449
`D Other:
`Priority document(s)
`
`0 B
`
`D Unsigned or partially signed
`0 Signed
`D Associate Power of Attorney
`D Information Disclosure Statement and Form PT0-1449
`Other Fee: $
`
`(1)
`FOR
`
`TOTAL CLAIMS
`
`INDEPENDENT
`CLAIMS
`
`CLAIMS AS FILED BY OTHER THAN A SMALL ENTITY
`(2)
`(3)
`(4)
`NUMBER FILED
`NUMBER EXTRA
`RATE
`X s 50
`
`20 -20
`
`0
`
`3- 3
`
`0
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`X $200
`
`ANY MULTIPLE ~ $360
`
`30- 100
`
`0
`
`X $250/50
`
`DEPENDENT CLAIMS
`TOTAL SHEETS OF
`SPEC AND DWGS
`
`(5)
`TOTALS
`
`$
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`$
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`0
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`0
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`BASIC FEE: Design ($350.00); Utiltiy ($1000.00)
`TOTAL FILING FEE
`OTHER FEES
`TOTAL CHARGES TO DEPOSIT ACCOUNT
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`$ 1,000
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`Charge $1.000 to Deposit Account 50-3718. At any time during the pendency of this application, please charge any
`fees required or credit any over payment to Deposit Account 50-3718 pursuant to 37 CFR 1.25. Additionally
`please charge any fees to Deposit Account 50-3718 under 37 CFR 1.16, 1.17, 1.19, 1.20 and 1.21. A duplicate
`copy of this sheet is enclosed.
`
`"Express Mail" Label No.:
`
`Date of Deposit:
`
`I hereby certify that this is being deposited with the United States
`Postal Service "Express Mail Post Office to Addressee" service
`under 37 CFR 1.10 on the date indicated above and is addressed
`to: Commissioner for Patents, P.O. Box 1450,
`Alexandria VA 22313-1450.
`
`Typed Name:
`
`Signature: ___________________ _
`
`Rev 10104 (TransNew)
`
`Respectfully submitted,
`
`Lee et al.
`
`By /thomas h. ham/
`
`Thomas H. Ham
`Attorney/Agent for Applicant(s)
`
`Reg. No. 43,654
`
`Date: August 14, 2007
`
`Telephone No. (925) 249-1300
`
`Nichia Exhibit 1002
`Page 1
`
`

`

`p.3
`
`DECLARATION AND POWER OF AnORNEY
`FOR PATENT APPLICAnOII
`
`As a below named inventor, I hereby declare that
`
`ATTORNEY DOCKET NO. 7003G258-02
`
`My residencelcorrespondenoe post offtca address and citizenship are as stated below next lo my name:
`
`1 believe 1 am the original, first and sole Inventor (If only one name is listed below) or an original, first and joint inventor (If plural
`names are Hsted below) of the subjecl matter which is claimed and for which a patenlls sought on the invention entitled:
`SEMICONDUCTOR DEVICE WITH A LIGHT EMmiNG SEMICONDUCTOR DIE
`
`the specification of which is attached hereto unless the following box is checked:
`0 was filed on _______ as US Application Serial No. or PCT International Application
`Number
`(If applicable).
`and was amended on
`
`I hereby state that I have reviewed and understood the contents of the abova-idenHIIed specillcaUon. Including the dairns, as
`amended by any amendment( a) referred to above. I acknowledge the duty to disclose all information which is material to
`patentability as defined In 37 CFR 1.56.
`For•ign AppiiCIItioll(c) ancllor CWm of Foreign Priority
`I hereby daim rontlgn priority benetlta undlll" Tille 35, United States Coda Section 119 d any foreign applcation(a) for patent or lrMnlol(s)
`certificate lisle<! below and hlrw'e alao klcmtllled below BOy foreign applicetioo for patent or lnwnlof(s) certltlc::ata having a tiling date befura lhat of the
`
`rm~~~-~T
`
`PrGvtsiOIIIII Application
`I hereby claim the benefit under Tille 35, Unilad S1ales Code Section 119(e) of any United States provisional applc:aUon(s) Hilled bl!llow
`
`U. l5. Pr1011ty lOialln
`I 1\ereby claim the benefit underTHie 35, United Stalas Cede, Section 120 of lilY United States applicalion(a) isbKt below anc.l, Jnsolar aa . .
`subject matter of each of the claims of this application Is not lhcloaed In lhe prior Uni1ed States applcallon In lhe manner provlcMd by the flm
`pwagraph of Title 35, United States Code Section 112, I adUlowledge 1lle diAy to dieeloae materiallnftnnallon 81 deftned in Tille 37, Cocla of
`Federal Regulations, Section 1.56(a) whidl oc;c;uned betwHn the filing 11-. of the prior applicatfon and the national ar PCT lntamatlonalftllng da
`ollhla aJ)Illlcation:
`
`0612712003
`
`SfXfUs ::;:.-..--1111
`
`ndrn
`
`POWI!R OF ATTORNeY:
`As a named inventor, I hereby appoint llle fallowing ataney(s) aOOior agent( a) to prosecul8 this application and transact all bual118811n the Patlnt
`and Trademark Office connecled lhs&oM!h: PRACmiONERS ASSOCIATED WITH CUSTOMER NUMBER 57299.
`
`Send Corruponclence ID :
`Cu~m.rNumbwl ~-57--2-99---,
`
`Direct Telephone Cale To:
`
`AVAGO TECHNOLOGIES. LTD.
`4380 Ziegler Road
`Fort Colina, CO 805211
`
`ThomaaH.Ham
`(925) 249-1300
`
`OR
`
`Scott Weitzel
`(970) 288-0747
`
`I hereby declare that all statements made herein of my own knowledge are true and that all statements made on Information and
`belief are believed to be true; and further that these statement$ were made Vt'ith the knowledge that willful false statements and the
`like so made are punishable by fine or imprisonment, or both, under Section 1001 of Title 18 of the United States Code and that
`such willful false statements may jeopardize the validity of the application or any patent iaeued thereon.
`
`Full.._m. of Inventor: Kong Weng LAe
`Residence: San Jose, California
`Correa pond ce Post Office Add,.. a: 438U[Llf1GII8f Road, Fort Colllna, CO 80525
`
`Cltblew.hlp: llalapla
`
`Invent«'• SJa<ul
`
`,..., .. 2
`
`Nichia Exhibit 1002
`Page 2
`
`

`

`OE.CLARAT~ONAND POWER- OF ATTORNEY
`FP~ PATENT APPLICATION (Contsnued)
`
`ATIORNE't:' DOCKET NO, 70030.259·02
`
`Fun Nama oUtS Joint fn'll·~ntcn·: Y&w.Choong Kuan
`.
`Res~(ience:~ ?~mm!\J, Malaysia .. ··.
`Corres~~n~;nc~~~l\:~ft1ce Addres~~ 43!!0 Ziegler<Ro<id; Fort Collins, CO 80525
`
`~.:' ~ \F<-··' '
`.'.;, \\
`
`Full Name of# 4 .Joint Inventor: Chen~i Wh¥' Tan
`Rllsfdenc~t: Penar\g, Ma§ays!a
`Correspondenc~J P~st9ffi~~ Addt~s;>; 4380 Ziegler Road, FortCo.mns, CO St.lfi~S
`('tf·
`~ ~.
`~ ~~ ... J,_A~V*'"'
`
`Full Name of# :5 Joint !nv·entcr: Girl Gh~e. Tan
`Re?irlence: Penang, Mafays~a · · ·
`Ccrrespondef!ce PostOffice Address! 4:180 ZiElgler Rood,. Fart comos, co 805.25
`
`Citizensch.lp-: Mal~KSia
`
`full Name oftf
`Re::siden:ce:
`CorrB$pondefle!i Post Offl:ci'~Addressc
`
`Jolnt!nve.lltor:
`
`Citi~enship;
`
`Full N,ame of# Joint lnvMtor:
`Rllsldence:
`Co-rrespoml~ne'!3 Post OfficRAdt;!mss~
`
`F11U Name <if#
`R~sl.denc:e:
`Corre~pond~fice Fo$t Offk:~ Address:
`
`JCliMt lnv!3ntor:
`
`FuH Name of# Join~ Inventor;
`Rcsfaence:
`CotrllSfX3ntl~nC!l Post Offlc~ Addrnss~
`
`Cilizt.ns:tHp;
`
`Nichia Exhibit 1002
`Page 3
`
`

`

`DECLARATION AND POWER OF ATTORNEY
`FOR PATENT APPLICATION (Continued)
`
`ATTORNEY DOCKET NO. 70030259-02
`
`Full Name of# 2 Joint Inventor: Kee Yean Ng
`Residence: Penang, Malaysia
`Correspondence Post Office Address: 4380 Ziegler ·Road, Fort Collins, CO 80525
`
`Citizenship: Malaysia
`
`lnvcniOr's Signature
`
`........ ..,.,..,...., .................. .......,..,.,., ........ _~.,..., .................... _~ .... ~ ............ ...
`:~):.':~.)
`
`Full Name of# 3 Joint Inventor: Yew Cheong Kuan
`Residence: Penang, Malaysia
`Correspondence Post Office Address: 4380 Ziegler Road, Fort Collins, CO 80525
`
`Citizenship: Malaysia
`
`.·.-.-.--·.·.·.-.-.-. ................ , ............ -. ........... , ................... , ..... ·•· ................ ·•·•·.·
`f.~: .. -~;
`
`Full Name of# 4 Joint Inventor: Cheng Why Tan
`Residence: Penang, Malaysia
`Correspondence Post Office Address: 4380 Ziegler Road, Fort Collins, CO 80525
`
`Citizenship: Malaysia
`
`,._,_ .................................. LLL ................................ ~~ ............... LL< ............................. ., •.•. ~-. ~---L~L····~".............._ ••• ............,_,
`~(W>:{~~··'.•; :~:~:iN·:O:·~~~
`
`Full Name of# 5 Joint Inventor: Gin Ghee Tan
`Residence: Penang, Malaysia
`Correspondence Pos Qffice Address: 4380 Ziegler Road, Fort Collins, CO 80525
`
`Citizenship: Malaysia
`
`Full Name of# Joint Inventor;
`Residence:
`Correspondence Post Office Address:
`
`lnvenlllr's Signature
`
`Full Name of# Joint Inventor:
`Residence:
`Correspondence Post Office Address:
`
`Citizenship:
`
`Date
`
`Clti:zenshlp:
`
`Inventor's Signqturc
`
`.......... ~L<,. ............ ~-··· ............. -
`
`................................. __
`
`:)::-t~
`
`Full Name of# Joint Inventor:
`Residence:
`Correspondence Post Office Address:
`
`Inventor's Si,paturc
`
`Full Name of# Joint Inventor:
`Residence:
`Correspondence Post Office Address:
`
`....................................................................... , .............. .,....._.._.._ ... __ ........, ................................ , ..... _~ .................................. ~~-.... ~-. ....... .
`
`h":'i:~~v."':'.~·s·~~~~~:w
`
`Citizenship:
`
`Date:
`
`Citizenship:
`
`Date
`
`Rev 09105 (OecPwr)
`
`Page 2 of .2
`
`Nichia Exhibit 1002
`Page 4
`
`

`

`Attorney Docket No. 70030259-02
`
`SEMICONDUCTOR DEVICE WITH A LIGHT EMITTING
`
`SEMICONDUCTOR DIE
`
`RELATED APPLICATION
`
`5
`
`10
`
`[0001]
`
`This application is a continuation-in-part ofU.S. Patent Application
`
`Serial No. 10/608,605, filed June 27, 2003, which is related to U.S. Patent
`
`Application Serial No. 10/608,606, filed June 27, 2003. Both disclosures are
`
`specifically incorporated herein by reference.
`
`BACKGROUND OF THE INVENTION
`
`[0002]
`
`Many types of conventional semiconductor device are composed of a
`
`semiconductor die mounted in a packaging device. One type of packaging device
`
`15
`
`widely used in the industry includes a metal lead frame. A metallization layer of
`
`aluminum located on the bottom surface of the semiconductor die is bonded to a
`
`conductive surface that forms part of the lead frame to attach and electrically
`
`connect the die to the lead frame. Additionally, electrical connections are made
`
`between bonding pads on the top surface of the die and other leads of the lead
`
`20
`
`frame to provide additional electrical connections to the die. The lead frame and
`
`semiconductor die are then encapsulated to complete the semiconductor device.
`
`The packaging device protects the semiconductor die and provides electrical and
`
`mechanical connections to the die that are compatible with conventional printed
`
`circuit board assembly processes.
`
`25
`
`[0003]
`
`In such conventional semiconductor devices, the bottom surface of
`
`the die is typically bonded to the conductive surface of the lead frame using a
`
`silver epoxy adhesive that cures at a relatively low temperature, typically about
`
`120 °C. The curing temperature of the silver epoxy adhesive is compatible with
`
`the other materials of the packaging device.
`
`30
`
`[0004]
`
`The volume of the packaging device used in such conventional
`
`semiconductor devices, i.e., the lead frame and the encapsulant, is typically many
`
`times that of the semiconductor die. This makes such conventional semiconductor
`
`devices unsuitable for use in applications in which a high packing density is
`
`1
`
`Nichia Exhibit 1002
`Page 5
`
`

`

`Attorney Docket No. 70030259-02
`
`required. A high packing density allows miniaturization and other benefits.
`
`Therefore, what is needed is a semiconductor packaging device that is comparable
`
`in volume with the semiconductor die and that is compatible with conventional
`
`printed circuit board assembly processes.
`
`5
`
`[0005]
`
`Recently, semiconductor die having a substrate surface metallization
`
`layer of a gold-tin alloy (80% Au:20% Sn approximately) have been introduced in
`
`light-emitting devices. Such semiconductor die typically have a substrate of
`
`sapphire, silicon carbide or a Group III-V semiconductor material, such as gallium
`
`arsenide. Semiconductor devices having substrates of the first two substrate
`1 o materials have layers of Group III-V semiconductor materials, such as gallium
`nitride, deposited on their substrates. The die attach process for such
`
`semiconductor die uses a gold-tin eutectic, which has a melting point of about 280
`°C. Temperatures as high as about 350 oc can be encountered in the die attach
`process for such die. Such high temperatures are incompatible with the materials
`
`15
`
`of many conventional packaging devices. Thus, what is also needed is a
`
`packaging device for semiconductor die that use a high-temperature die attach
`
`process.
`
`[0006]
`
`Many printed circuit assembly processes and assembly equipment
`
`require the use of standard semiconductor device packages. Modifying such
`
`20
`
`processes to use a new semiconductor device package can be expensive and can
`
`interrupt production. Therefore, what is additionally needed is a way to mount a
`
`semiconductor die that requires a high-temperature die attach process in a
`
`conventional packaging device.
`
`25
`
`SUMMARY OF THE INVENTION
`
`[0007]
`
`A semiconductor device includes a light emitting semiconductor die
`
`mounted on at least one of first and second electrically conductive bonding pads,
`
`which are located on a first major surface of a substrate of the device. The light
`
`30
`
`emitting semiconductor die has an anode and a cathode, which are electrically
`
`connected to the first and second electrically conductive bonding pads. The
`
`semiconductor device further includes first and second electrically conductive
`
`connecting pads, which are located on a second major surface of the substrate.
`
`2
`
`Nichia Exhibit 1002
`Page 6
`
`

`

`Attorney Docket No. 70030259-02
`
`The first and second electrically conductive bonding pads are electrically
`
`connected to the first and second electrically conductive connecting pads via first
`
`and second electrically conductive interconnecting elements.
`
`[0008]
`
`A semiconductor device in accordance with an embodiment of the
`
`5
`
`invention includes a substantially planar substrate, first and second electrically
`
`conductive bonding pads, a light emitting semiconductor die, first and second
`
`electrically conductive connecting pads, and first and second electrically
`
`conductive interconnecting elements. The substantially planar substrate has first
`
`and second major surfaces. The first and second major surfaces are opposed
`
`1 o
`
`surfaces. The first and second electrically conductive bonding pads are located on
`
`the first major surface. The light emitting semiconductor die has at least one of an
`
`anode and a cathode on a bottom major surface of the light emitting
`
`semiconductor die. The anode and the cathode of the light emitting
`
`semiconductor die are electrically connected to the first and second electrically
`
`15
`
`conductive bonding pads. The semiconductor light emitting die is mounted on at
`
`least the first electrically conductive bonding pad such that one of the anode and
`
`the cathode on the bottom major surface of the light emitting semiconductor die is
`
`electrically connected to the first electrically conductive bonding pad. The first
`
`and second electrically conductive connecting pads are located on the second
`
`20 major surface. The first electrically conductive interconnecting element is
`
`electrically connected to the first electrically conductive bonding pad and the first
`
`electrically conductive connecting pad. The second electrically conductive
`
`interconnecting element is electrically connected to the second electrically
`
`conductive bonding pad and the second electrically conductive connecting pad. In
`
`25
`
`an embodiment, at least one of the first and second electrically conductive
`
`interconnecting elements is located on at least one sidewall of the substantially
`
`planar substrate.
`
`[0009]
`
`A semiconductor device in accordance with another embodiment of
`
`the invention includes a substantially planar substrate, first and second electrically
`
`30
`
`conductive bonding pads, a light emitting semiconductor die, first and second
`
`electrically conductive connecting pads, and first and second electrically
`
`conductive interconnecting elements. The substantially planar substrate has first
`
`and second major surfaces. The first and second major surfaces are opposed
`
`3
`
`Nichia Exhibit 1002
`Page 7
`
`

`

`Attorney Docket No. 70030259-02
`
`surfaces. The first and second electrically conductive bonding pads are located on
`
`the first major surface. The light emitting semiconductor die has an anode and a
`
`cathode on a bottom major surface of the light emitting semiconductor die. The
`
`semiconductor light emitting die is mounted on the first and second electrically
`
`5
`
`conductive bonding pads such that the anode of the light emitting semiconductor
`
`die is electrically connected to the first electrically conductive bonding pad and
`
`the cathode of the light emitting semiconductor die is electrically connected to the
`
`second electrically conductive bonding pad. The first and second electrically
`
`conductive connecting pads are located on the second major surface. The first
`
`1 o
`
`electrically conductive interconnecting element is electrically connected to the
`
`first electrically conductive bonding pad and the first electrically conductive
`
`connecting pad. The second electrically conductive interconnecting element is
`
`electrically connected to the second electrically conductive bonding pad and the
`
`second electrically conductive connecting pad
`
`15
`
`[0010]
`
`Other aspects and advantages of the present invention will become
`
`apparent from the following detailed description, taken in conjunction with the
`
`accompanying drawings, illustrated by way of example of the principles of the
`
`invention.
`
`20
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0011]
`
`FIGS. IA, IB, IC, ID, IE and IF are respectively an isometric view,
`
`a side view, a front view, a top view, a bottom view and a cross-sectional view of
`
`a first embodiment of a packaging device in accordance with the invention. The
`
`25
`
`cross-sectional view of FIG. IF is along the section line IF-IF in FIG. ID.
`
`[0012]
`
`FIGS. 2A, 2B, 2C, 2D, 2E and 2F are respectively an isometric view,
`
`a side view, a front view, a top view, a bottom view and a cross-sectional view of
`
`a first embodiment of a semiconductor device in accordance with the invention.
`
`The cross-sectional view of FIG. 2F is along the section line 2F-2F in FIG. 2D.
`
`30
`
`[0013]
`
`FIGS. 3A, 3B, 3C, 3D, 3E and 3F are respectively an isometric view,
`
`a side view, a front view, a top view, a bottom view and a cross-sectional view of
`
`a second embodiment of a packaging device in accordance with the invention.
`
`The cross-sectional view of FIG. 3F is along the section line 3F-3F in FIG. 3D.
`
`4
`
`Nichia Exhibit 1002
`Page 8
`
`

`

`Attorney Docket No. 70030259-02
`
`[0014]
`
`FIGS. 4A, 4B, 4C, 4D, 4E and 4F are respectively an isometric view,
`
`a side view, a front view, a top view, a bottom view and a cross-sectional view of
`
`a second embodiment of a semiconductor device in accordance with the invention.
`
`The cross-sectional view of FIG. 4F is along the section line 4F-4F in FIG. 4D.
`
`5
`
`[0015]
`
`FIGS. 5A-5C are side views illustrating a method in accordance with
`
`the invention for fabricating a packaging device for a semiconductor die.
`
`[0016]
`
`FIG. 5D is a side view illustrating an optional additional process that
`
`may be included in the method illustrated in FIGS. 5A-5C.
`
`[0017]
`
`FIGS. 6A-6D are side views illustrating a method in accordance with
`
`10
`
`the invention for fabricating a semiconductor device.
`
`[0018]
`
`FIGS. 7 A and 7B are respectively a top view and a side view of a
`
`semiconductor device in accordance with another embodiment of the invention.
`
`[0019]
`
`FIGS. 8A, 8B and 8C are respectively a top view and different side
`
`views of a semiconductor device in accordance with another embodiment of the
`
`15
`
`invention.
`
`DETAILED DESCRIPTION
`
`[0020]
`
`FIGS. lA-lF are schematic diagrams illustrating a first exemplary
`
`20
`
`embodiment 100 of a packaging device for a semiconductor die in accordance
`
`with the invention. Packaging device 100 is composed of a substrate 110,
`
`interconnecting elements 120 and 122, a mounting pad 130, a bonding pad 132
`
`and connecting pads 140 and 142 (FIG. IE).
`
`[0021]
`
`Substrate 110 is substantially planar, has opposed major surfaces 112
`
`25
`
`and 114 and defines through holes 116 and 118 that extend through the substrate
`
`between major surfaces 112 and 114. Interconnecting element 120 is electrically
`
`conductive and is located in through hole 116. Interconnecting element 122 is
`
`electrically conductive and is located in through hole 118. Mounting pad 130 and
`
`bonding pad 132 are electrically conductive, are separate from one another and are
`
`30
`
`located on the portions of the major surface 112 of substrate 110 in which through
`
`holes 116 and 118 are respectively located. Connecting pads 140 and 142 are
`
`electrically conductive, are separate from one another and are located on the
`
`5
`
`Nichia Exhibit 1002
`Page 9
`
`

`

`Attorney Docket No. 70030259-02
`
`portions of the major surface 114 of substrate 110 in which through holes 116 and
`
`118 are respectively located.
`
`[0022]
`
`Mounting pad 130 and connecting pad 140 are electrically connected
`
`to opposite ends of interconnecting element 120. Thus, interconnecting element
`
`5
`
`120 extending through substrate 110 in through hole 116 electrically connects
`
`mounting pad 130 to connecting pad 140. Bonding pad 132 and connecting pad
`
`142 are electrically connected to opposite ends of interconnecting element 122.
`
`Thus, interconnecting element 122 extending through substrate 110 in through
`
`hole 118 electrically connects bonding pad 132 to connecting pad 142.
`
`10
`
`[0023]
`
`The material of substrate 110 is a thermally-conductive ceramic such
`
`as alumina or beryllia. In an embodiment, the material of the substrate was
`
`Kyocera.RTM. Type A440 ceramic sold by Kyocera Corp., of Kyoto, Japan.
`
`Typical dimensions of the substrate are in the range from about 0.5 mm square to
`
`about 2 mm square. Rectangular configurations are also possible. Alternative
`
`15
`
`substrate materials include semiconductors, such as silicon, and epoxy laminates,
`
`such as those used in printed-circuit boards. Other materials that have a high
`
`thermal conductivity and a low electrical conductivity can be used instead of those
`
`exemplified above. The coefficient of thermal expansion of the substrate material
`
`relative to that of the semiconductor die to be mounted on packaging device 100
`
`20
`
`should also be considered in choosing the substrate material.
`
`[0024]
`
`As will be described in more detail below, substrate 110 is part of a
`
`wafer (not shown) from which typically several hundred packaging devices 100
`
`are fabricated by batch processing. After fabrication of the packaging devices, the
`
`wafer is singulated into individual packaging devices. Alternatively, the
`
`25
`
`packaging devices may be left in wafer form after fabrication. In this case,
`
`singulation is not performed until after at least a die attach process has been
`
`performed to attach a semiconductor die to each mounting pad 130 on the wafer.
`
`In some embodiments, wafer-scale wire bonding, encapsulation and testing are
`
`also performed prior to singulation. Full electrical testing, including light output
`
`30
`
`testing, may be performed on the wafer.
`
`[0025]
`
`The material of interconnecting elements 120, 122 is metal or
`
`another electrically-conductive material. In an embodiment, the material of the
`
`interconnecting elements is tungsten, but any electrically-conductive material
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`Attorney Docket No. 70030259-02
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`capable of forming a low-resistance electrical connection with the pads, i.e.,
`
`mounting pad 130, bonding pad 132 and connecting pads 140, 142, and capable of
`
`withstanding the temperature of the die-attach process may be used. As noted
`
`5
`
`above, packaging device 100 may be subject to a temperature as high as about 350
`oc when a gold-tin eutectic is used to attach a semiconductor die to the mounting
`pad 130 of the packaging device. Interconnecting elements 120, 122 may be
`
`located relative to mounting pad 130 and bonding pad 132, respectively,
`
`elsewhere than the centers shown. Moreover, more than one interconnecting
`
`element may be located within either or both of the mounting pad and the bonding
`
`10
`
`pad.
`
`[0026]
`
`The material of pads 130, 132, 140, 142 is metal or another
`
`electrically-conductive material. Important considerations in selecting the
`
`material of the pads are adhesion to substrate 110, an ability to form a durable,
`
`low-resistance electrical connection with interconnecting elements 120 and 122
`
`15
`
`and an ability to withstand the temperature of the die attach process. In an
`
`embodiment, the structure of the pads is a seed layer of tungsten covered with
`
`layer of nickel about 1.2 J..Lm to about 8.9 J..Lm thick that is in turn covered with a
`
`layer of gold about 0.75 J..Lm thick. Other metals, alloys, conductive materials and
`
`multi-layer structures of such materials can be used.
`
`20
`
`[0027]
`
`Packaging device 100 is used to package a semiconductor die. A
`
`semiconductor device in which a semiconductor die is packaged using packaging
`
`device 1 00 described above will be described next.
`
`[0028]
`
`FIGS. 2A-2F are schematic diagrams illustrating an exemplary
`
`embodiment 200 of a semiconductor device in accordance with the invention.
`
`25
`
`Semiconductor device 200 incorporates packaging device 100 in accordance with
`
`the invention. Elements of semiconductor device 200 that correspond to elements
`
`of packaging device 100 described above with reference to FIGS. 1A-1F are
`
`indicated using the same reference numerals and will not be described again in
`
`detail.
`
`30
`
`[0029]
`
`Semiconductor device 200 is composed of packaging device 100
`
`described above with reference to FIGS. 1A-1F, a semiconductor die 250,
`
`encapsulant 252 and a bonding wire 254. In the example shown, semiconductor
`
`die 250 embodies a light-emitting diode and has anode and cathode electrodes (not
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`Attorney Docket No. 70030259-02
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`shown) covering at least parts of its opposed major surfaces. Semiconductor die
`
`250 is mounted on packaging device 100 with the metallization on its bottom
`
`major surface attached to mounting pad 130. Encapsulant 252 covers the
`
`semiconductor die and the part of the major surface 112 of substrate 1 00 where
`
`5 mounting pad 130 and bonding pad 132 are located. Bonding wire 254 extends
`
`between a bonding pad located on the top major surface of semiconductor die 250
`
`and bonding pad 132.
`
`[0030]
`
`The bonding pad on the top major surface of semiconductor die 250
`
`is typically part of or connected to the anode electrode of the light-emitting diode.
`
`10
`
`The metallization on the bottom major surface of semiconductor die 250 typically
`
`constitutes the cathode electrode of the light-emitting diode. Thus, the anode
`
`electrode of semiconductor die 250 is electrically connected to connecting pad
`
`142 by bonding wire 254, bonding pad 132 and interconnecting element 122, and
`
`the cathode electrode of semiconductor die 250 is electrically connected to
`
`15
`
`connecting pad 140 by mounting pad 130 and interconnecting element 120.
`
`[0031]
`
`Encapsulant 252 has a thickness greater than the maximum height of
`
`bonding wire 254 above major surface 112. In the example shown, the
`
`encapsulant is transparent to enable semiconductor device 200 to emit the light
`
`generated by semiconductor die 250.
`
`20
`
`[0032]
`
`Semiconductor die 250 is composed of one or more layers (not
`
`shown) of any semiconductor material composed of elements from Groups II, III,
`
`IV, V and VI of the periodic table in binary, ternary, quaternary or other form.
`
`Semiconductor die 250 may additionally include a non-semiconductor substrate
`
`material, such as sapphire, metal electrode materials and dielectric insulating
`
`25 materials, as is known in the art.
`
`[0033]
`
`In an embodiment of the above-described example in which
`
`semiconductor die 250 embodies a light-emitting diode, semiconductor die 250 is
`
`composed of a substrate of silicon carbide that supports one or more layers of
`
`(indium) gallium nitride. Such a light-emitting diode generates light in a
`
`30 wavelength range extending from ultra-violet to green. The bottom major surface
`
`(not shown) ofthe substrate remote from the layers of(indium) gallium nitride is
`
`coated with a metallization layer of a gold-tin alloy. A gold-tin eutectic attaches
`
`the semiconductor die to mounting pad 130, as described above, to provide a
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`Attorney Docket No. 70030259-02
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`mechanical and electrical connection between the semiconductor die and the
`
`mounting pad.
`
`[0034]
`
`The material of bonding wire 254 is gold. A process known in the
`
`art as low-loop wire bonding is used to connect the bonding wire between the
`
`5
`
`anode electrode of semiconductor die 250 and bonding pad 132. Using low-loop
`
`wire bonding minimizes the maximum height of the bonding wire above substrate
`
`110, and, therefore, reduces the overall height of semiconductor device 200.
`
`Other processes for providing an electrical connection between a bonding pad on a
`
`semiconductor die and a bonding pad on a packaging device are known in the art
`
`1 o
`
`and may be used instead, especially in applications in which device height is a less
`
`important consideration.
`
`[0035]
`
`The material of encapsulant 252 is clear epoxy. Alternative
`
`encapsulant materials include silicone. Embodiments of semiconductor device
`
`200 that neither emit nor detect light can use an opaque encapsulant.
`
`15
`
`[0036]
`
`In the example of semiconductor device 200 described above,
`
`semiconductor die 250 is embodied as a light-emitting diode. Semiconductor die
`
`250 may alternatively embody another type of diode without modification to
`
`packaging device 100. Versions of packaging device 100 may be used to package
`
`semiconductor die other than those that embody such electrical components as
`
`20
`
`diodes that have only two electrodes. Versions of packaging device 100 may be
`
`used to package semiconductor die that embody such electronic circuit elements
`
`as transistors and integrated circuits that have more than two electrodes. Such
`
`versions of packaging device 100 have a number of bonding pads, interconnecting
`
`elements and connecting pads corresponding to the number of bonding pads
`
`25
`
`located on the top major surface ofthe semiconductor die. For example, a version
`
`of packaging device 1 00 for packaging a semiconductor die that embodies a
`
`transistor having collector, base and emitter electrodes, and in which the substrate
`
`metallization provides the collector electrode, has two bonding pads, two
`
`interconnecting elements and two connecting pads. Wire bonds connect the
`
`30
`
`emitter bonding pad on the semiconductor die to one of the bonding pads on the
`
`packaging device and the base bonding pad on the semiconductor die to the other
`
`of the bonding pads on the packaging device.
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`Attorney Docket No. 70030259-02
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`[0037]
`
`The connecting pads, e.g., connecting pads 140 and 142, of
`
`embodiments of packaging device 100 having multiple connecting pads may be
`
`arranged to conform with an industry standard pad layout to facilitate printed
`
`circuit layout. In such embodiments, the interconnecting elements may be offset
`
`5
`
`from the centers of the respective mounting pads, bonding pads and connecting
`
`pads to allow the connecting pad layout to conform with such a standard pad
`
`layout. In some embodiments, one or more of the mounting pad, bonding pads
`
`and connecting pads may have a shape that differs from the regular shapes
`
`illustrated. Some irregular shapes include two main regions electrically connected
`
`10
`
`by a narrow track. For example, an irregularly-shaped bonding pad includes a
`
`region to which the bonding wire is attached, a region connected to the
`
`interconnecting element and a narrow track interconnecting the two regions.
`
`[0038]
`
`Some versions of packaging device may accommodate two or more
`
`semiconductor die. In such versions, mounting pad 130 is sized large enough to
`
`15
`
`accommodate the two or more semiconductor die. Additionally, such versions
`
`include sufficient bonding pads, interconnecting elements and connecting pads to
`
`make the required number of electrical connections to the semiconductor die.
`
`Alternatively, the packaging device may