United States Patent
`Koslov et al.
`
`[19]
`
`[11] Patent Number:
`
`5,940,450
`
`[45] Date of Patent:
`
`Aug. 17, 1999
`
`USt'10594-045t1A
`
`[58]
`
`[56]
`
`[54] CARRIER RECOVERY METHOD AND
`APPARA'I‘US
`
`[75]
`
`Inventors: Joshua L. Koslov, Hopewell; Frank A.
`Lane, Medt'ord Lakes, both of NJ.
`
`[73] Assignee: Hitachi America, ”(1.. Tarrytown. NY.
`
`[21] App]. No.: 08,807,565
`
`[22]
`
`Filed:
`
`Feb. 28, 1997
`
`Int. CH"
`[51]
`[52] US. Cl.
`
`H04L 27106
`375844; 375526; 375t329;
`375K331
`Field of Search ..................................... 375t326. 327.
`3757340. 329. 324, 334. 325, 371, 375.
`344, 260
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`4,308,505
`5,471,508
`5,519.356
`5,519,733
`5,594,758
`5,799,037
`
`12,0981 Messerschmill
`117’1995 Koslov .............
`
`5.319% Grenherg .
`57'1996 Huang ..........
`
`151997 Pelranovich .
`8.31998 Stroll et al.
`
`33lt25
`375L344
`375.844
`370,844
`375L344
`375,323
`
`OTHER PUBLICATIONS
`
`Neil K. Jablon. “Joint Blind Equalization. Carrier Recovery.
`and Timing Recovery for High-Order 0AM Signal (Ton-
`stellations", IEEE Transactions on Signal Pmcessing. vol.
`40, No. 6, pp. 1383—1398. Jun. 1992.
`Neil K. Jablon. “Joint Blind Equalization. Carrier Recovery.
`and Timing Recovery for 64—OAM and 128 0AM Signal
`Constellations". Record of lEEE International Conference
`on Communications (Boston, MA). Jun. 11-84, 1989, pp.
`lU43-1049.
`
`Albert Benveniste and Maurice Gou rsat. "Blind Equalizers".
`Transactions on Communications. vol. Com-32. No. 8. pp.
`871—883, Aug. 1984.
`
`Prittmry Exatttt'tter—Chi H. Pham
`Assistant Exatttr'ner—Bayard Emmanuel
`Attorney. Agent, or Firttt—Michaelson 8t. Wallace; Peter L.
`Michaelson; Michael P. Straub
`
`[57]
`
`ABSTRACT
`
`Improved carrier recovery methods and apparatus suitable
`for use with QAM. QPSK and a wide variety of other
`modulation formats is described. In accordance with the
`
`invention, the phase error between received symbols, rep-
`resenting a frequency error, is determined using one of a
`plurality of techniques. The estimated frequency error is
`used to adjust the phase andtor frequency of a received
`carrier signal to achieve a frequency lock. The methods and
`apparatus of the present invention can be easily integrated
`into existing carrier recovery designs to supplement known
`frequency In accordance with a first embodiment of the
`present invention. the receipt of pairs of consecutive outer
`symbols is detected, a frequency error associated with each
`pair of consecutive symbols is generated. and the frequency
`error is compared to a selected threshold value to determine
`if it is a non-ambiguous estimate of the frequency error. If
`the frequency error is non-ambiguous and from a pair of
`consecutive outer symbols. it is used to adjust the frequency
`andtor phase of a received carrier signal. In the second
`embodiment. the receipt of pairs ofccmscculivc outer sym-
`hols are detected. An estimate of the frequency error, deter-
`mined as the phase error between received symbols, is made
`in the second embodiment by doing a symbol to symbol, as
`opposed to a symbol to target comparison.
`
`26 Claims, 7 Drawing Sheets
`
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`Petitioner Sirius XM Radio Inc. - Ex. 1009, p. 1
`
`Petitioner Sirius XM Radio Inc. - Ex. 1009, p. 1
`
`

`

`US. Patent
`
`Aug. 17, 1999
`
`Sheet 1 0f 7
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`5,940,450
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`PRIOR ART
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`Petitioner Sirius XM Radio Inc. - Ex. 1009, p. 2
`
`Petitioner Sirius XM Radio Inc. - Ex. 1009, p. 2
`
`

`

`US. Patent
`
`Aug. 17, 1999
`
`Sheet 2 0f 7
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`5,940,450
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`Petitioner Sirius XM Radio Inc. - Ex. 1009, p. 3
`
`Petitioner Sirius XM Radio Inc. - Ex. 1009, p. 3
`
`

`

`US. Patent
`
`Aug. 17, 1999
`
`Sheet 3 0f 7
`
`5,940,450
`
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`Petitioner Sirius XM Radio Inc. - Ex. 1009, p. 4
`
`Petitioner Sirius XM Radio Inc. - Ex. 1009, p. 4
`
`

`

`US. Patent
`
`Aug. 17, 1999
`
`Sheet 4 0f 7
`
`5,940,450
`
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`Petitioner Sirius XM Radio Inc. - Ex. 1009, p. 5
`
`Petitioner Sirius XM Radio Inc. - Ex. 1009, p. 5
`
`

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`Petitioner Sirius XM Radio Inc. - Ex. 1009, p. 6
`
`Petitioner Sirius XM Radio Inc. - Ex. 1009, p. 6
`
`

`

`US. Patent
`
`Aug. 17, 1999
`
`Sheet 6 0f 7
`
`5,940,450
`
`FREQUENCY ERROR DETECTION CIRCUIT
`
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`Petitioner Sirius XM Radio Inc. - Ex. 1009, p. 7
`
`Petitioner Sirius XM Radio Inc. - Ex. 1009, p. 7
`
`

`

`US. Patent
`
`Aug. 17,1999
`
`Sheet 7 0f 7
`
`5,940,450
`
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`Petitioner Sirius XM Radio Inc. - Ex. 1009, p. 8
`
`Petitioner Sirius XM Radio Inc. - Ex. 1009, p. 8
`
`

`

`5,940,450
`
`1
`CARRIER RECOVERY METHOD AND
`APPARATUS
`
`FIELD OF THE INVENTION
`
`invention is directed to carrier recovery
`The present
`methods and apparatus and. more particularly. to improved
`carrier recovery methods and apparatus suitable for use in,
`e.g.. 0AM (quadrature amplitude modulation) andror QPSK
`(quadrature phase shift keying) demodulators.
`
`10
`
`BACKGROUND OF THE INVENTION
`
`15
`
`The transmission of various types of information as
`digital data continues to grow in importance. Quadrature
`amplitude modulation (0AM) and Quadrature phase shift
`keying (QPSK) are increasingly seeing use as an attractive
`vehicle to transmit digital data.
`As will be discussed in detail below, the carrier recovery
`methods and apparatus of the present invention may be used
`with QAM, QPSK and a variety of other types of modulated
`signals. For purposes of explanation, the methods and appa-
`ratus of the present invention will be explained in the context
`of an exemplary 0AM demodulator embodiment. 0AM and
`known 0AM carrier recovery will now be briefly discussed.
`In essence, QAM relies on transmitting data as a sequence
`of two-dimensional complex symbols.
`i.e. with both
`in-phase and quadrature components. Each symbol, based
`upon the data it represents. takes on a specific pre-defined
`value. A set of all of the values available for transmission
`delines an alphabet which. when graphically plotted, typi-
`cally on a two-dimensional basis, forms a constellation. The
`size and shape of the constellation depends upon the number
`of discrete values in the set and their spatial location in the
`constellation. The constellation frequently proposed for use
`in broadcasting. e.g., high definition television {I-lD'I‘V) data ‘
`contains. e.g.. 16, 32 or 64 valtJes (states), hence so-called
`[6, 32 or 64 OM, respectively.
`FIG. 1 illustrates a lG-QAM constellation. Each symbol
`in the constellation is denoted by an “".x In known 16 (JAM
`the permissible nominal symbol values for both the x and y
`coordinates is (3:1. :3) with the nominal squared magnitudes
`being approximately 2. 10 and 18. Constellation 110 ordi~
`narily contains three rings corresponding to the squared
`symbol magnitudes 2. 10. 18. of which only the inner most
`and middle rings 113. 117. respectively. are specifically
`shown.
`
`40
`
`45
`
`To receive broadcast 0AM data, a 0AM receiver essen-
`tially samples and filters a received output of a communi-
`cation channel. and applies resulting filtered samples to a
`decoder (e.g. a Viterbi decoder}, which contains one or more
`slicers. to yield detected symbols. The data contained in
`these latter symbols.
`if
`it contains compressed video
`information. is then appropriately decompressed to yield
`original source video data. To specifically accomplish QAM _
`reception, a QAM demodulator within the receiver performs
`the functions of tinting recovery, equalization and carrier
`recovery.
`
`50
`
`2
`of varying frequency ofisets, e.g.. drift or jitter that often
`occur between a transmitter and receiver. The input to a
`carrier recovery circuit is normally equalized symbols.
`FIG. 2 illustrates a known carrier recovery circuit 101. As
`illustrated the carrier
`recovery circuit 101 includes a
`de-rotator 102. a phase detector 104. loop filter 110, phase
`accumulator 112. ROM 114 for storing a SINE, COSINE
`lookup table, and a slicer module 106. A mode select control
`circuit 1.18 is also included to control switching between
`acquisition and tracking modes of operation. The carrier
`recovery circuit 101 may be the same as. or similar to. that
`described in US. Pat. No. 5,471,508 which describes one of
`Applicant’s earlier inventions in detail. In the illustrated
`embodiment. the slicer module 106 operates. in response to
`a control signal output by the mode select control circuit
`118.
`in either an acquisition or tracking mode. In carrier
`recovery circuits which do not support distinct tracking and
`acquisition modes of operation the acquisition module 122
`is omitted from the slicer module 106 and the mode select
`control circuit 118 is also omitted.
`As will be discussed below. various embodiments of the
`present invention can be used with carrier recovery circuits
`which support such distinct, e.g.. acquisition and tracking.
`modes of carrier recovery operation as well as carrier
`recovery circuits which support only a single. e.g.. tracking.
`mode of operation.
`In the carrier recovery circuit 101, carrier recovery is
`performed through the use of a digital phase-locked loop
`(DPLL) in which a reference carrier. on leads 165.
`is
`fabricated for use in dis-rotating incoming equalized sym-
`bols. To assure that the reference carrier is accurate. i.e. this
`carrier properly responds in the presence of jitter in the
`received signal or frequency andtor phase shifts between the
`transmitter and receiver. and thus can be used to properly
`de-rotate the equalized symbols, this carrier is adjusted, in
`Icons of both a frequency and phase,within the DPLl.based
`on an estimate of the phase error ((12,) that occurs between
`each de-rotatcd symbol and its corresponding ideal sliced
`value.
`
`Specifically. incoming equalived symbols are applied to a
`first input of de-rotator 102 while quadrature outputs of a
`sine generator, specifically the sine, cosine table stored in
`read only memory (ROM) 114. are applied to a second input
`of the tie-rotator 102. For any input
`to the table 114, the
`corresponding sine output produces the in-phase component
`of the reference carrier;
`the corresponding cosine output
`produces the quadrature component of this carrier. The input
`address to ROM 114 is an integrated phase error generated
`by the phase accumulator 112.
`The phase error signal is first synthesized by estimating
`the phase error between each incoming equalized de-rotated
`symbol (ZREC) and its corresponding ideal sliced value
`therefor (25;). In particular, each de-rotated symbol pro-
`duced by de-rotator 102 is supplied to a first input of the
`phase detector 104 and to the input to the slicer module 106.
`The phase detector 104 is implemented using a half-complex
`multiplier 108.
`In the illustrated embodiment, slicer module 106 includes
`a full slicer 120 and a reduced slicer 122. The full slicer
`
`In 0AM and QPSK carrier recovery is typically per-
`formed on a decision directed basis and in the absence of a
`pilot
`tone. Carrier recovery creates a reference carrier
`against which in-phase and quadrature modulated compo-
`nents may be determined. e.g.. both in terms of frequency
`and phase. such that the received demodulated symbols do
`not rotate. It is the carrier signal that is quadrature modulated
`by the symbols and then transmitted to a receiver. Carrier
`recovery must be able to properly function in the presence
`
`00
`
`generates an output for each of the received symbols by
`comparing them to the full set of 16 possible ideal values (in
`the case of 16 0AM) and selecting the one of the 16 possible
`ideal values closest to the input symbol value, as the full
`slicer‘s output. The reduced slicer 122 generates ideal sliced
`.‘ value outputs for outer. i.e.. non-inner. symbols, e.g.. outer
`corner symbols 1191,1192, 1193,1194, and outputs a zero as
`the sliced value (ZREC) when an inner symbol is received.
`
`Petitioner Sirius XM Radio Inc. - Ex. 1009, p. 9
`
`Petitioner Sirius XM Radio Inc. - Ex. 1009, p. 9
`
`

`

`5,940,450
`
`4
`which the second order accumulator can integrate to thereby
`generate an accurate frequency error signal.
`Accordingly. there is a need for improved carrier recovery
`circuits which can achieve a frequency lock in less time than
`existing carrier recovery circuits. particularly where large
`frequency errors exit. It is desirable that any such improved
`carrier recovery circuits be relatively easy to implement. It
`is also desirable, at least in some cases, that the improved
`carrier recovery circuits be capable of being easily combined
`with existing carrier recovery circuits thereby avoiding the
`need to entirely redesign various existing circuits. For maxi-
`mum versatility.
`it
`is also beneficial
`that any improved
`carrier recovery techniques be suitable for use with multiple
`modulation schemes.
`
`SUMMARY OF THE PRESENT INVENTION
`
`10
`
`15
`
`TJ III
`
`3
`The reduced slicer 122 can be implemented by first
`comparing the magnitude of receiver] symbol to a prese-
`lected threshold value to determine if is an outer symbol.
`When the threshold is not exceed, indicating a received
`symbol is an inner symbol a zero is output. However. if a
`received symbol is determined to be an outer symbol, it is
`compared to a reduced set of ideal symbol values. e.g.. four
`when only the outer four points are being used for acquisi-
`tion purposes, and the closest matching value is output. In
`such an embodiment. during acquisition mode when the
`reduced complexity slicer is used, the estimated phase error
`will be zero for
`received inner symbols.
`In such an
`embodiment. the received inner symbol will have little or no
`effect on constellation positioning.
`M discussed in U.S. Pat. No. 5,471,508 outer symbols
`have a longer radii and thus a larger signal to additive-plus-
`adaptive noise ratio than inner symbols. Theory suggests
`that. for this reason. outer symbols generally provide more
`reliable information regarding the current orientation of the
`constellation than inner symbols. By using only such outer
`symbols for phase error estimates when the ambiguity
`regarding phase errors are the highest. e.g.. during acquisi-
`tion mode. fasterlock on can be achieved as compared to the
`case where both the less reliable phase error estimates
`generated from inner symbols and the more reliable phase
`error estimates generated from outer symbols are used for
`correction purposes, e.g.. in the case where only a single
`mode of carrier recovery is. supported.
`A multiplexer 124. which is responsive to a mode select
`signal generated by the mode select control circuit 118 is
`used to control whether the output of the full or reduced
`slicer 120. 122 is supplied to the second input of the phase
`detector 108 at any given time. The mode select control
`circuit 118. which controLs. via the MUX 124, switching
`between acquisition and tracking slicer modes of operation.
`may be implemented using any one of a plurality of known
`techniques.
`The output of the phase detector 104. the estimated phase
`error l'l’.) between each de-rotated symbol and its corre-
`sponding sliced value. is calculated as being an imaginary
`part of the complex product of the equalized de-rotated
`symbol and the conjugate (2,3) of the sliced value(Z_,.,). That
`is:
`
`Tr'fmwnzczxa ‘ "lzmrc l lzsr. ‘ ls l “I Wart-$51 Flzurrrl I?"
`
`where it)“ is the actual phase error as opposed to the
`estimated phase error (ilk);
`per is the phase of the received symbol; and
`a)“ is the (desired) phase of the sliced symbol.
`In the known system of FIG. 2. the scalar phase error (ilk-l
`is applied to an input of second-order loop filter 110 and.
`from there. to phase integrator (accumulator) 112. A result-
`ing integrated (accumulated) phase error output by the phase
`accumulator 112 is applied as the input to ROM 114 which
`is responsible for generating the second input
`to the
`de-rotator as discussed above.
`
`While known carrier recovery circuits such as that illus-
`trated in FIG. 2 provide satisfactory carrier recovery under
`most conditions, such systems may still find it difficult and
`relatively time consuming to pull in extremely large fre-
`quency ofl‘sets. e.g., such as those that may be encountered
`where a large amount of signal jitter andfor poor signal
`transmission conditions exist.
`in a reasonable amount of
`time. This is because the phase detector output must have a
`significant biased DC component over a period of time
`
`The present invention relates to improved carrier recovery
`methods and apparatus. Unlike conventional phase error
`detection techniques which are directed to the estimation of
`phase errors between a received symbol and a target or
`sliced symbol,
`the present
`invention is directed to the
`detection and estimation of the phase error between con-
`secutive received symbols. Since the estimated phase error
`is a difi'erence of phase errors calculated over a period of
`time. e.g., two symbol time periods. it represents a carrier
`frequency error. i.e.. it is an estimation of the error between
`the frequency of the received signal and the actual carrier
`frequency. This frequency error is determined using one of
`a plurality of techniques.
`The estimated frequency error generated in accordance
`with the present invention is used to adjust the phase andior
`frequency of a received carrier signal. The frequency error
`estimation techniques of the present invention can be used
`with a variety of modulation methods including 0AM and
`QPSK modulation. Furthermore, the methods and apparatus
`of the present invention can be easily integrated into existing
`carrier recovery designs to supplement known frequency
`and phase error correction techniques.
`By using the phase and frequency error estimation and
`correction techniques of the present invention, in combina-
`tion with existing phase error estimation and correction
`techniques.
`large frequency offseLs can often be quickly
`pulled in even when the output of a conventional phase
`detector has a very small DC component.
`In accordance with a first embodiment of the present
`invention, the receipt of pairs of consecutive outer symbols
`is detected, a frequency error associated with each pair of
`consecutive symbols is generated. and the frequency error is
`checked to determine if it is a non-ambiguous estimate of the
`frequency error. If the frequency error is non-ambiguous,
`and from a pair of consecutive outer symbols. it is used to
`adjust the frequency andfor phase of a received carrier signal
`in an attempt to achieve or maintain a frequency lock with
`the received carrier signal. This may be done by supplying
`the frequency error signal to an input of a second order filter,
`the output of which is used. directly or indirectly. to control
`the phase andfor frequency of the received carrier signal.
`In the first embodiment, the detection of the receipt of a
`pair of consecutive outer symbols is performed in parallel
`with the frequency error estimation step. The receipt of a
`pair of consecutive outer symbols is detected by comparing
`the received magnitude of the received symbols to a prese-
`lected threshold value used to distinguish between inner and
`‘ outer symbols. Outer symbols are used for frequency error
`estimation purposes while inner symbols are not. The fre-
`quency error between outer symbols is calculated, in one
`
`*
`
`40
`
`45
`
`50
`
`55
`
`00
`
`Petitioner Sirius XM Radio Inc. - Ex. 1009, p. 10
`
`Petitioner Sirius XM Radio Inc. - Ex. 1009, p. 10
`
`

`

`5,940,450
`
`6
`apparatus be capable of being easily combined with existing
`carrier recovery designs to avoid having to totally redesign
`carrier recovery circuits. FIG. 3 illustrates a carrier recovery
`circuit implemented in accordance with a first embodiment
`of the present invention which is particularly well suited for
`use with existing carrier recovery circuit designs. As will
`become apparent from a review of FIGS. 2 and 3. the carrier
`recovery circuit of the present invention. illustrated in FIG.
`3, bears many similarities to the carrier recovery circuit 101
`of FIG. 2. Notably, however, the FIG. 3 embodiment difiers
`from the known embodiment by the presence of a new and
`novel frequency error detection ("FED") circuit 302 imple-
`mented in accordance with the present
`invention.
`In
`addition, the second order filter circuit 310 used in the FIG.
`3 embodiment. differs from the filter circuit 110 in that the
`filter circuit 310 is designed to receive both the frequency
`error signal generated by the FED circuit 302 and the phase
`error signal output by the phase detector 104. Components
`of the FIG. 3 carrier recovery circuit 300 which are the same
`as, or similar to, those of the known carrier recovery circuit
`101, will not be described again in detail for purposes of
`brevity.
`As illustrated in FIG. 3, the FED circuit 302 ofthe present
`invention receives as its inputs the estimated phase error
`signal output by the phase detector 104 and the mode select
`signal generated by the mode select control circuit 118 and
`the sliced symbols. As will be discussed in greater detail
`below, during acquisition modes of operation.
`the FED
`circuit 302 l) detects the receipt of consecutive outer
`symbols, 2) estimates the frequency error associated with
`each pair of sequentially received outer symbols; and 3}
`determines if the calculated frequency error is ambiguous. 1f
`the estimated frequency error is determined to be ambiguous
`the FED circuit 302 outputs a zero value which is supplied
`to a first input of the second order filter 310. However. if the
`estimated frequency error is determined to be reliable, it is
`supplied to the first input of the second order filter 310 and
`is used in generating the phase accumulator input signal. As
`illustrated. the second order filter 310 also receives as an
`input, the estimated phase error signal. This signal is also
`used when generating the input to the phase accumulator
`112.
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`embodiment of the present invention, by subtracting a phase
`error associated with the second symbol in a pair of outer
`symbols from a phase error associated with the first symbol
`in the pair of consecutive outer symbols.
`In accordance with a second embodiment of the present
`invention, the frequency error between consecutive symbols
`is once again determined. HoWever. in accordance with the
`frequency error estimation technique of
`the second
`embodiment. the phase error output by a phase detector is
`not used for purposes of frequency error estimation.
`Accordingly. the second embodiment does not require use of
`the output of a slicer for frequency error estimation pur-
`poses. As wit h the first embod iment. the second embodiment
`may include an outer symbol detection circuit and limit the
`frequency error esLimates to estimates associated with pairs
`of consecutively received outer symbols. As with the first
`embodiment,
`the frequency error signal generated by the
`second embodiment may be used directly or indirectly, to
`control and correct
`the phase auditor frequency of the
`received carrier signal.
`The various frequency error detection techniques of the
`present invention can be used alone or in combination with
`conventional phase error andi’or frequency error correction
`techniques. Furthermore, because the frequency error esti-
`mation and correction methods of the present invention are
`relatively easy to implement and can be readily incorporated
`into many existing carrier recover designs.
`they are well
`suited for a wide variety of carrier recovery applications.
`Many other features and embodiments of the present
`invention are described in detail below.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a diagram illustrating a 16 0AM constellation.
`Fl ('3. 2 illustrates a known carrier recovery circuit.
`F] (i. 3 is a block diagram of an improved carrier recovery
`circuit implemented in accordance with a first exemplary
`embodiment of the present invention.
`FIG. 4 is a block diagram of a frequency error detection
`circuit of the present invention suitable for use with the
`carrier recovery circuit illustrated in FIG. 3.
`FIG. 5 is a block diagram of an improved carrier recovery
`circuit implemented in accordance with a second exemplary
`embodiment of the present invention.
`FIG. 6 is a block diagram of a frequency error detection
`circuit of the present invention suitable for use with the
`carrier recovery circuit of FIG. 5.
`FIG. 7 illustrates signals generated at various points
`within the frequency error detection circuit
`illustrated in
`FIG. 6.
`
`DETAILED DESCRIPTION
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`By utiliaing the freqUency error signal generated by the
`FED circuit 302 to supplement existing phase error correc—
`tion techniques, large frequency ofi'sets can be pulled in. in
`less time then would normally be required. By virtue of
`using second-order filtering inherent in loop filter 310, the
`DPLL implemented in circuit 300 can attain a phase lock on
`a constellation formed of equalized symbols without
`a
`steady-state (D.C.) phase ofl'set as a
`function of input
`frequency ofilset, as would otherwise occur in the case of a
`first-order loop filter.
`The FED circuit 302, implemented in accordance with a
`first exemplary embodiment of the present invention will
`now be discussed in detail with reference to FIG. 4. The FED
`circuit 302 includes a consecutive outer symbol detection
`circuit 404, a frequency error estimation circuit 412. an
`ambiguity detector 418 and control logic including an AND
`gate 424 and a multiplexer ("MUX") 426. The control logic
`and MUX 426 are used in combination with the other
`circuitry to determine when the calculated frequency error is
`to be used, e.g., output by the frequency error detection
`circuit 312. A gain element 428 is also included in the FED
`circuit 302, to control the gain of the frequency error signal
`‘ and thus the amount of contribution the generated frequency
`error signal will have to the ultimate frequency and phase
`corrections which are made in response thereto.
`
`invention relates to _
`the present
`As discussed above,
`improved carrier recovery methods and apparatus. In accor-
`dance with the present
`invention a phase error between
`received symbols, e.g., outer symbols, which represean a
`carrier signal frequency error is calculated using new and
`novel techniques. In accordance with the present invention
`this frequency error is used. either alone or in combination
`with other frequency or phase error estimates, generated
`e.g., using known techniques, to adjust the frequency andfor
`phase of the received carrier signal.
`A first embodiment of the present invention will now be
`described with reference to FIG. 3. As discussed above, it is
`desirable that new improved carrier recovery methods and
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`Petitioner Sirius XM Radio Inc. - Ex. 1009, p. 11
`
`Petitioner Sirius XM Radio Inc. - Ex. 1009, p. 11
`
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`For the reasons discussed above, when a constellation is
`totaling. it is not possible to make a good estimation of the
`phase error based upon a fully sliced decision directed
`system. However, outer received symbols may provide
`useful phase error information, even in the presence of
`relatively large phase olisets and regardless of the state of
`equalization. In fact. even before a rotating constellation is
`fully equalized and the carrier recovered, in accordance with
`the present invention, one can estimate a useful frequency
`offset using outer received symbols in many instances.
`In accordance with the present invention, the estimated
`phase error signals generated by the slicer module 106 for
`consecutively received outer symbols is used to generate a
`frequency error signal that is an estimate of the carrier phase
`error over a two symbol
`time period. This operation is
`performed by the frequency error estimator circuit 412. The
`circuit 412 subtracts. from the phase error associated with a
`current symbol 1),, the phase error associated with an imme-
`diately preceding symbol 4);.
`The frequency error estimation circuit 412 includes a
`delay element 414 and a summer 416. The delay element
`414 receives as its input the estimated phase error signal (41f)
`which it outputs one sample period later to a subtracting
`input of the summer 416.
`In addition to receiving the
`delayed phase error signal 4): output by the delay element
`414,
`the summer 416, receives at a summing input,
`the
`current phase error signal 1), supplied to the input of the
`delay element 414. The summer 416 operates to subtract
`from the phase error 4:, associated with a current symbol, the
`phase error 1:: associated with the immediately preceding
`symbol. In this manner the summer 416 produces the desired
`frequency error signal.
`m discussed above, the phase error for inner symbols
`can't be reliably estimated in many cases, and particularly
`during acquisition mode where large phase errors tend to
`exist. For this reason. phase error estimates are not made for ‘
`inner symbols during acquisition mode operation. Thus. if
`consecutive outer symboLs, c.g., symbols other than the
`inner most symbols, are not received, it is not possible to
`reliably determine the frequency error between two symbols
`by subtracting the estimated phase error for each of the
`received symbols.
`The consecutive outer symbol detection circuit 404 is
`responsible for detecting the receipt of two consecutive
`outer symbols.
`i.e..
`the condition required for accurate
`frequency error estimates to be generated by the frequency
`error estimation circuit 412. As discussed above. the slicer
`module 106 implements a reduced constellation slicing
`algorithm during acquisition mode operation. This results in
`the output of the value (0.0) as the sliced symbol value ZSI
`whenever an inner symbol
`is received. Since the slicer
`module 106 outputs a known predictable value whenever an
`inner symbol is received, the value of the slicer module’s
`output may be examined to determine if an inner or outer
`symbol is being processed at any given time by the fre-
`quency error detection circuit 302.
`as illustrated,
`the consecutive outer symbol detection
`circuit 404 includes a first comparator 406 which is respon-
`sible for comparing the sliced symbol value Z“, to the known
`value,
`in this case (0.0),
`indicative of the receipt of a
`non-outer, e.g., inner symbol. When the value of the input
`signal 23,, fails to match that of the known value (0,0), it
`indicates that an outer symbol has been received and the
`output of the comparator 406 is asserted. However, when 2,;
`matches the value (0,0) it indicates that an inner symbol is
`being processed and that any frequency error estimate
`generated using that value is not reliable and should not be
`used.
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`The output of the comparator 406 is coupled to a unit
`delay element 408 which. in turn. has an output coupled to
`a first input ofan AND gate 410. Asecond input of the AND
`gate 410 is coupled directly to the output of the comparator
`404. Since the AND gate 410 receives as its inputs the
`current output of the comparator 406. and the previous
`output of the comparator 406. the output of the AND gate
`410 will only be high when the current symbol and the
`previous received symbol are outer symboLs. Thus,
`the
`output of the consecutive outer symbol detection circuit 404
`is a consecutive outer symbol detection signal which will be
`high when consecutive received symbols are outer symbols
`but low in other cases.
`
`The output ofthe frequency error estimation circuit 412 is
`coupled to the input to the ambiguity detector circuit 418.
`The ambiguity detection Circuit’s purpose is to detect when
`the estimated frequency error’s value is outside of a non-
`ambiguous range, e.g., a range where the direction in which
`to pull the carrier can be accurately determined. The maxi-
`mum frequency error that ean be accu