1
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`RS1039
`Rohde & Schwarz Gmbh & Co., KG vs. Tektronix, Inc.
`IPR2018-00643
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`

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`US. Patent
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`Mar. 9, 1999
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`5,880,973
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`US. Patent
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`Mar. 9, 1999
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`Sheet 3 0f9
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`5,880,973
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`206
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`SUBTRACTOR
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`A
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`STORAGE
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`302
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`US. Patent
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`Mar. 9, 1999
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`Sheet 4 0f9
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`5,880,973
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`202
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`400 /
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`208
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`US. Patent
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`Mar. 9, 1999
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`Sheet 5 0f 9
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`5,880,973
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`US. Patent
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`Mar. 9, 1999
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`Sheet 6 0f9
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`5,880,973
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`US. Patent
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`Mar. 9, 1999
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`Sheet 7 0f9
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`US. Patent
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`Mar. 9, 1999
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`Sheet 8 0f9
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`5,880,973
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`FIG.8 224
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`
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`FILTERRESET
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`9
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`US. Patent
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`Mar. 9, 1999
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`Sheet 9 0f9
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`5,880,973
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`900
`
`KJ
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`
`
`
` MONITOR
`OUTPUT SAMPLE
`
`0F FILTER
`
`
` PERFORM
`OVERFLOW
`
`DETECTION
`
`
`
`
` IS
`THERE AN
`
`OVERFLOW
`
`
`
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`RESET FILTER
`
`FIG.9
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`10
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`10
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`

`1
`SIGNAL PROCESSING SYSTEM AND
`METHOD FOR ENHANCED CASCADED
`INTEGRATOR-COMB INTERPOLATION
`FILTER STABILIZATION
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`The invention relates to signal processors. More
`particularly, the invention relates to signal processing sys-
`tems and methods with cascaded integrator-comb interpo-
`lation filters.
`
`2. Description of Related Art
`Significant advancements in digital signal processing are
`due largely to advancements in integrated-circuit fabrication
`and digital computer technology. That is, the rapid devel-
`opments in integrated-circuit technology, particularly very-
`large-scale integration (VLSI) of electronic circuits, have
`lead to the development of powerful and inexpensive digital
`computers and special-purpose digital hardware. These
`inexpensive and relatively fast digital systems are capable of
`performing complex digital signal processing techniques,
`which are usually too difficult and/or too expensive to be
`performed by analog circuitry or analog signal processing
`systems.
`As such, digital signal processing is now commonly
`employed in a wide variety of applications including com-
`munication systems (e.g., cellular, wireless, and radar
`systems), image processing, and speech processing.
`Sample rate conversion techniques (or processes) are
`typically performed by digital processing systems.
`In
`general, such techniques digitally convert the sample rate of
`a signal to a different rate. When the converted sample rate
`is lower than the original sampling rate, the process is called
`decimation. When the converted sample rate is higher, the
`process is called interpolation. In effect, decimation reduces
`the number of samples, whereas interpolation creates addi-
`tional samples of an original signal from a reduced set of
`samples.
`Interpolation is required in systems such as digital trans-
`mitters where the signal to be transmitted, at a given carrier
`frequency, must be sampled at a rate which is at least twice
`the frequency of a carrier signal. For example, speech—
`which is typically sampled at 8,000 samples per second (8
`KHz)—must be interpolated up to a sample rate of 50
`million samples per second (50 MHZ) before it can be
`modulated to carrier frequencies up to 25 million cycles per
`second (25 MHZ).
`Conventionally, signal processors have utilized a wide
`variety of interpolation filters to achieve this end. An effi-
`cient interpolation filter for this purpose was described in an
`article by Eugene B. Hogenhauer, “An Economical Class of
`Digital Filters for Decimation and Interpolation,” IEEE
`Transactions on Acoustics, Speech and Signal Processing,
`Vol. ASSP 29, No. 2, April 1981. The filter disclosed in the
`Hogenhauer article is called a cascaded integrator-comb
`(CIC) interpolation filter. The CIC interpolator filter repre-
`sented a significant advancement in the art and has since
`become the filter of choice for many applications.
`CIC interpolation filters are constructed as a series of “N”
`comb filter circuits (subtractors), followed by a zero pad
`circuit, followed by a series of “N” integrator circuits
`(adders). The comb section of the filter operates at a low
`sample rate, whereas the integrator section of the filter
`operates at a high sampling rate. Typically, the interpolation
`factor (R) is set between 2 and 10,000. The number of stages
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`(N) is selected according to the desired level of accuracy.
`The lowest practical number of stages commonly employed
`today is 3 (lowest accuracy) and the highest is 5 (highest
`accuracy). Typical filters have 4 stages.
`In operation, each comb circuit outputs the difference
`between its current
`input sample and its previous input
`sample. The zero pad circuit outputs the current
`input
`sample followed by “R—1” zero samples. Each integrator
`circuit outputs the sum of its current input sample with its
`previous output sample. The output of the last integrator
`stage is the interpolated output of the CIC interpolation filter.
`Implementing a CIC interpolation filter generally
`involves the following three requirements: 1) the filter must
`be reset before use; 2) addition and subtractions must be
`performed using modulo arithmetic; and 3) the word size in
`the subtracters, adders, and storage elements must be large
`enough to accommodate the arithmetic gain of the filter. The
`first requirement is typically satisfied by clearing all storage
`elements before use. The second requirement is satisfied by
`using sign-2’s-complement arithmetic. With respect to the
`third requirement, the Hogenhauer article disclosed that the
`requirement
`is satisfied if the last
`integrator stage can
`accommodate at least a sample (word) size of Bout bits,
`where Bom=(Bl-n+log2R(N'1)), Bin is the number of bits per
`input sample, and R is the interpolation factor. In other
`words, the output of the last integrator stage (and thus the
`fil(ter))must be able to accommodate an amplitude gain of
`R N'1 .
`There are many significant advantages of CIC interpola-
`tion filters including that: no multipliers are required (i.e.,
`processing is done with simple subtraction and addition
`functions); no storage is required for filter coefficients or
`large blocks of input samples; the structure of the filter is
`very “regular,” primarily consisting of two basic building
`blocks (comb filters and integrators); little external control
`or complicated local timing is required; and the same filter
`design can easily be used for a wide range of applications.
`For example, CIC interpolation filters require only “N”
`comb filters, “N” integrators, and “2N” storage elements to
`interpolate by very large amounts. This contrasts with other
`interpolation systems and methods that generally require at
`least
`log2R multipliers and adders. See Crochier et al.,
`“Interpolation and Decimation of Digital Signals-A Tutorial
`Review,” Proceedings of the IEEE, Vol. 69, No. 3, March
`1981.
`
`When properly designed and initialized, CIC interpolation
`filters are considerably stable and can process, without error,
`for extended periods of time. That is, the combination of the
`comb filters and the integrator allow the CIC interpolation
`filter to continuously operate in its intended manner.
`Conventional CIC interpolation filters, however, have
`sustained disadvantages. That is, a change in filter param-
`eters (e.g., the interpolation factor “R”)or the interjection of
`circuit noise causes unbounded growth, thereby rendering
`the CIC interpolation filter unstable. In general, there is a
`processing balance between the comb and integrator sec-
`tions of the filter, such that processed output samples of the
`filter remain within predetermined amplitude thresholds or
`limits. In other words, input samples are preconditioned by
`the comb section so that amplitude overflows do not occur
`in the integrator sections. When the parameters are changed
`or noise is interjected, variances (or errors) in samples being
`processed occur. These variances,
`in turn, are further
`acerbated, typically without bound, by the integrators.
`Once a conventional CIC interpolation filter becomes
`unstable it must be manually reset. As a practical matter,
`
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`5,880,973
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`3
`instability caused by the changing of filter parameters is not
`a significant problem because the change is initiated by the
`application (or user); the application “knows” that the filter
`becomes unstable at the time of such change. Accordingly,
`a properly designed application will merely reset the filter
`after it changes the parameters.
`Circuit noise, however, is random, caused for example by
`fluctuations in electrical power sources, atmospheric distur-
`bances (such as lightening, physical shock, high energy
`radiation particles), or other unpredictable events. Since
`these events are infrequent and hard to detect, an application
`is typically designed to wait until a complete system failure
`occurs, determine if the failure is due to a CIC interpolation
`filter instability, and only then reset the filter. For example,
`in a wireless communication application this type of
`instability, albeit infrequent, is catastrophic in that the chan-
`nel is completely lost requiring the user to initiate another
`connection. Indeed, the instability problem may cause such
`bandwidth growth that would affect other channels in the
`cellular system.
`Another example, where the instability of conventional
`CIC interpolation filters is a major problem which prevents
`their use, is in satellites where high energy radiation par-
`ticles are common. Furthermore,
`in such a space- and
`energy-constrained application, the provision of any addi-
`tional circuitry that might otherwise be required to monitor
`for instability would be costly and undesirable.
`SUMMARY OF THE INVENTION
`
`The invention meets the above needs, and overcomes the
`disadvantages and drawbacks of conventional CIC interpo-
`lation filters. The invention teaches a system and method of
`automatically detecting instabilities and resetting a CIC
`interpolation filter when instabilities are detected.
`The invention detects instabilities in the CIC interpolation
`filter by continuously monitoring the output samples of the
`filter. Under normal conditions, the output sample of the last
`stage of the filter should never exceed a predetermined
`threshold governed by A(R(N'1)), where A is the amplitude
`(magnitude) of the input sample. As such, only (Bl-n+log2R
`(N'1)) bits of precision are necessary for the final integrator
`circuit in a CIC interpolation filter. In an unstable condition,
`output samples exceed this predetermined threshold.
`The invention exploits this instability characteristic of
`CIC interpolation filters. That is, the invention monitors and
`detects output samples with amplitudes that exceed A(R(N'
`1)) (and correspondingly, require more than (Bin+log2R(N'1))
`bits to represent). Those samples which have such ampli-
`tudes are called overflow samples. Once the presence of an
`overflow sample is detected,
`the invention automatically
`resets the CIC interpolation filter.
`One prominent advantage of the invention is that insta-
`bility detection is achieved quickly, since each output
`sample of the CIC interpolation filter is checked. Thus,
`erroneous data is not propagated throughout the overall
`system for an unnecessarily protracted period of time.
`Correspondingly, another significant advantage of the
`invention is that it provides automatic and ensured recovery
`by resetting the CIC interpolation filter upon the detection of
`filter instability.
`A further advantage is that embodiments of the invention
`are very cost effective to implement. For example, one
`integrated circuit embodiment of the invention requires less
`than twenty CMOS gates. Moreover, the invention is likely
`to realize reductions in overall system design and operating
`costs. For example, in cellular systems where large numbers
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`of signals are being transmitted, this cost effective solution
`to the CIC filter instability problem will decrease the overall
`cost of cellular equipment.
`An additional advantage of the invention is that it can be
`readily implemented and integrated into a wide variety of
`existing CIC interpolation filter designs.
`The foregoing, and other features and advantages of the
`invention, will be apparent from the following, more par-
`ticular description of the preferred embodiments of the
`invention, the accompanying drawings, and the appended
`claims.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a high level block diagram of a signal processor
`(or digital
`transmit circuit) 100 in accordance with the
`principles of the invention;
`FIG. 2 is a detailed block diagram of a cascaded
`integrator-comb (CIC) interpolation filter 104 in accordance
`with the principles of the invention;
`FIG. 3 is a detailed block diagram of a comb filter 200;
`FIG. 4 is a detailed block diagram of a zero pad circuit
`202;
`FIG. 5 is a detailed block diagram of an integrator circuit
`204;
`FIG. 6 is a detailed block diagram of an overflow detect
`circuit 216;
`FIG. 7 is a detailed block diagram of an overflow detect
`circuit 700;
`FIG. 8 is a detailed block diagram of a reset hold circuit
`220; and
`FIG. 9 is a flow diagram of a method 900 for detecting
`filter instabilities and automatically resetting a CIC interpo-
`lation filter in accordance with the principles of the inven-
`tion.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`The preferred embodiments of the invention are now
`described with reference to the figures where like reference
`numbers indicate like elements. Also in the figures, the left
`most digit of each reference number corresponds to the
`figure in which the reference number is first used.
`FIG. 1 is a high level block diagram of a signal processor
`100 (alternatively referred to as digital transmit circuit 100)
`in accordance with the principles of the invention. More
`particularly, FIG. 1 illustrates one of the four transmit
`circuits that is to be contained in a GRAYCHIPTMGC4114
`
`Quad Transmit chip, which is specifically designed for use
`in
`cellular
`communication systems. The
`GRAYCHIPTMGC4114 Quad Transmit chip is the first ver-
`sion of this product
`to include an embodiment of the
`invention and will be commercially available from GRAY-
`CHIP Inc., 2185 Park Boulevard, Palo Alto, Calif. 94306,
`the assignee of this patent application.
`In general, digital transmit circuit 100 can be utilized in
`a number of communication applications. For example,
`digital transmit circuit 100 can be used with cellular radios
`to modulate a narrowband voice signal and up-convert the
`signal to a desired center carrier frequency. When multiple
`digital transmit circuits 100 are used to modulate multiple
`voice signals, each digital transmit circuit 100 up-converts
`its signal to a unique center carrier frequency. The output of
`each digital transmit circuit 100 is then added together to
`produce a wideband signal. Correspondingly, the wideband
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`signal includes all the constitute voice channels, each at a
`different frequency. In such cellular applications, the wide-
`band signal is then converted from digital samples to analog
`voltages and up-converted to a 800 MHZ cellular frequency
`band.
`
`As illustrated in FIG. 1, digital transmit circuit 100 is
`partitioned into two identical segments 136, 138, which
`respectively process the complex sample components (real
`(Q) and imaginary (I)) of a signal. Each channel includes a
`transmission (interpolate by four) filter 102, a cascaded
`integrator-comb (CIC) interpolation filter 104, and a mixer
`106. Transmission filter 102, CIC interpolation filter 104,
`and mixer 106 receive and send samples over data buses
`112, 114, and 116, respectively, as illustrated in FIG. 1.
`Digital
`transmit circuit 100 also includes a numerically
`controlled oscillator (NCO) 108 and an output combiner
`(summer) 110. NCO 108 is programmed by the communi-
`cation system over a frequency data bus 126.
`In this preferred embodiment, digital transmit circuit 100
`receives (over data bus 112) input samples from a commu-
`nication system (not shown). The communication system, in
`one embodiment, may be a US. cellular base station which
`uses the Advanced Mobile Phone Systems (AMPS) com-
`munication standard. As such, the input samples have been
`modulated, via Frequency Modulation (FM), and are pre-
`sented to digital transmit circuit 100 at an input sample rate
`of 31,250 samples per second (31.25 KHZ). The input rate is
`a design criteria and thus will vary significantly among
`different applications. For example, when utilized with
`cellular systems that use Differential Phase Shift Keying
`(DPSK) or Quadrature Phase Shift Keying (QPSK)
`modulation, the input sample rate would be approximately
`200 KHZ.
`
`The overall function of digital transmit circuit 100 is to
`increase the input sample rate (associated with the samples
`on bus 112) to a higher rate that is at least twice the desired
`center carrier frequency of the up-converted signal. As
`illustrated in FIG. 1, the higher sample rate (associated with
`the samples on bus 116), in this embodiment, is 50 MHZ,
`thus allowing center carrier frequencies of up to 25 MHZ. To
`achieve this end, digital transmit circuit 100 interpolates the
`31.25 KHZ input samples, by a factor of 1600, in order to
`create the 50 MHZ sampled version of the signal.
`Transmission filter 102 first interpolates the input samples
`(31.5 MHZ samples on bus 112) by a factor of 4, as well as
`shapes the spectral response. In general, implementation of
`transmission filter 102 is well known in the art. For example,
`a conventional finite impulse response (FIR) filter, with one
`or two stages, can be used. With respect to a QPSK-based
`cellular system, transmission filter 102 can be implemented
`as a conventional root-raised cosine (RRC) pulse shaping
`filter. In this embodiment, however, transmission filter 102
`is a low-pass filter with a 30 KHZ cut-off frequency. Trans-
`mission filter 102 also has two stages (not shown). In a
`presently preferred embodiment, the first stage is a sixty-
`three tap, interpolate by two, filter followed by the second
`stage that
`is a thirty-one tap,
`interpolate by two, filter.
`Additionally, the first stage filter is programmable to allow
`for the selection of filter shapes (e.g., low-pass or RRC).
`Other arrangements of filter 102 may be employed without
`departing from the spirit or scope of the present invention,
`however.
`
`Once input samples have been interpolated by a factor of
`four, CIC interpolation filter 104 interpolates the samples
`(125 KHZ samples on bus 114) by an additional factor of
`400, thereby achieving the desired sampling gain of 1600
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`(i.e., equal to 4*400). Accordingly, CIC interpolation filter
`104 outputs samples at 50 MHZ onto bus 116. These samples
`(at 50 MHZ) are then sent to mixer 106 and multiplied by a
`sine output 132 (or a cosine output 134) of NCO 108 to
`up-convert
`to the desired center carrier frequency. The
`resulting samples (on bus 128) of each channel are sent to
`output combiner 110 that sends the processed output
`samples to the communication system to transmission.
`As illustrated in FIG. 1, CIC interpolation filter 104
`receives a system reset signal 118, a clock signal 122, a
`R><clock signal 124, and interpolation factor data (R) (over
`bus 120) from the communication system. System reset
`signal 118 is controlled by the communication system to
`force a reset condition, such as after the changing of the
`interpolation factor “R”. In this embodiment, clock 122 is a
`125 KHZ free running clock. The frequency of clock 122
`corresponds with the rate of the samples on bus 114.
`R><clock 124 is also a free running clock that operates at a
`frequency “R” times greater than that of clock 122 (50
`MHZ), which corresponds with the rate of the samples on
`bus 116.
`
`FIG. 2 illustrates a detailed block diagram of CIC inter-
`polation filter 104 in accordance with the principles of the
`invention. CIC interpolation filter 104 includes “N” number
`of comb filters 200, a zero pad circuit 202, and “N” number
`of integrator circuits 204. There are an equal number (N) of
`stages, each stage having one comb filter 200 and one
`integrator circuits 204.
`In general,
`the lowest practical
`number of stages is 3 (lowest accuracy) and the highest is 5
`(highest accuracy). In this embodiment N=4. Comb filters
`200, zero pad circuit 202, and integrator circuits 204 are
`generally implemented in accordance with the article by
`Eugene B. Hogenhauer, “An Economical Class of Digital
`Filters for Decimation and Interpolation,” IEEE Transac-
`tions on Acoustics, Speech and Signal Processing, Vol.
`ASSP 29, No. 2, April 1981, the disclosure of which is
`herein by incorporated reference. Since CIC interpolation
`filters are well known in the art, only those details that are
`necessary to understand the features and advantages of the
`invention are discussed.
`
`Unlike conventional CIC interpolation filters, however,
`CIC interpolation filter 104 also includes an overflow detec-
`tion circuit 216, an automatic reset circuit 218, and a reset
`hold circuit 220 in accordance with the invention. As such,
`CIC interpolation filter 104 is automatically reset once an
`overflow condition is detected, thereby providing prompt
`and ensured filter recovery.
`In operation, samples (125 MHZ) are sent (over bus 114)
`to comb (1) filter 200 for processing. The output samples of
`comb (1) filter 200 are sent (over bus 206) to comb (2) filter
`200 for further processing. Similarly,
`the output of each
`successive comb filter 200 is sent to the next, with comb (N)
`filter 200 sending (over data bus 206) its processed samples
`to zero pad circuit 202.
`A detailed block diagram of comb filter 200 is illustrated
`in FIG. 3. Comb filter 200 includes a resettable storage
`element 300 and a subtractor circuit 302. In this embodiment
`
`storage element 300 is a single word register. In operation,
`for each cycle of clock 122, storage element 300 stores the
`current sample presented on its input data bus 114/206.
`Concurrently, subtractor circuit 300 subtracts the output of
`storage element 300 (which is the value of the previous
`sample) from the current sample. In general, the sample
`(word) size for storage element 300 and subtractor 302 must
`be at least (Bl-n+log2N) bits, where Bin is the number of bits
`per sample into a CIC interpolation filter.
`In this
`
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`5,880,973
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`7
`embodiment, since Bin=16 and N=4 these element must have
`at least 18 bits.
`
`In addition, storage element 300 is cleared with the
`assertion of CIC-reset 214. An alternate preferred embodi-
`ment of comb filter 200 has a storage element without an
`individual reset feature. In such an embodiment, storage
`element of comb filter 200 is cleared by “flushing” the CIC
`interpolation filter. That is, data bus 114 is cleared (set to
`value of zero) and CIC-reset 214 is held asserted for enough
`clock cycles to allow zero data to propagate throughout the
`comb storage elements.
`FIG. 4 illustrates a detailed block diagram of zero pad
`circuit 202. Zero pad circuit 202 includes a 2:1 multiplexer
`400 and a binary counter 402. In operation, multiplexer 400
`passes onto bus 208 either the samples (on bus 206) or a zero
`value 404. Multiplexer 400 is controlled by counter 402
`which generates a multiplexer control signal 406. Counter
`402 is clocked by R><clock 124 and programmed (over bus
`120) with the interpolation factor (R). For every “R” cycles
`of R><clock 124, counter 402 asserts multiplexer control
`signal 406 to select the sample on bus 206 for one cycle. For
`the remaining “R—1” cycles, counter 402 asserts control
`signal 406 to select zero value 404. As would be apparent to
`one skilled in the art, multiplexer 400 can alternately be
`implemented with an “AND” gate circuit to set bus 206 to
`a zero value for each “R—1” cycles.
`The output samples of zero pad circuit 202 are sent (over
`bus 208) to integrator (1) 204 for further processing. The
`output samples of integrator (1) 204 are passed (over bus
`210) to integrator (2) 204. Similarly, the output samples of
`each successive integrator circuit 204 are sent to the next for
`further processing, with integrator (N) 204 sending its
`output samples (50 MHZ) onto bus 116.
`FIG. 5 illustrates a detailed block diagram of integrator
`circuit 204.
`Integrator circuit 204 includes a resettable
`storage element 500 and an adder circuit 502.
`In this
`embodiment, storage element 500 is a single word register.
`In operation, for each cycle of R><clock 124, storage element
`500 stores the current sample presented on data bus 206.
`Concurrently, adder circuit 502 adds the output (on bus 504)
`of storage element 500 (which is the value of the previous
`output sample of adder 500) to the current sample.
`CIC-reset 214 causes storage element 500 to clear its
`contents and set its output to zero. An alternate embodiment
`of integrator circuit 204 has a clear circuit (on either bus 504
`or bus 506) between storage 500 and adder 502 to clear
`storage element 500.
`Conventionally the sample (word) size for each storage
`element 500 and adder circuit 502 must be at least (Bl-”4'
`log2R(N'1)) bits. However, this embodiment, in accordance
`with the invention, has at least (1+Bm+log2R(N'1)) bits to
`allow for overflow detection. As such, this embodiment uses
`a sample size of 59 (i.e., 1+16+log2400(4'1)) bits in integra-
`tor (N) 204.
`This additional bit is utilized by overflow circuit 216 to
`detect filter instability. In operation, overflow circuit 216
`monitors the samples sent on bus 116 by integrator (N) 204
`and checks an overflow condition. If an overflow condition
`
`is detected, overflow circuit 216 asserts an auto-reset signal
`222.
`
`FIG. 6 illustrates a detailed block diagram of overflow
`circuit 216. Since this embodiment utilizes sign-2’s-
`complement arithmetic, overflow circuit 216 is a simple
`exclusive-OR (XOR) gate 600. The inputs to XOR gate 600
`are the two most significant bits (MSBs) of bus 116, MSB
`602 (bit 58 in this embodiment) and MSB-1 604 (bit 57 in
`
`10
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`15
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`20
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`25
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`30
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`35
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`40
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`45
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`50
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`55
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`60
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`65
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`8
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`this embodiment). MSB-1 604 is the 2’s-complement sign
`bit and MSB 602 is an “extra” 2’s-complement sign bit. The
`remaining bits of bus 116 (MSB-2 to LSB; or bits 56-0 in
`this embodiment) are used for sample data.
`An overflow condition is detected by monitoring both
`MSB 602 and MSB-1 604. Under normal conditions, both
`bits have the same value (i.e., “00” or “11”). When CIC
`interpolation filter 104 is unstable, overflow conditions
`occur and these bits do not have the same values (i.e., “01”
`or “10”). Accordingly, exclusive-OR gate 600 asserts autore-
`set signal 222 when an overflow is detected, thereby auto-
`matically and promptly recovering CIC interpolation filter
`104 without requiring system level intervention.
`While FIG. 6 illustrates the overflow circuit for this
`
`embodiment of the invention, other implementations would
`be apparent to one skilled in the art. For example, FIG. 7
`illustrates an alternate embodiment of an overflow circuit
`
`700 which is included in a CIC interpolation filter similar to
`CIC interpolation filter 104 illustrated in FIG. 2. In this
`embodiment, overflow circuit 700 includes a storage ele-
`ment 702 and a comparator circuit 704. Storage element 702
`is a single word register having a word width of approxi-
`mately (Bin+log2R(N'1)) bits.
`In operation, the output sample on bus 712 (similar to bus
`116) is compared with output 706 of storage register 702.
`Although all the bits of the output sample are compared in
`this embodiment, it would be apparent to one skilled in the
`art that only a predetermined number of MSBs are required,
`in many applications, to make the comparison. When the
`output sample exceeds output 706 of storage register 702,
`comparator circuit 704 asserts auto-reset signal 710 (similar
`to auto-reset 222) to indicate an overflow condition and thus
`filter instability. The communication system in this embodi-
`ment initializes storage register 702, over data bus 708, with
`a predetermined threshold governed by A(R(N'1)), where A
`is the maximum amplitude (magnitude) of the input samples
`to CIC interpolation filter 104.
`Returning now to the embodiment illustrated in FIG. 2,
`auto-reset signal 222 is combined with system reset 118 at
`reset circuit 218 (which is a simple OR gate in this
`embodiment). As previously discussed, system reset 118
`allows the communication system force a reset condition
`and recover the filter after a change in filter parameters (e.g.,
`interpolation factor “R”). Auto-reset signal 222, in contrast,
`is generated “automatically” within CIC interpolation filter
`104 to recover from instabilities cause by random noise.
`When either, or both, of these reset signals are asserted, reset
`circuit 218 asserts a filter reset signal 224. Alternatively, CIC
`interpolation filter 104 can be implemented without reset
`circuit 218. That is, since overflow circuit 216 automatically
`detects all filter instabilities (caused by random noise as well
`as changes in filter parameters), having a system reset
`capability (via system reset 118) may not be required in
`some applications. In such instances, auto-reset signal 222 is
`input directly into reset hold circuit 220.
`In this embodiment, reset hold circuit 220, in response to
`filter reset signal 224, asserts CIC-reset 214 for a predeter-
`mined number of clock cycles to guarantee that CIC inter-
`polation filter 104 is fully reset. However, as would be
`apparent to one skilled in the art, utilization of a reset hold
`circuit is not necessary in those implementations in which
`the CIC interpolation filter is fully reset in approximately
`one cycle of R><clock 124.
`FIG. 8 illustrates a detailed block diagram of reset hold
`circuit 220 in accordance with this embodiment. Reset hold
`circuit 220 includes a down counter 800 that is hardwired for
`
`14
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`14
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`5,880,973
`
`9
`a predetermined count. When filter reset signal 224 is
`asserted, down counter 800 is enabled and CIC-reset 214 is
`asserted. Down counter 800 maintains CIC-reset 214 in its
`asserted state while it counts down toward zero. Once the
`zero count is reached, down counter 800 releases CIC-reset
`214 and reloads the predetermined count. Down counter
`800, however, can be programmable, rather than hardwired,
`to allow the communication system set the count value.
`As would be appreciated by one skilled in the art, all these
`advantages of the invention can be realized at an insignifi-
`cant cost since the various embodiments of the invention can
`
`be readily implemented with very simple combinational
`logic. Indeed, several embodiments of the invention would
`require less than 20—30 CMOS gates to implement
`the
`overflow and reset circuits.
`Method and Process
`
`FIG. 9 is a flow diagram illustrating a method 900 of
`detecting instabilities and resetting a CIC interpolation filter
`in accordance with the principles of the invention. During
`step 902, the output of the CIC interpolation filter is moni-
`tored for a next output sample.
`In step 902, overflow
`detection is performed. As discussed above, there are several
`techniques of performing overflow detection.
`In this
`embodiment, step 902 compares the value of the output
`sample with a predetermined maximum threshold value.
`In step 904, if no overflow condition is detected,
`the
`method returns to step 902 and waits for the next output
`sample. If, however, an overflow condition is detected, the
`CIC interpolation filter is reset in step 908. After resetting
`the filter, the method returns to step 902 and waits for the
`next output sample.
`Additional Embodiments
`
`In another embodiment of CIC interpolation filter 104,
`storage elements are added between or within comb circuits
`200, or zero pad circuit 202, or integrator circuits 204. These
`additional storage elements may be added if they are nec-
`essary to decrease the timing delays between these circuits.
`If these storage elements are added, they must either have
`reset capabilities built-in, or the auto-reset signal 222 must
`be held active by reset hold circuit 220 for en