1
`
`RS1038
`Rohde & Schwarz Gmbh & Co., KG vs. Tektronix, Inc.
`IPR2018-00643
`
`

`

`US 6,487,573 B1
`Page 2
`
`OTHER PUBLICATIONS
`
`William R. Bevan, “A Simplified Equalization Analyzer,”
`Journal oftheAudio Engineering Society, vol. 26, No. 3, pp.
`120—129, Mar. 1978.
`Ronald E. Crochiere and Lawrence R. Rabiner, “Interpola-
`tion and Decimation of Digital Signals—A Tutorial
`Review,” Proc. IEEE, vol. 69, No. 3, pp. 300—331, Mar.
`1981.
`
`Robert Adams and Tom Kwan, “A Stereo Asynchronous
`Digital Sample—Rate Converter for Digital Audio,” IEEE
`Journal ofSolid—State Circuits, vol. 29, No. 4, pp. 481—488,
`Apr. 1994.
`
`Sangil Park, Garth Hillman and Roman Robles, “A Novel
`Structure for Real—Time Digital Sample—Rate Converters
`with Finite Precision Error Analysis,” IEEE, pp. 3613—3616,
`1991.
`
`Tor A. Ramstad, “Digital Methods for Conversion Between
`Arbitrary Sampling Frequencies,” IEEE Transactions on
`Acoustics, Speech, and Signal Processing, vol. ASSP—32,
`No. 3, pp. 577—591, Jun. 1994.
`S. Cucchi, et al., “DSP Implementation of Arbitrary Sam-
`pling Frequency Conversion for High Quality Sound Appli-
`cation,” IEEE, pp. 3609—3612, 1991.
`
`* cited by examiner
`
`2
`
`

`

`US. Patent
`
`Nov. 26, 2002
`
`Sheet 1 0f3
`
`US 6,487,573 B1
`
`RELJn
`
`12
`
`14
`
`16
`
`x
`
`10
`
`
`
`—50
`
`—100
`
`MAGNITUDE
`(dB)
`
`— 1 so
`
`-200
`
`————-——-—4-——-——--——l-——-——-————l—-———-—————-L——-————
`
`
`0.5
`
`1
`
`1.5
`
`2
`
`FREQUENCY (HZ)
`
`2.5
`
`X106
`
`3
`
`

`

`US. Patent
`
`Nov. 26, 2002
`
`Sheet 2 0f3
`
`US 6,487,573 B1
`
`42
`\ so
`
`44
`\ 60
`H2,1(z)
`
`. 54
`
`.
`
`46
`\ 70
`H3.1(z)
`
`.
`
`40
`/
`
`l'_s_in
`x(n)
`
`(64 Tops)
`
`52
`
`2
`
`FS'I"
`
`x10‘)
`
`FIG. 4
`
`(9 Tops)
`H2,2(z)
`64
`52
`H23 2
`
`8
`H2,16(z)
`
`66
`
`(3 Tops)
`- 78
`H3,2(z)
`. 58
`74
`'
`72
`‘
`32F3_;n - 32R3Fs_in
`H3.3(2)
`q(”I
`SRC Ratio = (32R3)/S
`
`.
`
`°
`
`48
`IS
`
`FS—Out
`Kn)
`
`.
`
`76
`
`H3.R3(z)
`
`0
`
`DETERMINE WHICH STAGE 3
`OUTPUT SAMPLE WILL BE THE
`CURRENT SRC OUTPUT SAMPLE
`
`DETERMINE AND RETRIEVE FROM
`STORAGE STAGE 2 F[LTER
`COEFICIENTS NEEDED TO FORM
`NEEDED STAGE 2 OUTPUT SAMPLES
`
`DETERMINE WHICH STAGE 2
`
`OUTPUT SAMPLES WILL BE USED
`TO FORM STAGE 3 OUTPUT SAMPLE
`
`DETERMINE AND
`
`DETERMINE INPUT SAMPLES NEEDED
`TO FORM NEEDED
`STAGE 1 OUTPUT SAMPLES
`
`
`
`COMPUTE COEFFICIENTS OF STAGE
`3 FILTERS TO BE APPLIED
`T0 STAGE 2 OUTPUT SAMPLES
`TO FORM STAGE 3 OUTPUT SAMPLE
`
`DETERMINE AND RETRIEVE FROM
`STORAGE STAGE 1 FILTER
`COEFICIENTS NEEDED TO FORM
`NEEDED STAGE 1 OUTPUT SAMPLES
`
`DETERMINE STAGE 1 OUTPUT
`SAMPLES NEEDED To FORM
`NEEDED STAGE 2 OUTPUT SAMPLES
`
`PERFORM NECESSARY FILTERING
`OPERATIONS FOR STAGES 1
`2 THEN 3
`
`'
`
`OUTPUT SAMPLE
`
`FIC . 5
`
`4
`
`

`

`US. Patent
`
`Nov. 26, 2002
`
`Sheet 3 0f3
`
`US 6,487,573 B1
`
`142
`
`144
`
`146
`
`147 *32Fs_in
`
`F
`
`_
`5-°”t
`1__47Fs
`
`$48160
`
`X(n)
`
`/
`140
`
`160*32Fs_ 1n
`
`FIG. 6
`
`142
`Fsin—> /
`
`2Fs in‘>
`
`144
`7/
`
`145
`32Fs_in_’ / 1‘4J'7"'~-52Fs_in_"
`
`Fs_oul =
`
`147Fs_in
`W —»
`
`148
`
`71")
`
`.
`
`
`
`
`160*32Fs_;n
`
`/
`140
`
`154
`
`156
`
`[710.8
`
`147 417147 147
`
`TIME'
`
`n
`
`5
`
`

`

`US 6,487,573 B1
`
`1
`MULTI-RATE DIGITAL FILTER FOR AUDIO
`SAMPLE-RATE CONVERSION
`
`TECHNICAL FIELD OF THE INVENTION
`
`This invention relates to audio sample-rate conversion
`systems, and more particularly relates to multistage sample-
`rate conversion filters.
`
`BACKGROUND OF THE INVENTION
`
`there have
`For both historical and technical reasons,
`existed a number of industrial standards on audio digital
`signal sample rates. The well known examples are the 44.1
`kHz sample rate for consumer CD players and 48 kHz for
`professional digital audio. This, in turn, has given rise to
`sample-rate conversion (“SRC”) systems for converting a
`stream of digital data at one sample rate to a stream of digital
`data at a different sample rate. However, the cost of existing
`SRC systems is high. This imposes a severe constraint in
`designing more affordable digital audio products that apply
`to various source signals.
`Early implementations of SRC systems were done in a
`hybrid digital/analog domain. They were relatively simple,
`since all that is needed is a digital-to-analog (D/A) converter
`followed by an analog-to-digital (A/D) converter. The D/A
`converter runs at
`the input sample rate while the A/D
`converter is controlled by the output sample rate. If the
`output sample rate is lower, an analog anti-aliasing filter is
`provided between them. These three components are expen-
`sive and consume a large amount of power, if designed for
`minimum signal degradation.
`Performing sample-rate conversion (SRC) in the digital
`domain has been a research/development topic for more than
`a decade. The article by R. E. Crochiere and L. R. Rabiner,
`“Interpolation and decimation of digital signals-A tutorial
`review,” Proc. IEEE, vol. 69, pp. 300—331, March 1981, is
`an excellent reference for understanding fundamental
`insights from early research results in this art area. Real-
`time, all-digital SRC systems are becoming more and more
`significant because digital processing of signals, such as
`voice, audio and video, appears to be increasingly dominant
`over traditional analog methods thanks to higher signal
`quality, rich features and the continually lowering cost of
`digital signal processing.
`FIG. 1 shows a typical, all-digital SRC system 10 con-
`sisting of three basic building blocks: an interpolator
`(expander) 12, a high quality lowpass digital filter 14, and a
`decimator 16. The expander 12 takes an input stream of
`samples at one frequency, for example F ii”, and digitally
`produces a stream of digital samples at a higher rate that is
`an integer multiple, designated R in this example, of the
`input rate. Thus, the output of expander 12 is a stream of
`digital samples at a rate of Fsiom=R FLm The decimator
`does the reverse. Thus,
`the decimator 16 takes an input
`stream of samples at one frequency, for example X=R FLL—n,
`and digitally produces a stream of digital samples at a lower
`rate, divided by an integer division factor, designated S in
`this example, of the input
`rate. This is referred to as
`decimation, or, alternatively, downsampling. Thus, the out-
`put of decimator 16 is a stream of digital samples at a rate
`of X/S=F570m=(R/S)FLW[.
`The reason for performing expansion followed by deci-
`mation is that the input sample rate and the output sample
`rate may not be a simple integer multiple of one another. The
`ratio of the interpolation factor R over the decimation factor
`S is the SRC ratio R/S where both R and S are positive
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`integers. For R>S the SRC system is said to be operated in
`an SRC-UP mode, whereas an SRC-DOWN mode means
`R<S.
`
`R and S may be chosen to have large values in order to
`achieve higher quality SRC. However, when the values of R
`and S are high, very-high order digital filters, usually finite
`impulse response (“FIR”) digital filters, are necessary. Thus,
`as S and R increase, a greatly increasing amount of coeffi-
`cient memory is required. For example, at a sample rate of
`48 kHz an equi-ripple prototype FIR filter with transition
`bandwidth of Af=4 kHz, passband ripples=10'3 and stop-
`band errors=10'5, has an order of approximately 128. The
`order of lowpass filter 14 in FIG. 1 is 128R for an interpo-
`lation filter (R is the interpolation factor up to over 1000).
`It
`is actually quite difficult or even impossible as a
`practical matter to design an equi-ripple FIR filter with tens
`of thousands of orders. In fact, the major difficulty encoun-
`tered in existing audio SRC system, implemented either in
`an application-specific integrated circuit (ASIC) or on a
`programmable digital signal processor (DSP) such as a
`Texas Instruments TMS320 scrics DSP chip, seems to be
`large memory size and high computational complexity. For
`example, an ASIC described in an article by R. Adams and
`T. Kwan, “A stereo asynchronous digital sample-rate con-
`verter for digital audio,” IEEE J. Solid-State Circuits, vol.
`29, pp. 481—488, April 1994, needs tens of kilobytes of
`memory to store just a fraction of the nearly 10 million filter
`coefficients used.
`
`Moreover, filter coefficient interpolation, which is per-
`formed to generate thousands of sets of required polyphase
`filter coefficients in real time, expends significant computa-
`tional power which is provided by a hardware multiplier
`plus an accumulator. A similarly difficult situation is also
`encountered when a programmable DSP chip is employed.
`For example, see the article by S. Park et al., “A novel
`structure for real-time digital sample-rate converters with
`finite precision error analysis,” Proc. Int. Conf. on Acoust,
`Speech and Signal Processing, pp. 3613—3616, Toronto,
`1991. Several kilobytes of memory are employed in these
`SRC systems for filter coefficients alone, in addition to their
`computational complexities falling in the neighborhood of
`10 MIPs for one channel of high quality audio.
`Therefore, attempts have been made using window
`techniques, for example using a Kaiser window, to design
`extremely high-order FIR filters. By using an interpolation
`technique in calculating required coefficients in real-time, a
`single-stage SRC filter system, such as the system 10 shown
`in FIG. 1, has become closer to practical, and hardware
`implementation examples have been reported. Examples
`may be found, e.g., in US. Pat. Nos. 4,780,892, 4,564,918,
`4,825,398 and 4,748,578. However, these implementations
`fall short of the desired efficiencies allowing their utilization
`in affordable digital audio products for consumers.
`Other attempts at avoiding the use of high-order filters
`make use of special functions such as Lagrange polynomials
`or B-spline functions. See, for example, T. O. Ramstad,
`“Digital methods for conversion between arbitrary sampling
`frequencies,” IEEE Trans. Acoust, Speech and Signal
`Processing, vol. ASSP-32, pp. 577—591, June 1984, for an
`article on the former, and S. Cucchi et al., “DSP implemen-
`tation of arbitrary sampling frequency conversion for high
`quality sound application,” Proc. Int. Conf. on Acoust,
`Speech and Signal Processing, pp. 3609—3612, Toronto,
`1991, for the latter. These methods, however, all have the
`drawback of requiring a very large number of computations.
`It is known that multistage decimation or interpolation
`filters are generally more efficient than single-stage filters, in
`
`6
`
`

`

`US 6,487,573 B1
`
`3
`terms of computational complexity. It appears that the same
`conclusion also holds on memory requirements of multi-
`stage filters over single-stage versions. It would therefore be
`desirable to have a multi-stage scheme employing a far
`smaller memory than required in the prior art to store some
`of the SRC filter coefficients, and have an accompanying
`arrangement for efficiently calculating the rest of the filter
`coefficients, in real time.
`Therefore, it is an object of this invention to provide an
`efficient multistage multi-rate filter. It is also an object of the
`present invention to provide a multistage SRC filter that is
`more efficient in both computational and memory require-
`ments than prior art multistage SRC filter implementations.
`It is a further object of the present invention to provide a
`multistage SRC that represents a balance of resource con-
`siderations.
`
`SUMMARY OF THE INVENTION
`
`In accordance with the present invention there is provided
`a method for providing a sample-rate conversion (“SRC”)
`filter on an input stream of sampled data provided at a first
`rate, to produce an output stream of data at a second rate
`different from the first rate. The input stream of sampled data
`is operated on with a first
`low-order interpolation filter
`routine to produce a first stream of intermediate data. The
`first stream of intermediate data is operated on with a first
`simplified interpolation filter routine, having a substantially
`small number of operations to calculate the coefficients
`thereof, to produce a second stream of intermediate data.
`The second stream of intermediate data is operated on with
`a first decimating filter routine to produce the output stream
`of data.
`
`invention can exhibit
`Implementations of the present
`excellent characteristics such as an extremely low memory
`requirement, simple design and implementing procedure and
`moderate computational complexity.
`Filter performance of the new implementations can easily
`reach 100 dB signal-to-noise-ratio (SNR) level. The sim-
`plicity inherent in the present invention allows hardware
`implementation, by using either an ASIC or a programmable
`DSP chip, to be easier and more straightforward than here-
`tofore.
`
`These and other features of the invention will be apparent
`to those skilled in the art from the following detailed
`description of the invention, taken together with the accom-
`panying drawings.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a block diagram showing a typical, all-digital
`SRC system;
`FIG. 2 is a block diagram showing a preferred embodi-
`ment of the present invention;
`FIG. 3 is a graph showing the frequency response of a
`stage-3 filter, with r=3;
`FIG. 4 is a more detailed diagram of a preferred embodi-
`ment of the present invention;
`FIG. 5 is a flow chart showing the general method for
`indexing used in the preferred embodiment of the present
`invention;
`FIG. 6 is a block diagram of a simplified model for
`explaining the indexing used in the preferred embodiment of
`the present invention;
`FIG. 7 is a block diagram of a more detailed model for
`explaining the indexing used in the preferred embodiment of
`the present invention;
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`4
`FIG. 8 is a schematic diagram depicting a data output
`stream as a series of vectors; and
`FIG. 9 is a diagram of an SRC filter that utilizes a Z-A
`modulator.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENT
`
`The four stage SRC filter structure 20 depicted in FIG. 2
`is a block diagram of a preferred embodiment of the present
`invention. It represents an excellent balance between easy
`design procedure, reduced memory/computation needs, and
`simple system control flow. The SRC filter structure 20
`comprises a stage-1 expander/filter 22, a stage-2 expander/
`filter 24, a stage-3 expander/filter 26 and a stage-4 decimator
`28. The stage-4 decimator 28 can be a simple factor of S
`prior art decimator, and so the discussion that follows
`focuses on how best to apply the principles of the present
`invention to design efficiently embodiments of the first three
`filters in stages 1, 2 and 3, and how to design them for
`optimum performance. As an initial matter in that regard,
`only FIR filters are utilized in the embodiments disclosed
`herein, because they offer linear phase responses and effi-
`cient polyphase implementations in multirate processing.
`However, infinite impulse response (“IIR”) digital filters
`may be used, if desired.
`Further, while the embodiment of the present invention
`disclosed in detail herein utilizes three expander/filter
`stages, this is only preferred, but not required. Two of such
`stages, or, alternatively, greater than three such stages may
`be used in the application of the principles of the present
`invention, and still remain within the scope of the present
`invention as defined by the appended claims.
`Now, returning to the preferred embodiment, the stage-1
`expander/filter 22 performs an interpolation of factor R1.
`The value of R,
`is relatively small so that the transition
`bandwidth of the stage-1 expander/filter 22 is still reason-
`ably large. The reason for this is that a large value of R1,
`causing a high output sample rate at the stage-1 expander/
`filter 22, can lead to an extremely narrow transition band
`that, in turn, proportionally results in a very high-order for
`stage-1 filters, which is undesirable. It is desirable to main-
`tain the order of the stage-1 filter between 100 and 800.
`With a small vale of R1, the output sample rate in the stage
`2 expander/filter 24 is relatively high. However, even though
`the output sample rate is significantly higher in the stage-2
`expander/filter 24 than in the previous stage, the transition
`band of the stage-2 expander/filter 24 can be more relaxed
`than that of stage 1 since a large number of the image bands
`have been already removed by the stage-1 expander/filter 22,
`preferably at least half of the image bands. The selection of
`R2 is not arbitrary, however, because it
`is desirable to
`simplify the stage-3 expander/filter 26 given that
`it
`is
`running at a rather high sample rate, RleFLl—n. Thus, the
`choice of R2 depends on how the stage-3 expander/filter 26
`is designed.
`The design aspects of the stage-3 expander/filter 26
`occupy a significant role in the design of the preferred
`embodiment of the present invention. Akey aspect is that the
`stage-3 expander/filter 26 is a relatively simple filter. Simple
`filters have trivial filter coefficients, and the simplest non-
`zero filter coefficients are simply ones. Further, the stage-3
`expander/filter 26 is cascaded. As a general design matter, it
`should be appreciated that a trivial-coefficient-based filter
`can perform acceptably if it is cascaded, even if only two
`times.
`
`The underlying principles for the stage-3 expander/filter
`26 are now described. Let the stage-3 expander/filter 26 be
`
`7
`
`

`

`5
`a cascade of r all-one-coefficients filters that are described
`by:
`
`6
`
`TABLE 1
`
`US 6,487,573 B1
`
`Eq.
`
`(1)
`
`Stage-3 Filter Performance
`
`Notice that, for simplicity, a normalization factor has been
`omitted in Equation (1). Using the filter described by Equa-
`tion (1) in stage 3 substantially removes a significant hurdle
`that has existed heretofore in designing SRC systems: huge
`storage requirements for filter coefficients. As is shown
`below, the coefficients of H3(z) can be evaluated based on
`very simple equations when r is small, say r=2 or 3. The
`magnitude response of H3(z) is easily evaluated as:
`
`w _ sin(wR3/2) ’
`We} ”4 sum/2) ]
`
`Eq.
`
`(2)
`
`The function of H3(z) is to eliminate the image bands
`introduced by padding (i.e., inserting) zero-value samples
`between input samples of stage 3. Furthermore, the mono-
`tonic property of H3(z) between DC and the frequency
`m°=29° m3, at which the filter frequency response reaches its
`first null value, allows the evaluation of Equation (2) at just
`two digital frequency points to determine the performance of
`the filter. The first point is
`
`w1=27r
`
`
`fp
`RFsiin,
`
`where fp denotes maximum frequency of base band signals,
`and R=R1R2R3 is the interpolation factor of the whole SRC
`system. At 001:
`
`,
`
`
`7rfp
`RlRZFsiin
`7r
`
`fp ]
`RFsiin
`
`sin[
`sin[
`
`]
`
`Eq-
`
`(3)
`
`This expression gives the maximum droop in the pass-
`band of the stage-3 expander/filter 26. Thus m2=mO—rt/R
`represents the edge frequency of the first stopband of the
`stage-3 filter, and. the corresponding frequency response at
`(n2 is:
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`.
`”(ZR-R3)
`_ “(T]
`
`’
`
`Eq-
`
`(4)
`
`50
`
`Note the following useful information that is evident from
`the above expression:
`Increasing the value of Rle can greatly improve the filter
`performance of stage 3 in both passband and stopband.
`In other words, the first image band is located further
`away from base band as Rle increases.
`For large values of R3, which indeed is the case in many
`SRC applications, the frequency responses at 001 and (n2
`asymptotically become independent of R3.
`To quantitatively examine the filter performance of stage
`3 at both 001 and (n2 several useful cases are evaluated and
`shown in Table 1 with these parameters: R3=256 (28), fp=20
`kHz and FLM=48 kHz.
`
`55
`
`60
`
`65
`
`R1
`2
`2
`2
`2
`2
`2
`
`R2
`4
`s
`16
`32
`64
`128
`
`H(ej”1) (dB)
`—0.087r
`—0.022r
`—0.006r
`—0.001r
`—0.0003r
`—0.0001r
`
`H(ej”2) (dB)
`—23.6r
`—29.8r
`—36.0r
`—42.1r
`—48.1r
`—54.2r
`
`A value of r=3 is an optimally balanced selection, and is
`considered preferred. It will be clear from an inspection of
`Table 1 that a value of r=1 does not provide nearly adequate
`filter performance in most applications, although the filter
`coefficients are indeed trivial.
`
`With r=2,
`simple:
`
`the coefficients of H3(z) still remain quite
`
`(5) 113(rz)=nl§n§R3
`
`Eq. (5)
`
`Notice that the other half (R3—1) of the filter coefficients
`(R3+1§n§2R3—1) can be obtained from symmetry.
`Although this filter provides good filter performance, over
`100 dB stopband rejection for digital processing of audio
`signals is often desired. This requires the value of Rle to
`be at least 256. It will be recalled that it is preferable to use
`R1=2 for the reason previously described. If R1 is selected
`to be 2, then to maintain the value of Rle as at least 256,
`R2 must be 128 or even larger. Therefore, the sample rate at
`the output of the stage-2 expander/filter 24 reaches a mini-
`mum of 256F57m. That is over 10 MHZ when Fsiin=44’1
`kHz or higher. Also, for R2=128, the order of the stage-2
`expander/filter 24 may well increase to over a thousand in
`order to retain high filter performance. An order of one
`thousand means large amounts of memory are required,
`which is undesirable. It is desirable to maintain the order of
`
`the stage-2 filter between 100 and 1200.
`With r=3, a high-quality filter is easily achieved even
`though Rle has a moderate value. FIG. 3 is a chart in which
`the horizontal axis represents frequency in Hertz and the
`vertical axis represents magnitude of response in dB, show-
`ing such a filter’s frequency response 30 within a frequency
`range including the first stopband 32 that rejects the first
`image band. The first stopband 32, or equivalently, image
`band, starts at 1512 kHz and ends at 1560 kHz with the first
`null sitting at 1536 kHz.
`The filter coefficients when r=3 can be evaluated by the
`following expression:
`
`h3(”)=
`
`
`nn+l
`2
`(
`)
`
`R3(R3+l)
`2
`
`lsan3—1
`3R3
`—(R3—fl)(2R3—l—VL) R3SnST—l
`
`6
`E.
`q H
`
`Notice that R3 has been. assumed to be an even number,
`and again only half of the symmetric coefficients are
`described in Equation (6). The end summing index in
`Equation (6) simply changes to (3R3—1)/2 if an odd integer
`of R3 is chosen. The evaluating procedure to obtain those
`coefficients is sufficiently straightforward to allow compu-
`tation in real time. Thus, each set of polyphase components
`of H3(z) consists of at most three integers that require a total
`of only three integer multiplications and several additions/
`shifts. The largest coefficient of H3(z) is given by 3R3R3/
`4=3><214 for R3=28, requiring merely 16-bit precision,
`which, in turn, requires only 16-bit registers.
`
`8
`
`

`

`US 6,487,573 B1
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`7
`Given r=3, R2 can be chosen as 8 or 16 for audio SRC
`applications. In the following design examples R2=16 and
`R3=256. If strict passband performance is required a simple
`filter can be employed with several taps to pre-distort the
`base-band signals such that
`the droop in the passband
`introduced by the stage-3 expander/filter 26 is well com-
`pensated.
`It is well known that filters with fixed coefficients can be
`implemented more efficiently than those having program-
`mable coefficients. This is particularly true when implement-
`ing filters in ASICs. Therefore, when implementing H3(z),
`since the coefficients are determined by the value of R3 and
`calculated in real time, the design must be general enough to
`accommodate every possible set of filter coefficients that
`will arise in a particular implementation. In any event, it is
`desirable to maintain R3 between 100 and 10,000.
`Upon having chosen the value of R2 the stage-2 expander/
`filter 24 can easily be made with fixed coefficients. Those
`fixed coefficients can further be represented by canonical
`signed digits (CSD) form to greatly simplify computations
`by using add/shift operations rather than normal multiplica-
`tions. Even by using a programmable DSP chip, fixed
`coefficients are easier to handle than time-varying coeffi-
`cients.
`
`In implementing an embodiment of the present invention
`particular attention should be made in designing the first
`stage filter. In this regard, it should be noted that making
`distinct
`the considerations between SRC-UP and SRC-
`
`DOWN modes has so far been ignored in the discussion
`herein. This will now be discussed. The care that should be
`
`exercised in designing efficient stage-1 filters that are able to
`handle both UP and DOWN modes highlights an important
`design consideration when seeking the high efficiency
`achievable by the inventive SRC design methodology dis-
`closed herein.
`
`Some problems are encountered in design when UP
`modes are involved. They are discussed below. The function
`of the stage-1 filter simply erases the image band caused by
`the first interpolator. Therefore, the stage-1 expander/filter
`22 can have fixed coefficients. But in DOWN modes, the
`stage-1 expander/filter 22 must remove high frequency
`components of the input signals in addition to cutting the
`imagc band off.
`Two embodiments of the present invention are presented
`herein for solving this problem, in the form of two methods.
`In the first method, several stage-1 filters may be provided,
`each of which is suitable to a specific DOWN mode. The
`selection from those pre-set filters is easily done by feeding
`an index that points to a correct initial memory address of
`stored filter coefficients. If desired,
`those pre-computed
`coefficient sets can be stored in a host system such as a
`personal computer to save the memory on an ASIC or DSP
`chip.
`The second method calls for a real-time computing
`scheme, similar to H3(z), that generates filter coefficients
`based on a generic set of filter coefficients and still meets the
`filter specifications. Note that
`this computing procedure
`needs to be executed only once when the SRC ratio is
`changed, and stays on until a new SRC ratio is invoked.
`Nonetheless, the first of these two methods is considered
`preferred, and that method is utilized in the following design
`examples.
`Designing filters that can be employed for converting
`sample rates between 44.1 and 48 kHz, based on the above
`design guidelines, will now be considered.
`A. Stage-1 Filters
`Stage-1 filters having an order of 126 provide adequate
`filter performance and require acceptable amounts of
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`memory and computational complexities. In the UP mode,
`i.e., the 44.1—>48 kHz case, a 126th-order FIR filter can
`provide over 100 dB stopband rejection and maintain up to
`20 kHz passband signals. It is also possible to employ a
`half-band FIR filter if a somewhat greater number of aliasing
`errors can be tolerated in the transition band from 20 kHz to
`
`24 kHz. In half-band FIR filters one of the two polyphase
`sub-filters is a delay element. Therefore half-band FIR filters
`need nearly 50% lower computations and coefficient
`memory in comparison to normal FIR filters with the same
`filter orders. To further reduce computations, symmetry in
`filter coefficients can be used. Indeed, by selecting an
`even-order, half-band FIR filters have polyphase compo-
`nents with symmetrical coefficients.
`In the DOWN mode, however, a 126th-order FIR filter
`can only maintain a passband of about 18.5 kHz if the 100
`dB stopband rejection requirement applies.
`Actual filter coefficients for a Stage-1 filter used in a
`Matlab simulation of an embodiment of the present inven-
`tion are found in Appendix A. The designer may wish to
`select other coefficients to accommodate specific application
`constraints and/or performance objectives. Optimal quanti-
`zation of filter coefficients may be considered by the
`designer, as well. All of such variations are well within the
`purview of those of ordinary skill in this art area.
`B. Stage-2 Filters
`Only the stage-2 expander/filter 24 should have fixed
`coefficients that are independent of the SRC mode. To be
`consistent with the filter performance in the stage-1
`expander/filter 22 configured as described above, a 143rd-
`order FIR filter should be used. The order number 143 offers
`
`an advantage in that every polyphase component has the
`same number of coefficients,
`that is, nine, when R2=16.
`Although the polyphase components may no longer have
`symmetric coefficients, half of the polyphase components
`have coefficients that are mirror-symmetric with their coun-
`terparts in the other half of the polyphase components. Such
`a property may be exploited to save coefficient memories.
`Actual filter coefficients for a Stage-2 filter used in a
`Matlab simulation of an embodiment of the present inven-
`tion are found in Appendix B. The designer may wish to
`sclcct othcr cocfficicnts to accommodatc spccific application
`constraints and/or performance objectives. Optimal quanti-
`zation of filter coefficients may be considered by the
`designer, as well. All of such variations are well within the
`purview of those of ordinary skill in this art area.
`In this connection, the designer may wish to consider for
`stage-2 filters a cascade of several half-band FIR filters
`having half zero filter coefficients, which results in a need for
`only half of the computations otherwise, as well as half of
`the memory requirement. The designer should keep in mind,
`however,
`that a drawback of using a cascade of several
`half-band FIR filters is the need for a more complicated
`indexing scheme than that described in the following sec-
`tions.
`
`C. Stage-3 Filters
`This filter has already been discussed in detail in the
`previous section. Note, however, that it might be preferred
`to make this filter fully programmably controlled by select-
`ing R3 in real time. Remember that larger values of R3
`require higher dynamic ranges in filtering computations.
`Since the impulse response of this filter is very smooth, it
`is possible to compress the coefficients. Piecewise linear-
`ization may be used,
`for example. However, since the
`coefficients are already easily calculated, and since the
`filtering operation does not use neighboring coefficients in
`the computation of any given output sample, it is not clear
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`US 6,487,573 B1
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`9
`that significant savings would result from compression, but
`the implementation enhancement is suggested in the interest
`of full disclosure.
`
`D. Implementation Architecture
`Amore detailed diagram of a preferred implementation of
`the new SRC filter is shown in FIG. 4. The SRC filter 40
`
`includes three expander/filter stages 42, 44, 46, and a
`decimator stage 48. The stage-1 expander/filter 42 includes
`two polyphase sub-filters 50, 52, corresponding to R1=2,
`each receiving the input x(n) provided at a sample rate of
`FLl-n. The outputs of polyphase sub-filters 50, 52, are
`selected at a rate of ZFLL-n, as shown by switch 54, and
`provided at
`that rate as the input x1(n)
`to the stage-2
`expander/filter 44.
`The stage-2 expander/filter 44 includes sixteen polyphase
`sub-filters 60, 62, 64, .
`.
`. 66, corresponding to R2=16, each
`receiving the input x1(n). The outputs of polyphase sub-
`filters 60, 62, 64,
`.
`.
`. 66, are selected sequentially and
`cyclically at a rate of 32FLl—n, in as shown by switch 68, and
`provided at
`that
`rate as the input q(n)
`to the stage-3
`expander/filter 46.
`The stage-3 expander/filter 46 includes R3 polyphase
`sub-filters 70, 72, 74, .
`.
`. 76, each receiving the input q(n).
`The outputs of polyphase sub-filters 70, 72, 74, .
`.
`. 76, are
`selected sequentially and cyclically at a rate of 32R3FLL-n, as
`shown by switch 78, and provided at that rate as the input to
`the stage-4 decimator 48. The output of decimator 48 is the
`output y(n) of the SRC filter 40.
`In practice,
`the stage-4 factor-S decimating must be
`merged into the three previous stages to avoid any redundant
`computations that are not related to output samples at a
`required sample rate. This is accomplished in the preferred
`embodiments herein by a novel
`indexing technique,
`explained below. The resulting memory size for the SRC
`filter coefficients is only 136 words, which is more than an
`order of magnitude reduction in comparison to the prior art
`SRC systems described in the article by R. Adams and T.
`Kwan, and the article by S. Park et al., cited above. On the
`other hand, the number of multiplications is 97 per output
`sample, a moderate quantity for a high quality SRC system.
`An SRC procedure for converting samples provided at a
`rate of 48 kHz to a rate of 44.1 kHz will now be explained
`in detail, in conjunction with a Matlab listing implementing
`such procedure. This procedure includes a novel indexing
`scheme alluded to above. It will be recalled that it was
`
`pointed out that major increases in storage and processing
`efficiencies are obtained in the preferred embodiments by
`way of such novel indexing scheme. This indexing is best
`understood by working backwards from the output sample.
`FIG. 5 is a flow chart showing the steps in determining the
`current output sample. Thus, the first step 80 is to determine
`which stage-3 output sample will be the current SRC output
`sample. The second step 82 is to determine which stage-2
`output samples will be used to form the appropriate stage-3
`output sample. The third step 84 is to determine the coef-
`ficients of the stage-3 filters that will be applied to the
`stage-2 output samples to form the needed stage-3 output
`sample, and to compute those coefficients. The fourth step
`86 is to determine