I 1111111111111111 11111 1111111111 111111111111111 IIIII IIIII IIIIII IIII IIII IIII
`US0073 83453B2
`
`c12) United States Patent
`Youngs
`
`(IO) Patent No.:
`(45) Date of Patent:
`
`US 7,383,453 B2
`*Jun. 3, 2008
`
`(54) CONSERVING POWER BY REDUCING
`VOLTAGE SUPPLIED TO AN
`INSTRUCTION-PROCESSING PORTION OF
`A PROCESSOR
`
`(75)
`
`Inventor: Lynn R. Youngs, Cupertino, CA (US)
`
`(73) Assignee: Apple, Inc, Cupertino, CA (US)
`
`( *) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 55 days.
`
`This patent is subject to a terminal dis(cid:173)
`claimer.
`
`(21) Appl. No.: 11/213,215
`
`(22) Filed:
`
`Aug. 25, 2005
`
`(65)
`
`Prior Publication Data
`
`US 2005/0283628 Al
`
`Dec. 22, 2005
`
`Related U.S. Application Data
`
`(63) Continuation of application No. 11/103,911, filed on
`Apr. 11, 2005, now Pat. No. 6,973,585, which is a
`continuation of application No. 10/135,116, filed on
`Apr. 29, 2002, now Pat. No. 6,920,574.
`
`(51)
`
`Int. Cl.
`G06F 1100
`(2006.01)
`G06F 1126
`(2006.01)
`(52) U.S. Cl. ....................... 713/300; 713/320; 713/324
`
`(58) Field of Classification Search ................. 713/300
`See application file for complete search history.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`5,666,537 A *
`Debnath et al.
`............ 713/322
`9/1997
`6,347,379 Bl*
`Dai et al.
`................... 713/320
`2/2002
`6,721,892 Bl*
`Osborn et al. .............. 713/300
`4/2004
`6,792,551 B2 *
`Dai ............................ 713/320
`9/2004
`6,795,896 Bl *
`Hart et al.
`.................. 711/118
`9/2004
`2003/0056127 Al*
`Vaglica ....................... 713/300
`3/2003
`2003/0120959 Al
`Bohrer et al. ............... 713/320
`6/2003
`2003/0120962 Al
`Dai et al.
`................... 713/320
`6/2003
`* cited by examiner
`
`Primary Examiner-Rehana Perveen
`Assistant Examiner-Stefan Stoynov
`(74) Attorney, Agent, or Firm-Park, Vaughan & Fleming,
`LLP; Edward J. Grundler
`
`(57)
`
`ABSTRACT
`One embodiment of the present invention provides a system
`that facilitates reducing static power consumption of a
`processor. During operation, the system receives a signal
`indicating that instruction execution within the processor is
`to be temporarily halted. In response to this signal, the
`system halts an instruction-processing portion of the pro(cid:173)
`cessor, and reduces the voltage supplied to the instruction(cid:173)
`processing portion of the processor. Full voltage is main(cid:173)
`tained to a remaining portion of the processor, so that the
`remaining portion of the processor can continue to operate
`while the instruction-processing portion of the processor is
`in reduced power mode.
`
`21 Claims, 3 Drawing Sheets
`
`CLOCK SIGNAL 130
`
`INTERRUPTS 128
`
`INTERRUPT PROCESSOR 112
`
`ARITHMETIC-LOGIC UNIT 104
`
`PROCESSOR 102
`
`REAL-TIME CLOCK 114
`
`REGISTER FILES 106
`
`CLOCK DISTRIBUTION
`CIRCUITRY 116
`
`PIPELINES 108
`
`L2 CACHE 118
`
`L 1 CACHES 110
`
`CACHE TAGS 120
`
`NON-CORE POWER AREA 124
`
`CORE POWER AREA 126
`
`MEMORY
`SIGNALS 132
`
`NON-CORE POWER 136
`
`CORE POWER 134
`
`1
`
`RS1036
`Rohde & Schwarz Gmbh & Co., KG vs. Tektronix, Inc.
`IPR2018-00643
`
`

`

`U.S. Patent
`
`Jun.3,2008
`
`Sheet 1 of 3
`
`US 7,383,453 B2
`
`CLOCK SIGNAL 130
`
`INTERRUPTS 128
`
`INTERRUPT PROCESSOR 112
`
`PROCESSOR 102
`
`~ I ARITHMETIC-LOGIC UNIT 104
`
`REAL-TIME CLOCK 114
`
`REGISTER FILES 106
`
`CLOCK DISTRIBUTION
`CIRCUITRY 116
`
`PIPELINES 108
`
`L2 CACHE 118
`
`L 1 CACHES 110
`
`CACHE TAGS 120
`
`- - - CACHE SNOOP CIRCUITRY 122
`
`NON-CORE POWER AREA 124
`
`CORE POWER AREA 126
`
`MEMORY
`SIGNALS 132
`
`NON-CORE POWER 136
`
`CORE POWER 134
`
`FIG. 1A
`
`2
`
`

`

`U.S. Patent
`
`Jun.3,2008
`
`Sheet 2 of 3
`
`US 7,383,453 B2
`
`CLOCK SIGNAL 130
`
`INTERRUPTS 128
`
`REAL-TIME CLOCK 114
`
`CLOCK DISTRIBUTION
`CIRCUITRY 116
`
`PROCESSOR 102,
`
`ARITHMETIC-LOGIC UNIT 104
`
`REGISTER FILES 106
`
`PIPELINES 108
`
`L 1 CACHES 110
`
`.I
`·1
`
`.I
`·1
`
`I INTERRUPT PROCESSOR 112 I ~
`I ~
`I i
`.I
`·1
`NON-CORE POWER AREA 124
`..............................
`I
`.I
`·1
`I
`
`L2 CACHE 118
`
`CACHE TAGS 120
`
`~: CACHE SNOOP CIRCUITRY 1221
`
`CORE POWER AREA 126
`
`MEMORY
`SIGNALS 132
`
`NON-CORE POWER 136
`
`CORE POWER 134
`
`FIG. 1B
`
`3
`
`

`

`U.S. Patent
`
`Jun.3,2008
`
`Sheet 3 of 3
`
`US 7,383,453 B2
`
`START
`
`MONITOR PROCESSOR LOAD 202
`
`YES
`
`NO
`
`YES
`
`HALT PROCESSOR 208
`
`SAVE STATE 214
`
`WAIT FOR INTERRUPT 210
`
`HALT PROCESSOR 216
`
`RESTART PROCESSOR 212
`
`REDUCE CORE POWER 218
`
`WAIT FOR INTERRUPT 220
`
`RESTORE CORE POWER 222
`
`RESTART PROCESSOR 224
`
`RESTORE STATE 226
`
`FIG. 2
`
`4
`
`

`

`US 7,383,453 B2
`
`1
`CONSERVING POWER BY REDUCING
`VOLTAGE SUPPLIED TO AN
`INSTRUCTION-PROCESSING PORTION OF
`A PROCESSOR
`
`RELATED APPLICATION
`
`This application is a continuation of U.S. patent applica(cid:173)
`tion Ser. No. 11/103,911, filed 11 Apr. 2005 now U.S. Pat
`No. 6,973,585. This application hereby claims priority under 10
`35 U.S.C. §120 to the above-listed application. Note that
`pending U.S. patent application Ser. No. 11/103,911 is itself
`a continuation of U.S. patent application Ser. No. 10/135,
`116, filed 29 Apr. 2002 now U.S. Pat. No. 6,920,574.
`
`BACKGROUND
`
`15
`
`25
`
`2
`indicating that instruction execution within the processor is
`to be temporarily halted. In response to this signal, the
`system halts an instruction-processing portion of the pro(cid:173)
`cessor, and reduces the voltage supplied to the instruction-
`s processing portion of the processor. Full voltage is main(cid:173)
`tained to a remaining portion of the processor, so that the
`remaining portion of the processor can continue to operate
`while the instruction-processing portion of the processor is
`in reduced power mode.
`In one embodiment of the present invention, reducing the
`voltage supplied to the instruction-processing portion of the
`processor involves reducing the voltage to a minimum value
`that maintains state information within the instruction-pro(cid:173)
`cessing portion of the processor.
`In one embodiment of the present invention, reducing the
`voltage supplied to the instruction-processing portion of the
`processor involves reducing the voltage to zero.
`In one embodiment of the present invention, the system
`saves state information from the instruction-processing por-
`20 tion of the processor prior to reducing the voltage supplied
`to the instruction-processing portion of the processor. This
`state information can either be saved in the remaining
`portion of the processor or to the main memory of the
`computer system.
`In one embodiment of the present invention, upon receiv(cid:173)
`ing a wakeup signal, the system: restores full voltage to the
`instruction-processing portion of the processor; restores
`state information to the instruction-processing portion of the
`processor; and resumes processing of computer instructions.
`In one embodiment of the present invention, maintaining
`full voltage to the remaining portion of the processor
`involves maintaining full voltage to a snoop-logic portion of
`the processor, so that the processor can continue to perform
`cache snooping operations while the instruction-processing
`35 portion of the processor is in the reduced power mode.
`In one embodiment of the present invention, the system
`also reduces the voltage to a cache memory portion of the
`processor. In this embodiment, the system writes cache
`memory data to main memory prior to reducing the voltage.
`In one embodiment of the present invention, the remain(cid:173)
`ing portion of the processor includes a control portion of the
`processor containing interrupt circuitry and clock circuitry.
`In one embodiment of the present invention, the remain(cid:173)
`ing portion of the processor includes a cache memory
`45 portion of the processor.
`
`1. Field of the Invention
`The present invention relates to techniques for conserving
`power usage in computer systems. More specifically, the
`present invention relates to a method and an apparatus for
`reducing power consumption in a processor by reducing
`voltage supplied to an instruction-processing portion of the
`processor, while maintaining voltage to other portions of the
`processor.
`2. Related Art
`Dramatic advances in integrated circuit technology have
`led to corresponding increases in processor clock speeds.
`Unfortunately, these increases in processor clock speeds
`have been accompanied by increased power consumption. 30
`Increased power consumption is undesirable, particularly in
`battery-operated devices such as laptop computers, for
`which there exists a limited supply of power. Any increase
`in power consumption decreases the battery life of the
`computing device.
`Modem processors are typically fabricated using Comple(cid:173)
`mentary Metal Oxide Semiconductor (CMOS) circuits.
`CMOS circuits typically consume more power while the
`circuits are switching, and less power while the circuits are
`idle. Designers have taken advantage of this fact by reducing 40
`the frequency of ( or halting) clock signals to certain portions
`of a processor when the processor is idle. Note that some
`portions of the processor must remain active, however. For
`example, a cache memory with its associated snoop circuitry
`will typically remain active as well as interrupt circuitry and
`real-time clock circuitry.
`Although reducing the frequency of ( or halting) a system
`clock signal can reduce the dynamic power consumption of
`a processor, static power consumption is not significantly
`affected. This static power consumption is primarily caused
`by leakage currents through the CMOS devices. As integra(cid:173)
`tion densities of integrated circuits continue to increase,
`circuit devices are becoming progressively smaller. This
`tends to increase leakage currents, and thereby increases
`static power consumption. This increased static power con- 55
`sumption results in reduced battery life, and increases cool(cid:173)
`ing system requirements for battery operated computing
`devices.
`What is needed is a method and an apparatus that reduces
`static power consumption for a processor in a battery 60
`operated computing device.
`
`BRIEF DESCRIPTION OF THE FIGURES
`
`FIG. lA illustrates different power areas within processor
`so 102 in accordance with an embodiment of the present
`invention.
`FIG. lB illustrates alternate power areas within processor
`102 in accordance with an embodiment of the present
`invention.
`FIG. 2 is a flowchart illustrating the process of monitoring
`processor load and switching to power saving modes in
`accordance with an embodiment of the present invention.
`
`DETAILED DESCRIPTION
`
`SUMMARY
`
`One embodiment of the present invention provides a
`system that facilitates reducing static power consumption of
`a processor. During operation, the system receives a signal
`
`The following description is presented to enable any
`person skilled in the art to make and use the invention, and
`is provided in the context of a particular application and its
`requirements. Various modifications
`to
`the disclosed
`65 embodiments will be readily apparent to those skilled in the
`art, and the general principles defined herein may be applied
`to other embodiments and applications without departing
`
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`

`US 7,383,453 B2
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`3
`from the spirit and scope of the present invention. Thus, the
`present invention is not intended to be limited to the embodi(cid:173)
`ments shown, but is to be accorded the widest scope
`consistent with the principles and features disclosed herein.
`
`Processor 102
`FIG. lA illustrates different power areas within processor
`102 in accordance with an embodiment of the present
`invention. Processor 102 is divided into a core power area
`126, and a non-core power area 124. Core power area 126
`includes the instruction-processing portion of processor 102.
`Specifically, core power area 126 includes arithmetic-logic
`unit 104, register files 106, pipelines 108, and possibly level
`one (Ll) caches 110. Note that Ll caches 110 can alterna(cid:173)
`tively be located in non-core power area 124.
`Arithmetic-logic unit 104 provides computational and
`logical operations for processor 102. Register files 106
`provide source operands, intermediate storage, and destina(cid:173)
`tion locations for instructions being executed by arithmetic(cid:173)
`logic unit 104. Pipelines 108 provides a steady stream of 20
`instructions to arithmetic-logic unit 104. Instructions in
`pipelines 108 are decoded in transit. Therefore, pipelines
`108 may contain instructions in various stages of decoding
`and execution. Ll caches 110 include data caches and
`instruction caches for arithmetic-logic unit 104. Ll caches 25
`110 are comprised of very high-speed memory to provide
`fast access for instructions and data. In one embodiment of
`the present invention, Ll caches 110 includes a write(cid:173)
`through data cache.
`Non-core power area 124 comprises the remaining por(cid:173)
`tion of processor 102 and includes interrupt processor 112,
`real-time clock 114, clock distribution circuitry 116, level
`two (L2) caches 118, cache tags 120, and cache snoop
`circuitry 122. In general, non-core power area 124 includes
`portions of processor 102 that are not directly involved in
`processing instructions, and that need to operate while
`instruction processing is halted.
`Interrupt processor 112 monitors interrupts 128 and peri(cid:173)
`odically interrupts the execution of applications to provide
`services to external devices requiring immediate attention.
`Interrupt processor 112 can also provide a wake-up signal to
`core power area 126 as described below. Real-time clock
`114 provides time-of-day services to processor 102. Typi(cid:173)
`cally, real-time clock 114 is set upon startup from a battery
`operated real-time clock in the computer and thereafter
`provides time to the system. Clock distribution circuitry 116
`provides clock signals for processor 102. Distribution of
`these clock signals can be switched off or reduced for
`various parts of processor 102. For example, clock distri(cid:173)
`bution to core power area 126 can be stopped while the clock 50
`signals to non-core power area 124 continue. The acts of
`starting and stopping of these clock signals are known in the
`art and will not be described further. Real-time clock 114
`and clock distribution circuitry 116 receive clock signal 130
`from the computer system. Clock signal 130 is the master
`clock signal for the system.
`L2 cache 118 provides a second level cache for processor
`102. Typically, an L2 cache is larger and slower that an Ll
`cache, but still provides faster access to instructions and data
`than can be provided by main memory. Cache tags 120
`provide an index into data stored in L2 cache 118. Cache
`snoop circuitry 122 invalidates cache lines base primarily on
`other processors accessing their own cache lines, or I/O
`devices doing memory transfers, even when instruction
`processing has been halted. L2 cache 118, cache tags 120,
`and cache snoop circuitry 122 communicate with the com(cid:173)
`puter system through memory signals 132.
`
`45
`
`5
`
`4
`Non-core power area 124 receives non-core power 136
`and core power area 126 receives core power 134. The
`voltage applied for non-core power 136 remains at a voltage
`that allows circuitry within non-core power area 124 to
`remain fully active at all times. In contrast, non-core power
`136 may provide different voltages to non-core power area
`124 based upon the operating mode of processor 102. For
`example, if processor 102 is a laptop attached to external
`electrical power, the voltage provided to non-core power
`10 136 (and to core power 134 during instruction processing)
`may be higher than the minimum voltage, thus providing
`faster execution of programs.
`The voltage applied to core power 134 remains suffi-
`15 ciently high during instruction processing so that core power
`area 126 remains fully active. However, when processor 102
`receives a signal that processing can be suspended, the
`voltage supplied by core power 134 can be reduced.
`In one embodiment of the present invention, the voltage
`in core power 134 is reduced to the minimum value that will
`maintain state information within core power area 126, but
`this voltage is not sufficient to allow processing to continue.
`In another embodiment of the present invention, the voltage
`at core power 134 is reduced to zero. In this embodiment, the
`state of core power area 126 is first saved before the voltage
`is reduced to zero. This state can be saved in a dedicated
`portion of L2 cache 118, in main memory, or in another
`dedicated storage area. Upon receiving an interrupt or other
`signal indicating that processing is to resume, the voltage in
`30 core power 134 is restored to a normal level, saved state is
`restored, and processing is restarted.
`FIG. 1B illustrates an alternative partitioning of power
`areas within processor 102 in accordance with an embodi(cid:173)
`ment of the present invention. As shown in FIG. 1B, L2
`35 cache 118, cache tags 120, and cache snoop circuitry 122 are
`included in core power area 126 rather than in non-core
`power area 124. In this embodiment, the voltage supplied as
`core power 134 is reduced or set to zero as described above,
`however, the cache circuitry within processor 102 is also put
`40 into the reduced power mode. Prior to reducing the voltage
`supplied to core power area 126, data stored in L2 cache 118
`is flushed to main memory. Additionally, if the voltage at
`core power 134 is reduced to zero, the state of processor 102
`is first saved in main memory.
`
`Monitoring and Switching
`FIG. 2 is a flowchart illustrating the process of monitoring
`processor load and switching to power saving modes in
`accordance with an embodiment of the present invention.
`The system starts by monitoring the processor load (step
`202). Next, the system determines if the processor will be
`needed soon (step 204). This determination is made based on
`the current execution pattern and the cost of entering and
`recovering from nap mode. This cost, calculated in power
`55 usage, must be less than the power wasted by not going into
`nap mode. If the processor will be needed soon at step 204,
`the process returns to step 202 to continue monitoring the
`processor load.
`If the processor will not be needed soon at step 204, the
`60 system determines if the processor has been taking long naps
`recently (step 206). If not, the system enters a normal nap
`mode, which involves halting the processor without reduc(cid:173)
`ing any voltages (step 208). Typically, halting the processor
`involves removing the clock signals to the core power area
`65 of the processor. After halting the processor, the system
`waits for an interrupt (step 210). Upon receiving an interrupt
`or other signal requiring a restart, the system restarts instruc-
`
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`5
`tion processing (step 212). After restarting instruction pro(cid:173)
`cessing, the process returns to step 202 to continue moni(cid:173)
`toring the processor load.
`If the processor has recently been taking long naps at step
`206, the system enters a deep nap mode, which involves
`saving the state information from the core power area (step
`214), halting the processor (step 216), and then reducing the
`voltage supplied to the core power area (step 218). After
`reducing the voltage, the system waits for an interrupt (step
`220).
`Upon receiving the interrupt or other signal requiring a
`restart, the system restores the voltage to the core power area
`(step 222). Next, the modules within the core power area are
`restarted (step 224). The system then restores the state
`information that was saved at step 214 (step 226). After the 15
`processor has been restarted, the process returns to step 202
`to continue monitoring the processor load. Note that the
`above description applies when the processor is used to save
`and restore the state information. In cases where dedicated
`hardware saves and restores the state information, steps 214 20
`and 216, and steps 224 and 226 can be reversed. Note also
`that if the voltage supplied to the core power area 126 is
`reduced but maintained at a level where modules in the core
`power do not lose state information, steps 216 and 224 are
`not required.
`The foregoing descriptions of embodiments of the present
`invention have been presented for purposes of illustration
`and description only. They are not intended to be exhaustive
`or to limit the present invention to the forms disclosed.
`Accordingly, many modifications and variations will be 30
`apparent to practitioners skilled in the art. Additionally, the
`above disclosure is not intended to limit the present inven(cid:173)
`tion. The scope of the present invention is defined by the
`appended claims.
`What is claimed is:
`1. An instruction-processing system with minimal static
`power leakage, the instruction-processing system compris(cid:173)
`ing:
`a core with instruction-processing circuitry;
`an area coupled to the core;
`a core voltage provided to the core; and
`an area voltage provided to the area;
`wherein in a normal operation mode:
`a clock signal to the core is active;
`the core voltage is a first value;
`the core is active;
`the area voltage is a second value; and
`the area is active;
`wherein in a first power-saving mode that is exited upon
`receipt of an interrupt signal:
`the clock signal to the core is inactive;
`the core voltage is equal to or greater than the first
`value; and
`the area voltage is equal to or greater than the second 55
`value;
`wherein in a second power-saving mode that can be exited
`upon receipt of a signal that is not an interrupt signal:
`the clock signal to the core is inactive;
`the core voltage is less than the first value; and
`the area voltage is equal to or greater than the second
`value.
`2. The instruction-processing system of claim 1, wherein
`the first power-saving mode can be exited upon receipt of a
`signal that is not an interrupt signal.
`3. The instruction-processing system of claim 1, wherein
`the area comprises a cache.
`
`6
`4. The instruction-processing system of claim 3, wherein
`the area further comprises cache tags.
`5. The instruction-processing system of claim 1, wherein
`prior to entering the second power-saving mode, the state of
`the core is saved to a memory.
`6. The instruction-processing system of claim 1, wherein
`upon exiting the second power-saving mode, the state of the
`core is restored.
`7. The instruction-processing system of claim 1, wherein
`10 in the second power-saving mode, the core voltage is at zero.
`8. A method for minimizing static power leakage in an
`instruction-processing system, wherein the instruction-pro(cid:173)
`cessing system comprises a core with instruction-processing
`circuitry, an area coupled to the core, a core voltage provided
`to the core, and an area voltage provided to the area, the
`method comprising:
`entering a normal operation mode by:
`providing a clock signal to the core;
`providing the core with a core voltage that is equal to
`a first value;
`providing the area with an area voltage that is equal to
`a second value;
`entering a first power-saving mode by:
`disabling the clock signal to the core;
`providing the core with a core voltage that is equal to
`or greater than the first value; and
`providing the area with an area voltage that is equal to
`or greater than the second value;
`exiting the first power-saving mode upon receipt of an
`interrupt signal;
`entering a second power-saving mode by:
`disabling the clock signal to the core;
`setting the core voltage to a value less than the first
`value; and
`providing the area with an area voltage that is equal to
`or greater than the second value; and
`exiting the second power-saving mode upon receipt of a
`signal that is not an interrupt signal.
`9. The method of claim 8, further comprising exiting the
`40 first power-saving mode upon receipt of a signal that is not
`an interrupt signal.
`10. The instruction-processing system of claim 8, wherein
`the area comprises a cache.
`11. The method of claim 10, wherein the area further
`45 comprises cache tags.
`12. The method of claim 8, further comprising saving the
`state of the core to a memory prior to entering the second
`power-saving mode.
`13. The method of claim 8, further comprising restoring
`the state of the core upon exiting the second power-saving
`mode.
`14. The method of claim 8, wherein in the second power(cid:173)
`saving mode, setting the core voltage to the value less than
`the first value comprises setting the core voltage to zero.
`15. A computer-readable medium containing data repre(cid:173)
`senting an instruction-processing system with minimal static
`power leakage, the instruction- processing system compris(cid:173)
`ing:
`a core with instruction-processing circuitry;
`an area coupled to the core;
`a core voltage provided to the core; and
`an area voltage provided to the area;
`wherein in a normal operation mode:
`a clock signal to the core is active;
`the core voltage is a first value;
`the core is active;
`
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`60
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`the area voltage is a second value; and
`the area is active;
`wherein in a first power-saving mode that is exited upon
`receipt of an interrupt signal:
`the clock signal to the core is inactive;
`the core voltage is equal to or greater than the first
`value; and
`the area voltage is equal to or greater than the second
`value;
`wherein in a second power-saving mode that can be exited 10
`upon receipt of a signal that is not an interrupt signal:
`the clock signal to the core is inactive;
`the core voltage is less than the first value; and
`the area voltage is equal to or greater than the second
`value.
`16. The computer-readable medium of claim 15, wherein
`the first power-saving mode can be exited upon receipt of a
`signal that is not an interrupt signal.
`
`15
`
`8
`17. The computer-readable medium of claim 15, wherein
`the area comprises a cache.
`18. The computer-readable medium of claim 17, wherein
`the area further comprises cache tags.
`19. The computer-readable medium of claim 15, wherein
`prior to entering the second power-saving mode, the state of
`the core is saved to a memory.
`20. The computer-readable medium of claim 15, wherein
`upon exiting the second power-saving mode, the state of the
`core is restored.
`21. The computer-readable medium stem of claim 15,
`wherein in the second power-saving mode, the core voltage
`is at zero.
`
`* * * * *
`
`8
`
`

`

`UNITED STATES PATENT AND TRADEMARK OFFICE
`CERTIFICATE OF CORRECTION
`
`: 7,383,453 B2
`PATENT NO.
`APPLICATION NO. : 11/213215
`DATED
`: June 3, 2008
`: Lynn R. Youngs
`INVENTOR(S)
`
`Page 1 of 1
`
`It is certified that error appears in the above-identified patent and that said Letters Patent is
`hereby corrected as shown below:
`
`Title Page item [73]
`
`In the Assignee Name ( on page 1 ), please delete "Apple, Inc.".
`
`In the Assignee name ( on page 1 ), please insert --APPLE INC.--.
`
`Signed and Sealed this
`
`Thirteenth Day of January, 2009
`
`JONW.DUDAS
`Director of the United States Patent and Trademark Office
`
`9
`
`

`

`UNITED STATES PATENT AND TRADEMARK OFFICE
`CERTIFICATE OF CORRECTION
`
`: 7,383,453 B2
`PATENT NO.
`APPLICATION NO. : 11/213215
`DATED
`: June 3, 2008
`: Lynn R. Youngs
`INVENTOR(S)
`
`Page 1 of 1
`
`It is certified that error appears in the above-identified patent and that said Letters Patent is
`hereby corrected as shown below:
`
`Title page Item [73]
`In the Assignee Name ( on page 1 ), please delete "Apple, Inc.".
`
`Title page Item [73]
`In the Assignee Name ( on page 1 ), please insert --APPLE INC.--.
`
`Signed and Sealed this
`
`Seventeenth Day of February, 2009
`
`JOHN DOLL
`Acting Director of the United States Patent and Trademark Office
`
`10
`
`

`

`UNITED STATES PATENT AND TRADEMARK OFFICE
`CERTIFICATE OF CORRECTION
`
`: 7,383,453 B2
`PATENT NO.
`APPLICATION NO. : 11/213215
`: June 3, 2008
`DATED
`: Lynn R. Young
`INVENTOR(S)
`
`Page 1 of 3
`
`It is certified that error appears in the above-identified patent and that said Letters Patent is hereby corrected as shown below:
`
`In claim 1 (at column 5, line 36), please delete the word "minimal" and insert the word,
`--minimized-- so the line reads "A instruction-processing system with minimized static".
`
`In claim 1 (at column 5, line 45), please insert the words, --that is sufficient to maintain the
`state information of the instruction-processing circuitry-- so the line reads "the core voltage is a
`first value that is sufficient to maintain the state information of the instruction-processing
`circuitry".
`
`In claim 1 (at column 5, line 47), please insert the words, --that is sufficient to maintain the
`data stored in the area-- so the line reads "the area voltage is a second value that is sufficient
`to maintain the data stored in the area".
`
`In claim 1 (at column 5, line 49), please delete the word "is" and insert the words, --can be-(cid:173)
`so the line reads "wherein in a first power-saving mode that can be exited upon".
`
`In claim 1 (at column 5, line 53), please delete the words "equal to or greater than the first
`value" and insert the words, --sufficient to maintain the state information of the instruction-processing
`circuitry-- so the line reads "the core voltage is sufficient to maintain the state information of the
`instruction-processing circuitry".
`
`In claim 1 (at column 5, line 55), please delete the words "equal to or greater than the
`second value" and insert the words, --sufficient to maintain the data stored in the area-- so the
`line reads "the area voltage is sufficient to maintain the data stored in the area".
`
`In claim 1 (at column 5, line 61), please delete the words "equal to or greater than the
`second value" and insert the words, --sufficient to maintain the data stored in the area-- so the
`line reads "the area voltage is sufficient to maintain the data stored in the area".
`
`In claim 8 (at column 6, line 19), please delete the words "that is" so the line reads
`"providing the core with a core voltage equal to".
`
`Signed and Sealed this
`
`Eighth Day of June, 20 I 0
`
`David J. Kappos
`Director of the United States Patent and Trademark Office
`
`11
`
`

`

`CERTIFICATE OF CORRECTION ( continued)
`U.S. Pat. No. 7,383,453 B2
`
`Page 2 of 3
`
`In claim 8 (at column 6, line 20), please insert the words, --that is sufficient to maintain the
`state information of the instruction-processing circuitry-- so the line reads "a first value that is
`sufficient to maintain the state information of the instruction-processing circuitry".
`
`In claim 8 (at column 6, line 21), please delete the words "that is" so the line reads
`"providing the area with an area voltage equal to".
`
`In claim 8 (at column 6, line 22), please insert the words, --that is sufficient to maintain the
`data stored in the area-- so the line reads "a second value that is sufficient to maintain the
`data stored in the area".
`
`In claim 8 (at column 6, line 25), please delete the words "equal to" and insert the words,
`--sufficient to maintain the state information of the instruction-processing circuitry-- so the line
`reads "providing the core with a core voltage that is sufficient to maintain the state information
`of the instruction-processing circuitry".
`
`In claim 8 (at column 6, line 26), please delete the words "or greater than the first value".
`
`In claim 8 (at column 6, line 27), please delete the words "equal to" and insert the words,
`--sufficient to maintain the data stored in the area-- so the line reads "providing the area with an
`area voltage that is sufficient to maintain the data stored in the area".
`
`In claim 8 (at column 6, line 28), please delete the words "or greater than the second
`
`value".
`
`In claim 10 (at column 6, line 42), please delete the words "instruction-processing system"
`and insert the word, --method-- so the line reads "the method of claim 8, wherein".
`
`In claim 15 (at column 6, line 56), please delete the words "containing data repre-" and
`insert the words, --storing code which represents-- so the line reads "A computer-readable
`medium storing code which represents".
`
`In claim 15 (at column 6, line 57), please delete the words "senting" and "minimal" and
`insert the word, --minimized-- so the line reads "an instruction-processing system with
`minimized static".
`
`In claim 15 (at column 6, line 66), please insert the words, --that is sufficient to maintain
`the state information of the instruction-processing circuitry-- so the line reads "the core voltage
`is a first value that is sufficient to maintain the state information of the instruction-processing
`circuitry".
`
`In claim 15 (at column 7, line 1), please insert the words, --that is sufficient