United States Patent
`
`[19]
`
`[11] Patent Number:
`
`4,613,976
`
`Sewerinson et a1.
`
`[45] Date of Patent:
`
`Sep. 23, 1986
`
`[54] CONSTANT ENVELOPE OFFSET QPSK
`MODULATOR
`
`[75]
`
`Inventors: Ake Sewerinson, Port Coquitlam;
`Andrew V. Hellquist, Burnaby, both
`of Canada
`
`[73] Assignee: British Columbia Telephone
`Company, Burnaby, Canada
`
`[21] App]. No.: 606,427
`
`[22] Filed:
`
`May 2, 1984
`
`Int. Cl.“ ............................................. H04L 27/18
`[51]
`[52] US. Cl.
`................................... 375/52; 332/16 R;
`332/23 R
`[58] Field of Search ................... 375/52, 53, 67, 9, 46;
`332/9 R, 9 T, 16 R, 16 T, 21, 23 R; 455/615
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`.. 375/53
`3,643,023 2/ 1972 Ragsdale et al.
`.. 375/53
`3,916,101 10/1975 Bertin et a1.
`
`375/53
`......
`4,008,373 2/ 1977 Nash et a1.
`.. 375/53
`4,168,397
`9/1979 Bradley ...........
`.
`
`375/53
`4,229,821 10/1980 De Jager et a1.
`375/53
`4,417,219 11/1983 Brossard et a1.
`4,504,802
`3/1985 Heatherington ...................... 375/52
`
`OTHER PUBLICATIONS
`
`Kato et a1, “Cross—Correlated Phase Shift Keying Sys-
`tem with Improved Envelope Fluctuation”, 1982,
`IEEE Proceeding on Comm, pp. 2E.11—2E.15.
`Feher et al, “New Modulation Techniques for Low
`Cost Power and Bandwidth Efficient Satellite Earth
`Stations”, IEEE Transaction on Communication, vol.
`COM-30, No. 1, Jan. 82, pp. 275—283.
`De Jager et al, “Tamed Frequency Modulation, A
`Novel Method to Achieve Spectrum Economy in Digi-
`tal Transmission”, IEEE Transaction on Communica-
`tion, vol. COM-26, No. 5, May 1978, pp. 534-542.
`D. Muilwijk, “Correlative Phase Shift Keying a Class
`of Constant Envelope Modulation Techniques”, IEEE
`Transaction on Communication, vol. COM 29, Mar.
`1981, pp. 226—236.
`C. Dekker, “The Application of Tamed Frequency
`
`Modulation to Digital Transmission Via Radio”, 1979
`IEEE NTC, 1979, pp. 55.31-55.37.
`D. Muilwijk, J. Noordanus, “Digital Phase Modulation
`Method Giving a Band—Limited Spectrum for Satellite
`Communication”, American Institute of Aeroautics and
`Astronautics, 1980, pp. 391-398.
`
`Primary Examiner—Robert L. Griffin
`Assistant Examiner—Stephen Chin
`Attorney, Agent, or Firm—Russell A. Cannon
`
`[57]
`
`ABSTRACT
`
`The modulator comprises a serial to parallel converter
`which separates alternate bits of a serial-binary data
`stream into I and Q bit streams that are stored in associ-
`ated shift registers, a pair of ROMS that drive associated
`D/A converters, and a quadrature-phase modulator.
`Each bit of the I and Q bit streams has a duration of 2T,
`where T is the bit interval or period of a data bit. Each
`of the ROMS comprises blocks of memory that contain
`a plurality of digital Words. The present and immediate
`past I and Q bits in the shift registers, and a baud clock
`signal of one-half the data signal rate, are applied to
`address inputs of the ROMS for selecting associated
`memory blocks in the 2 ROMS. A counter then clocks
`the ROMS for sequentially outputting the contents of
`the addressed memory blocks to the converters which
`produce analog voltages that phase modulate a carrier
`signal for moving a resultant signal vector with a con-
`stant envelope during each bit interval. The contents of
`the ROMS are selected to provide a substantially con-
`stant amplitude vector whose rate of change w of phase
`satisfies the criteria:
`
`10) = 1(t — 21‘)
`yes
`yes
`no
`no
`
`Q0) = Q(t — 2T)
`yes
`no
`yes
`no
`
`|W|
`0
`W
`2W
`
`0
`
`where W and 2W are constant phase velocities that
`rotate the signal vector a total of 45° and 90°, respec-
`tively, in a bit or symbol interval.
`
`9 Claims, 11 Drawing Figures
`
`TIIIIIG
`CLOCK
`
`2|
`25
`
`DIGITAL
`T0 ANALD
`
`I
`CONVERTER
`
`1
`
`SERIAL YO
`
`PARALLEL
`CONVERTER
`
`.IDFF" SET)
`
`
`DIGITAL
`
`T0 ANALOG
`CONVERTER
`
`
` r.____._.__..___.._
`
`Page 1 of 14
`
`SAMSUNG EXHIBIT 1016
`
`SAMSUNG EXHIBIT 1016
`
`Page 1 of 14
`
`

`

`US. Patent
`
`Sep.23, 1986
`
`Sheetl of7
`
`4,613,976
`
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`Page 2 of 14
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`Page 2 of 14
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`4,613,976
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`Page 3 of 14
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`Page 3 of 14
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`

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`US. Patent
`
`Sep. 23, 1986
`
`Sheet 3 of 7
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`4,613,976
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`Page 4 of 14
`
`Page 4 of 14
`
`

`

`US. Patent
`
`Sep.23,1986
`
`Sheet4of7
`
`4,613,976
`
`
`
`Page 5 of 14
`
`Page 5 of 14
`
`

`

`US. Patent
`
`Sep. 23, 1986
`
`Sheet 5 of 7
`
`4,613,976
`
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`
`Page 6 of 14
`
`Page 6 of 14
`
`

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`US. Patent
`
`Sep. 23, 1986
`
`Sheet 6 of 7
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`Page 7 of 14
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`

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`U.S. Patent
`
`Sep. 23, 1986
`
`Sheet 7 of 7
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`4,613,976
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`Page 8 of 14
`
`
`

`

`4,613,976
`
`1
`
`CONSTANT ENVELOPE OFFSET QPSK
`MODULATOR
`
`BACKGROUND OF INVENTION
`
`2
`(5) D. Muilwijk, “Correlative Phase Shift Keying-a
`Class of Constant Envelope Modulation Techniques”,
`IEEE Transactions on Communications, Vol. COM 29,
`March 1981, pages 226—236.
`(6) C. Dekker, “The Application of Tamed Fre-
`quency Modulation to Digital Transmission Via Ra-
`dio”, 1979 IEEE, NTC 1979, pages 5531—5537.
`(7) D. Muilwijk, J. Noordanus, “Digital Phase Modu-
`lation Methods Giving a Band-Limited Spectrum for
`Satellite Communications”, American Institute of
`Aeronautics and Astronautics, 1980, pages 391—398.
`In QPSK modulation,
`the modulator is preferably
`arranged for generating an angle modulated carrier
`signal or vector, of substantially constant amplitude and
`continuous phase in each symbol interval of length T,
`said phase being determined by a set of rules. In such a
`QPSK modulation system an input data signal may be
`broken into in-phase (I) and quadrature-phase (Q) pulse
`trains receiving odd and even numbered data bits, re-
`spectively. These pulse trains are used to establish the
`amplitude and phase of the signal vector. The magni-
`tude of the signal vector is maintained substantially
`constant as the phase thereof varies in order to prevent
`spectrum spreading. The phase of the signal vector is
`also caused to be continuous for the same reason. In
`
`Ref. 1, a cross-correlated phase shift keying modem
`employs non-linear switching filters in producing the
`desired signal. The generation of hard-limited quadra-
`ture modulated signals and analysis thereof is discussed
`in Ref. 2. In the tamed frequency modulation scheme in
`Ref. 3 and the associated US patent (Ref. 4), digital
`words that dictate the phase change are obtained from
`a pair of memories in accordance with particular code
`rules that require a plurality of successive data bits and
`information from .a quadrant counter.
`An object of this invention is the provision of an
`improved PSK modulation method and apparatus for
`producing angle modulated carrier signals or phasors of
`relatively constant amplitude and continuous phase.
`SUMMARY OF THE INVENTION
`
`In accordance with this invention, an improved
`method of generating a phase shift keying modulated
`signal vector from a digital input data signal in which
`alternate bits are directed into in-phase and quadrature-
`phase I and Q channels, with the current bit that is
`entered into each channel being held constant for the
`time interval 2T of the current and next data bits, and
`wherein the phase of the signal vector varies by pre-
`scribed amounts and in prescribed directions during the
`time or symbol interval T of each data bit, comprises
`the step of causing the rate of change w of phase to be
`determined as follows:
`
`10) = In — 2T)
`yes
`yes
`no
`no
`
`00) = 00 — 2T)
`yes
`no
`yes
`no
`
`M
`0
`W
`W
`2W
`
`where w is the phase velocity or rate of change of
`phase, and W and 2W are constant phase velocities that
`will rotate the signal vector a total of 45° and 90°, re-
`spectively, in one bit time T.
`
`This invention relates to method and apparatus for
`converting a data signal into an offset quadrature-phase
`shift keying (OQPSK) signal for transmission, and more
`particularly to improved method and apparatus for
`producing a QPSK modulated signal having a substan-
`tially constant amplitude and continuous phase.
`Factors that must be considered in selecting a modu-
`lation method for transmitting digital information in a
`satellite communication system include transmit power
`requirements, spectral efficiency, transmission channel
`non-linearities, and the complexity of hardware re-
`quired for implementation. In particular, the frequency
`spectrum associated with the modulation method must
`fit within certain constraints. If the communication
`system uses frequency division multiplex techniques
`with a channel spacing of UT, where T is the symbol
`interval and the reciprocal thereof is equivalent to a full
`QPSK mainlobe, any energy out of this frequency range
`causes adjacent channel interference. QPSK sidelobes
`can be removed through filtering either pre—or post-
`—output amplification. Power requirements and cost
`considerations normally make it desirable to employ
`amplifiers that operate at or near saturation. The choice
`of pre—-—or——post-amplification filtering is influenced by
`the following factors:
`post-amplification filtering allows the use of saturated
`amplifiers without distortion and is often used with
`wideband transmission. For narrow band or fre-
`quency agile applications the complexity of the
`filter is often prohibitive.
`pre-amplification filtering allows for simple spectrum
`shaping, but does simultaneously introduce signal
`envelope fluctuations. Non—linearities introduced
`by an amplifier will reduce these envelope fluctua-
`tions and may result in spectral spreading by resto-
`ration of sidelobes, which can cause adjacent chan-
`nel interference and increase the bit error rate.
`Hence, some type of PSK modulation with reduced
`spectral sidelobes and without envelope amplitude vari-
`ations is preferred. QPSK modulation providing a mod-
`ulated signal having a constant amplitude and continu-
`ous phase is a particularly attractive type of modulation
`that may be used here. Published articles related to PSK
`and which are incorporated herein by reference, are:
`(1) S. Kato, K. Feher, “Cross-Correlated Phase Shift
`Keying (XPSK) System With Improved Envelope
`Fluctuation”, 1982 IEEE Proceedings on Communica-
`tions, pages 2E.1.1—2E.l.5.
`(2) K. Feher, T. Le-Ngoc, H. P. Van, “New Modula-
`tion Techniques for Low Cost Power and Bandwidth
`Efficient Satellite Earth Stations”, IEEE Transactions
`on Communications, Vol. Com-30, No. 1, Jan. 1982,
`pages 275—283.
`(3) F. deJager, C. Dekker, “Tamed Frequency Mod-
`ulation, A Novel Method to Achieve Spectrum Econ-
`omy in Digital Transmission”, IEEE Transactions on
`Communications, Vol. Com-26, No. 5, May 1978, pages
`534-542.
`
`(4) F. de Jager, C. Dekker, D. Muilwijk, “System for
`Data Transmission by Means of An Angle-Modulated
`Carrier of Constant Amplitude”, US. Pat. No.
`4,229,821, issued Oct. 21, 1980.
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`45
`
`50
`
`55
`
`60
`
`65
`
`Page 9 of 14
`
`Page 9 of 14
`
`

`

`3
`
`4,613,976
`
`4
`even numbered bits D2, D4, etc. into the Q data stream
`16 (while holding each data bit on the associated output
`line thereof constant during the subsequent baud inter-
`val of duration 2T). Stated differently, the 1 channel
`data signal is updated at times t1, t3, etc., with the I data
`level being held constant throughout the subsequent
`baud time of 2T. Similarly, the Q channel data signal is
`updated at times t2, t4, etc. with the Q data level being
`held constant throughout the subsequent baud time of
`2T. Thus, the I data bit 11 is equal to Dlvggvhich-is a"
`logic 0) throughout ”the baud time- interval of If be-
`tween tl and t3.‘ Similarly, the Q data bit Q1 is equal to
`lD2 (which is a logic level 0) during the baud time inter-
`val of 2T between times t2-t4, even though the data bit
`D3 between times t3-t4 is now high.
`The registers 15 and 17 may be serial shift registers
`which are clocked by baud clock pulses on line 38 (see
`FIG. 2, waveform 38). The present and immediate past
`I-data bits I(t) and I(t—2T) in register 15 are applied on
`output lines thereof to associated address inputs of the
`two ROMS. Similarly, the present and immediate past
`Q-data bits Q(t) and Q(t—ZT) in register 17 are applied
`on output lines thereof to associated address inputs of
`the two ROMS. It is these present and past I and Q-data
`bits, together with the baud clock BC on line 38, which
`make up unique addresses of associated blocks of mem-
`ory in the two ROMS (see FIG. 7) which contain infor-
`mation in look-up tables for causing a signal vector or
`phasor 30 on line 30 to move in a prescribed manner and
`at rates in accordance with a unique set of rules.
`Briefly, there are only eight positions at which the
`signal vector 30 may reside at the end of a symbol inter-
`val. The end points of these allowable phasor positions
`are on a circle 62 of constant amplitude and have phases
`that are multiples of 45° with respect to the origin (see
`FIG. 5). Only four of these phasors (at i45° and
`i 135°) are rest states where the phasor can remain
`throughout a symbol
`interval. Ideally the phasor 30
`continuously moves along the circle 62 of constant
`amplitude, at prescribed rates and in prescribed direc-
`tions during symbol intervals in accordance with the
`states of present and prior I and Q channel data bits. The
`I(t—2T) and Q(t—2T) signals essentially tell where the
`phasor was at the end of a symbol interval, and the I(t)
`and Q(t) signals essentially tell where the phasor is to
`move during the subsequent symbol interval T. The
`phasor may move :45“ from any n45“ point, where n is
`an integer,
`in FIG. 5. The phasor may move :90“,
`however, only from m45° points, where m is an even
`numbered integer (i.e., at 0°, :90, and 180°). Con-
`versely, the phasor may stay at rest throughout a sym-
`bol interval only when the phasor is at p45”, where p is
`an odd numbered integer (i.e., at :45" and i135°).
`This means that at the start of any symbol interval only
`two things can happen during that symbol interval: the
`phasor can stay at rest or move 45°; alternatively, the
`phasor can move 45" or 90".
`In an embodiment of this invention that was built and
`
`operated the phasor moved at a constant rate during
`each symbol interval. The rules for specifying the direc-
`tion and rate of phase change during each symbol inter-
`val are described more fully hereinafter. These rules
`and the allowable phase changes are tabulated in FIG. 4
`as a function of the baud clock and current and past data
`bits in the I and Q channels.
`In order to accomplish any required phase change
`during a symbol interval, each of the ROMS is divided
`into 32 different blocks of memory (see FIG. 7). This
`
`BRIEF DESCRIPTION OF DRAWINGS
`
`FIG. 1 is a block diagram of a preferred embodiment
`for practicing this invention;
`FIG. 2 is waveforms for a baud clock signal 38, a
`serial binary input data stream 10, and I and Q bit
`streams 14 and 16 that are derived from the input data
`stream;
`FIG. 3 is eye patterns appearing on lines 27 and 28 of
`the I and Q channels, the heavy lines therein corre-
`sponding to associated signals for the input data signal
`10 in FIG. 1;
`FIG. 4 is a tabulation of the code rules and associated
`phase changes for one embodiment of ‘this' invention;
`FIG. 5 is..a vector diagram illustrating how the ampli-
`tude or end point of a modulated carrier vector signal or
`phasor on line 30 moves along a circle 62, which is a
`constant envelope or amplitude path, as a function of
`the input data 10 in FIG. 2;
`FIG. 6 is a phase diagram illustrating in more detail
`how the vector sum of the I and Q channel signals on
`lines 27 and 28 maintain a substantially constant en-
`velope/amplitude as the phasor 30 moves in accordance
`with the coding rules of this invention;
`FIG. 7 is a listing of the memory locations in memory
`blocks of the ROMS;
`FIG. 8 is a phasor diagram illustrating phase angle
`change.
`FIG. 9 is a graphic representation of an ideal analog
`signal 27 that is required on line 27 for a perfectly con-
`stant amplitude phasor signal 30;
`FIG. 10 is a graphic representation of the correspond-
`ing analog voltage 27 for the digital system in FIG. 1;
`and
`FIG. 11 is a tabulation of the contents of memory
`blocks B17 of ROMS 21 and 22 for a phase shift of +4S°
`from +270° to +315°.
`
`DESCRIPTION OF PREFERRED
`EMBODIMENTS
`
`Referring now to FIG. 1, a QPSK (quadrature-phase
`shift keying) modulator embodying this invention com-
`prises a serial to parallel converter 12, a pair of shift
`registers 15 and 17, a pair of read-only memories
`(ROM) 21 and 22, a pair of digital to analog converters
`25 and 26, and a quadrant modulator 29. The converter
`12 receives an input data signal 10 from a data source
`(not shown) which also provides synchronous data
`clock pulses and clock timing pulses on lines 31 and 32.
`A clock means 33 is responsive to clock pulses on line
`31 for producing baud clock pulses (see FIG. 2, wave-
`form 38) having a repetition rate that is one-half that of
`the data clock pulses. An example of an input waveform
`is shown in FIG. 2, waveform 10. This data signal 10
`may be differentially encoded prior to converter 12 or
`such encoding may be provided in the converter 12. In
`the following description, however, the data signal 10 is
`an unencoded binary data signal for simplification of
`illustration.
`
`The converter 12 is a conventional serial to parallel
`converter which operates in a conventional manner for
`separating alternate bits in the input data stream into
`in-phase (I) and quadrature-phase (Q) data streams on
`lines 14 and 16 (see FIG. 2, waveforms 14 and 16). This
`operation causes the data signals 14 and 16 in the I and
`Q channels to be offset from each other by one bit inter-
`val T. More specifically, converter 12 directs odd num-
`bered bits D1, D3, etc. into the I data stream 14 and
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`4O
`
`45
`
`50
`
`55
`
`60
`
`65
`
`Page 10 of14
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`Page 10 of 14
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`

`

`5
`corresponds to the number of different addresses that
`are defined by the five input signals to the ROMS (i.e.,
`the baud clock and the present and past I and Q channel
`bits). Stated differently,
`there are 16 possible phase
`changes when the Q channel is most recently updated
`and 16 more for when the I channel is most recently
`updated. Thus, a block of ROM is used for each combi-
`nation of input data, with each new I or Q-data bit
`causing a jump to a new memory block.
`Considering the operation at an arbitrary time t6 in
`FIG. 2 where the Q channel is most recently updated
`(i.e., the baud clock is low) then BC=O, Q(t)=D6,
`Q(t—2T)=D4, I(t)=D5, and I(t—2T)=D3.
`In order to treat data in the proper sequence D3, D4,
`D5, D6, the system must treat the channel bits as fol-
`lows: I(t-—2T), Q(t—ZT), I(t) and Q(t). For the preced-
`ing symbol interval from time t5 in which the I channel
`is most recently updated (i.e., the baud clock is high),
`however, BC: 1, I(t)=DS, I(t—2T)=D3, Q(t)=D4,
`and Q(t—2T)=D2. Thus,
`the correct data sequence
`now is found to be D2, D3, D4, D5. This means that the
`system must treat the I and Q channel bits here in a
`different order at time t5, i.e., Q(t—2T), I(t—2T), Q(t),
`and I(t), than at time t6. The baud clock indicates which
`of the I and Q channels was most recently updated and
`serves to resolve the ambiguity here. The manner in
`which the bits are considered is taken care of in the
`address units of the ROMS and the memory blocks.
`Associated memory blocks in the two ROMs have a
`plurality of memory locations containing digital code
`words that represent voltages for the associated I and Q
`components for moving the signal vector relatively
`smoothly along circle 62 in FIGS. 5 and 6, i.e., from one
`phase position to another phase position that is no more
`than 90° away from the former. These code words
`which are in associated pairs of memory blocks in the
`two ROMS are utilized to specify the amplitudes of the
`outputs from the D/A converters, which define the
`amplitude of the I and Q components, respectively. The
`sum of the I and Q components defines the output phase
`vector of the modulator over the given symbol interval
`(e.g., between times t1—t2, t2—t3, etc.), i.e., the magni-
`tude of the phasor and the rate and direction of its tra-
`jectory during a symbol interval. The counter 35 is
`responsive to clock timing pulses on line 32 during each
`symbol interval for producing a sequence of 5 bit words
`on line 36 which step through the look-up tables of
`addressed memory blocks of the two ROMS (i.e., 32
`possible steps). The clock timing pulses on line 32 are at
`a rate N times faster than the data rate, where N is not
`greater than 32. In a particular embodiment N=24. As
`a result, only 24 of the 32 memory locations in each
`memory block are accessed in this implementation.
`Unused ones of the 32 memory locations are stepped
`over by the clocking. This produces a sequence of mul-
`ti-bit digital words on ROM output lines 23-24. In order
`to move the vector 30 in FIG. 6 at a constant velocity
`between allowable positions there, the difference be-
`tween adjacent code words in a particular block of
`memory is preferably a constant which may be 0.
`The number of bits for the ROM output words on
`lines 23—24 is actually dependent on the desired accu-
`racy of the associated analog voltages on lines 27—28
`and the number of steps or memory locations in'each
`memory block. In a system that was built and operated,
`8 bit words were generated on lines 23-24 and each
`memory block contained only 24 memory locations
`(steps). The digital-to-analogue converters 25—26 used
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`45
`
`50
`
`‘55
`
`60
`
`65
`
`4,613,976
`
`'6
`only the 6 most significant bits of the 8 bit word gener-
`ated by the ROMs 21—22. Although the contents of
`memory locations are repeated in different memory
`blocks, the sequence of code words in each memory
`block is unique. This can be seen by considering the I
`and Q components of the _vector 30 in FIG. 6 as it
`moves about the constant envelop circle 62 there.
`The code words from the ROMS are converted to
`associated analog voltages by circuits 25—26. The con-
`verters 25 and 26 are preferably linear and provide
`outputs which are symmetrical about 0. They can
`readily be specified by a few points or digital words
`from associated memory locations. Three of these
`points are:
`00(H): produces a maximum negative amplitude out-
`put from the converters,
`7E(H): produces a 0 amplitude output from the con-
`verters, and
`FC(H): produces a maximum positive amplitude out-
`put from the- converters (where (H) here designates a
`hexidecimal number). The actual amplitude range of the
`output voltage depends on the particular D/A con-
`verter that is selected and is irrelevant to the modula~
`tion scheme itself. In practice it is about $100 milli-
`volts. The magnitude of the output voltage from the
`converters for an arbitrary hexadecimal (H) number is
`found by inter-polating between the above points. For
`example, if given the hexadecimal number 3F, which is
`exactly halfway between 7B (O amplitude) and 00 (maxi-
`mum negative amplitude), the output voltage of the
`converters would be 0.5 times the maximum negative
`amplitude.
`.
`The I channel signal i(t) for a fully analog system and
`a digital system having an infinite number of digital
`steps or words defining the phase trajectory is smooth
`as is shown in FIG. 9. In a digital system, however, the
`corresponding signal i’(n), for n=O——N, has a granular-
`ity defined by the number N of steps or digital words
`used to traverse the trajectory (see FIG. 10). In an
`embodiment of this invention that was built and success-
`fully operated, each memory block contained 24 dis-
`tinct memory locations. There was no significant mea-
`surable noise or adjacent channel symbol interference in
`this structure.
`‘
`The pair of quadrature-phase signals from converters
`25—26 are combined with a pair of quadrature-phase
`sinusoidal carrier signals in product modulators 55—56
`of the quadrature modulator 29. The product signals are
`summed in a combining circuit 59 .for producing the
`sinusoidal phase modulated carrier signal or phasor 30
`of the form sin (wct+¢(t)) on line 30.
`-
`In order to move the vector 30 in FIG. 6 at a constant
`velocity between allowable positions there, one and
`other of the I and Q components 72 and 74 must in-
`crease and decrease at prescribed rates. By way of ex-
`ample, the code words in blocks B17 (Row 17 of FIG.
`4) of the ROMS 21 and 22 and associated analog volt-
`ages from converters 25—26 for moving the phasor
`+45° from +270° to +315° are shown in FIG. 11. The
`code words in the memory blocks B10 (Row 10 of FIG.
`4) for moving the phasor —45° from +351° to +270°
`are switched and are the reverse of (i.e., occur in the
`opposite order to) those in FIG. 11.
`information
`the
`Referring now to FIG.
`11,
`Q(t—2T)=O, Q(t)=0, I(t—2T)=O, I(t)=l, and baud
`clock=0 selects blocks B17 of memory in the ROMs.
`Column 1 in FIG. 11 represents digital words (in hex-
`idecimal)
`from counter 35 which step the ROMS
`
`Page 11 of 14
`
`Page 11 of 14
`
`

`

`4,613,976
`
`8
`-continued
`6. Allowable phase changes within a symbol
`interval T are:
`Ad)
`0“
`
`:45”
`:90"
`
`FROM
`p45°, where p = 1,3,5,7
`(45°, 135°, 225°,3l5“)
`. 8
`n45“, where n = 0,1, .
`.
`m45°, where m = 0,2,4,6
`(0°, 90°, l80°, 270°)
`
`The operation of the modulator in FIG. 1 will now be
`described for the input data signal 10 in FIG. 2 in accor-
`dance with these rules. First consider a time interval in
`
`which binary data is unchanging in both of the I and Q
`bit streams for a period of several bits. Such a situation
`_is represented at the beginning of the data stream in
`FIG. 2, prior to the time t2 there. The data in each of
`the I and Q bit streams then, for both the present and
`immediate past bits, is O. In accordance with rule 3, row
`1, the phasor will remain stationary at one of the rest
`points, e. g., (0,0) at +225° in FIG. 5 (rows 1-2 of FIG.
`4). Thus; the phasor is at + 225° at time t2 and at time t3
`(one bit interval later) as represented by the boxed nu—
`merals 2 and 3 in FIG. 5.
`
`In the next bit period, the odd numbered bit D3 goes
`high at time t3 for updating the I channel while the
`signal level in the Q channel is held low. Consideration
`of the I and Q-data signals at this time reveals that I(t-
`);&I(t—2T) now, i.e., between times t3—t4 and t1-t2,
`respectively, but that Q(t)=Q(t——2T)=0. This means
`that there is a 45° change in the phase of the phasor in
`accordance with rule 3, row 3. And since the I channel
`is most
`recently
`updated
`at
`t3
`and
`now
`I(t—2T)=Q(t)=0, the phasor is rotated in the counter-
`clockwise direction from its rest position in accordance
`with rule 4(a), row 2. This is shown in FIG. 5 as the
`arrow 64 drawn from position 3 to position 4, i.e., from
`225° to 270° (row 17 of FIG. 4).
`For the next data bit D4 starting at time t4, it will be
`noted that this data bit is again low during updating of
`bit Q2 for the Q channel so that now I(t—2T)#I(t)
`whereas Q(t—2T)=Q(t)=0. This again specifies a 45°
`phase change in accordance with row 3 of rule 3. And
`since BC=O and I(t)¢Q(t—2T) for D4, then the phasor
`is again rotated 45° counterclockwise in accordance
`with row 1 of rule 4(b) (row 17 of FIG. 4). This is repre-
`sented in FIG. 5 by the arrow 65.
`During the next two data bits D5 and D6 between
`times t5 and t7, the contents of the I and Q-data chan-
`nels are unchanged so that the phasor remains at the
`previously established rest point (1,0) in FIG. 5 which
`was previously established by the movement to position
`5 (rows 25 and 26 of FIG. 4). During the next data bit
`D7, however, only the I channel changes state. This
`causes a 45° phase change in accordance with row 3 of
`rule 3. But in this instance the phasor rotates in the
`clockwise direction as specified by row 1 of rule 4(a)
`(row 10 of FIG. 4). The phasor therefore moves from
`position 7 to position 8 in FIG. 5.
`Since the next data bit D8 is even numbered, the Q
`channel is updated and changes state. In this instance,
`however, I(t—2T);/:I(t) and Q(t—2T)7&Q(t). This con-
`dition calls for a maximum phase change of 2W=90° in
`accordance with row 4 of rule 3, with the trajectory or
`rotation of the phase vector being clockwise in accor-
`dance with row 2 of rule 4(b) (row 13 of FIG. 4). This
`is represented by the arrow 67 in FIG. 5. This phase
`shift of —9O°=7r/2 radians is the maximum phase shift
`
`7
`through the contents of memory blocks B17. Columns 2
`and 4 represent the contents of prescribed memory
`locations within memory blocks B17, for the I and Q
`channels, and columns 3 and 5 represent the amplitudes
`of corresponding analog signals from converters 25—26.
`Column 6 represents the phase of the resultant signal
`vector 30 in FIG. 6 for these contents of the associated
`memory locations.
`It can be determined that the phase angle progresses
`uniformly from +270° to +315° as desired. Although
`the data in FIG. 11 includes some round-off errors,
`these would not necessarily occur in practice where a
`larger number of digits are employed. Also, there ap-
`pears some granularity in the output voltages of the
`converters as is expected from a finite number of sam-
`ples.
`In accordance with another aspect of this invention,
`the phase of the signal vector or phasor 30 is dictated by
`the input data according to the following unique set of
`rules which data in the ROMS satisfy:
`1. The phase of the modulated signal vector or phasor
`30 is continuous.
`2. The phase trajectory of the vector is determined by
`the baud clock and present and prior bit values in the
`two channels.
`3. The rate of change of phase is determined as fol-
`lows:
`
`|w|
`Q(t) = Q(t — 2T)
`I(t) = I(t — 2T)
`0
`yes
`yes
`W
`no
`yes
`no
`yes
`W
`no
`no
`2W
`
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`where, w is the phase volocity or rate of change of
`phase, W and 2W are constant phase velocities that will
`rotate the phasor 30 a total of 7r/4 and 17/2 radians in
`one bit time T, and I(t—2T) in waveform 14 is between
`'t6 and t7 for a current I(t) between t8 and t9.
`4. The direction of rotation of the phasor 30 depends
`on whether the I or Q-data stream was most recently
`updated, i.e., whether the present time t is associated
`with an odd or even numbered data bit in the input data
`stream, where each channel
`is updated during each
`baud time interval of 2T and the two channel signals are
`offset from each other by one bit time T. By way of
`example, the Q channel signal is most recently updated
`between times t4 and t5 when BC=O in FIG. 2. In
`c