`
`®
`MOST
`
`Media Oriented Systems Transport
`
`Multimedia and Control
`Networking Technology
`
`OS8104
`Preliminary Product Data Sheet
`
`DS8104PP2
`
`Sept. 2000
`
` Copyright 1997-2000 Oasis SiliconSystems AG
`
`(cid:211)
`

`

`OS8104
`Ordering Information
`OS8104gpR
`
`
`
`R - Tape and Reel (optional)
`p - Package:
`S - SOIC
`Q - QFP
`P - SSOP
`L - PLCC
`g - Grade (temperature, supply, etc.)
`
`D - DIP
`U - Die
`
`Base Part Number
`
`Valid Part Numbers:
`
`Order Number
`
`OS8104AQ
`OS8104AQR
`
`Grade
`
`Temperature
`-40 to +85° C
`-40 to +85° C
`
`Supply
`4.5 to 5.5 V
`4.5 to 5.5 V
`
`Package
`
`44-pin TQFP
`44-pin TQFP, Tape and Reel
`
`This table represents parts that were available at the time of printing and may not represent parts that
`are currently available. For the latest list of valid ordering numbers for this product, please contact your
`local sales office.
`
`Support and Further Information
`For more information on the MOST technology, product line, and custom IC development using MOST
`tools, contact one of our offices below.
`
`Oasis SiliconSystems AG
`1101 S. Capital of Texas Highway
`Building B, Suite 101
`Austin, Texas 78746 USA
`
`Oasis SiliconSystems AG
`Bannwaldallee 48
`D-76185 Karlsruhe
`Germany
`
`(+1) 512 306-8450
`Tel:
`Fax: (+1) 512 306-8442
`america@oasis.com
`
`(+49) (0) 721 6 25 37 - 0
`Tel:
`Fax: (+49) (0) 721 6 25 37 - 119
`europe@oasis.de
`
`Oasis SiliconSystems AG
`4-16 Oomaru Tsuzuki-ku
`Yokohama 224-0061, Japan
`
`(+81) (90) 2757 1419
`Tel:
`Fax: (+81) (45) 941 7818
`pacrim@oasis.de
`
`Technical Support
`For technical support please refer to one of the following email addresses:
`support@oasis.de
`support@oasis.com
`
`Preliminary Product Data Sheet
`Page 2
`
` Copyright 1997-2000 Oasis SiliconSystems AG
`
`DS8104PP2
`
`(cid:211)
`

`

`OS8104
`
`
`
`Intellectual Property
`Duplication of this document without permission is prohibited. All rights reserved. The information within
`this document is confidential and Oasis SiliconSystems intellectual property.
`
`Trademarks
`MOST is a registered trademark of Oasis SiliconSystems. All other trademarks used in this document
`are the property of their respective owners.
`
`Patents
`There are a number of patents and patents pending on the MOST technology. The rights to these patents
`are not granted without any specific Agreement between the users and the patent owners.
`
`Preliminary Product Data Sheet
`A Preliminary Product Data Sheet describes a product which is in limited production and subject to
`change. Oasis SiliconSystems has worked diligently to ensure that the information in this document is
`accurate and reliable. However, the information in this document is subject to change without notice and
`is provided "as is" without warranty of any kind (expressed or implied).
`
`Preliminary Product Data Sheet
`
` Copyright 1997-2000 Oasis SiliconSystems AG
`
`DS8104PP2
`Page 3
`
`(cid:211)
`

`

`OS8104
`Conventions
`Within this manual, the following abbreviations and symbols are used for improving readability:
`
`
`
`PIN
`BIT
`x..y
`[a,b,c]
`0xzz
`bREG
`wREG
`mREG
`rsvd
`/
`x
`
`
`
`Comment
`
`Name of a PIN
`Name of a single bit within a register
`Range from x to y. Used as abbreviation e.g. for a group of bits like D7..0
`List of alternative elements to choose from.
`Hexadecimal number (value zz)
`Single-byte (8-bit) register
`Single-word register (16-bit)
`Multi-byte register (e.g. message buffer)
`The respective bit or register is reserved for future use
`Inverter. Attached pin or bit uses inverted logic (low or 0 active)
`Don’t care
`Rising edge
`Falling edge
`
`Revision History
`
`Revision
`1.1
`2
`
`Date
`
`Initial Data Sheet
`Sept. 2000 Fully revised.
`
`Description
`
`Preliminary Product Data Sheet
`Page 4
`
` Copyright 1997-2000 Oasis SiliconSystems AG
`
`DS8104PP2
`
`(cid:211)
`

`

`OS8104
`
`
`TABLE OF CONTENTS
`
`LIST OF FIGURES...........................................................................................................................10
`
`LIST OF TABLES ............................................................................................................................12
`
`1
`
`INTRODUCTION........................................................................................................................17
`
`2 GENERAL OVERVIEW ..............................................................................................................17
`2.1
`Functional Description .............................................................................................................17
`2.2 Network Interface & Compatibility............................................................................................18
`2.3 On-Chip Network Management................................................................................................18
`2.3.1 Channel Allocation ............................................................................................................19
`2.3.2 Physical Position Sensing..................................................................................................19
`2.3.3 Network Delay Detection ...................................................................................................20
`2.3.4 Node Alive Supervision .....................................................................................................20
`2.4 On-Chip Power Management...................................................................................................20
`2.4.1
`Low-Power Mode...............................................................................................................20
`2.4.2
`Zero Power Mode..............................................................................................................20
`2.5 Data Transfer Methods ............................................................................................................20
`2.5.1 Bandwidth .........................................................................................................................21
`2.5.1.1 Control Messaging.....................................................................................................................21
`2.5.1.2 Synchronous (Stream) Data ......................................................................................................22
`2.5.1.3 Asynchronous (Packet) Data .....................................................................................................23
`2.6 MOSTNetServices API ............................................................................................................24
`3 MAIN FUNCTIONAL BLOCKS...................................................................................................25
`
`4 OS8104 CONFIGURATION........................................................................................................27
`
`5 CONTROL PORT IN SERIAL MODE.........................................................................................29
`I2C Mode .................................................................................................................................29
`5.1
`5.1.1 Writing To Control Port......................................................................................................30
`5.1.2 Reading From Control Port................................................................................................31
`5.2 SPI Mode ................................................................................................................................32
`5.2.1 Writing To Control Port......................................................................................................32
`5.2.2 Reading From Control Port................................................................................................32
`6 NETWORK INTERFACE............................................................................................................33
`6.1 MOST Frame Structure ...........................................................................................................33
`6.2 Network Configuration .............................................................................................................34
`6.2.1
`bXCR (Transceiver Control Register) ................................................................................35
`6.2.2
`bXSR (Transceiver Status Register) ..................................................................................36
`6.2.3
`bXSR2 (Transceiver Status Register 2) .............................................................................36
`6.2.4 Capturing Error Events......................................................................................................37
`6.2.5
`bSBC (Synchronous Bandwidth Control register)...............................................................37
`6.2.6
`bNDR (Node Delay Register).............................................................................................39
`6.2.7
`bNPR (Node Position Register) .........................................................................................39
`6.2.8
`bMPR (Maximum Position Register)..................................................................................39
`6.2.9
`bMDR (Maximum Delay Register) .....................................................................................40
`6.2.10 Network Registers After Lock ............................................................................................40
`7 SOURCE DATA PORTS IN SERIAL MODE ..............................................................................41
`7.1 General Description.................................................................................................................41
`7.1.1 Source Data Port Registers ...............................................................................................41
`
`Preliminary Product Data Sheet
`
` Copyright 1997-2000 Oasis SiliconSystems AG
`
`DS8104PP2
`Page 5
`
`(cid:211)
`

`

`
`OS8104
`7.1.2 Serial Source Port Interface ..............................................................................................41
`7.1.3
`Internal Structure of Serial Source Data Interface..............................................................42
`7.1.4 S/PDIF (IEC 60958-3) Data Transport ...............................................................................43
`7.1.5
`Transparent Data Transport...............................................................................................43
`7.2 Source Data Port Configuration (Serial)...................................................................................44
`7.2.1
`bSDC1 (Source Data Control Register 1)...........................................................................44
`I2S (Philips) Source Data Format ...............................................................................................46
`7.2.1.1
`7.2.1.2 SONY Source Data Format .......................................................................................................46
`7.2.1.3 Matsushita Source Data Format ................................................................................................47
`7.2.2
`bSDC2 (Source Data Control Register 2)...........................................................................47
`7.2.3
`bSDC3 (Source Data Control Register 3)...........................................................................48
`7.2.4 Serial Source Data Port Modes .........................................................................................49
`7.2.4.1 Mode 1......................................................................................................................................50
`7.2.4.2 Mode 2......................................................................................................................................50
`7.2.4.3 Mode 3......................................................................................................................................51
`7.2.4.4 Mode 4......................................................................................................................................51
`7.2.4.5 Mode 5......................................................................................................................................51
`7.2.4.6 Mode 6......................................................................................................................................52
`7.2.4.7 Mode 8......................................................................................................................................52
`7.2.4.8 Mode 9......................................................................................................................................53
`7.2.4.9 Mode 10 ....................................................................................................................................53
`7.2.4.10 Mode 11 ....................................................................................................................................53
`7.2.4.11 Mode 12 ....................................................................................................................................53
`7.2.5 Mode Configuration Register Overview .............................................................................54
`7.2.6 S/PDIF (IEC-60958) ..........................................................................................................55
`7.2.6.1 Synchronizing To S/PDIF...........................................................................................................56
`7.2.6.2 S/PDIF Speed Modes ................................................................................................................56
`7.2.6.3 S/PDIF Data To S/PDIF Data.....................................................................................................57
`7.2.6.4 S/PDIF Data To Non-S/PDIF Data .............................................................................................58
`7.2.6.5 Non-S/PDIF Data To S/PDIF Data .............................................................................................58
`8 PARALLEL ACCESS.................................................................................................................59
`8.1 Control Port in Parallel Mode...................................................................................................60
`8.1.1 Writing CP MAP Data Register..........................................................................................61
`8.1.2 Writing To Control Port......................................................................................................62
`8.1.3 Reading From Control Port................................................................................................63
`8.1.4 Control Port Status Register (bCP)....................................................................................64
`8.1.5 Control Signal Overview....................................................................................................64
`8.2 Source Port (SP) In Parallel Mode...........................................................................................65
`8.2.1 Parallel-Synchronous mode...............................................................................................65
`8.2.1.1 Reading from FIFO....................................................................................................................66
`8.2.1.2 Writing into FIFO.......................................................................................................................67
`8.2.2 Parallel-Asynchronous mode.............................................................................................67
`8.2.2.1 Memory Address Pointer (MAP).................................................................................................68
`8.2.2.2 Writing to FIFO .........................................................................................................................68
`8.2.2.3 Writing MAP..............................................................................................................................69
`8.2.2.4 Writing 8 bytes to the FIFO........................................................................................................70
`8.2.2.5 Writing 1 Byte to the FIFO .........................................................................................................70
`8.2.2.6 Reading 8 Bytes from the FIFO .................................................................................................71
`8.2.3 Reading the Source Port Status Register (bSP).................................................................72
`8.2.4 Source Port Control Signal Overview ................................................................................73
`8.3 Parallel-Combined Mode .........................................................................................................73
`8.3.1 Configuring Parallel-Combined Mode ................................................................................75
`8.3.1.1
`bPCMA (Parallel-Combined Mode Activate register)...................................................................75
`8.3.2 Receiving Source Data......................................................................................................75
`8.3.3 Asynchronous Data Packets..............................................................................................76
`8.3.3.1
`Length.......................................................................................................................................76
`8.3.3.2 Received Async. Status Bytes ...................................................................................................77
`8.3.3.3 Handling Received Data ............................................................................................................79
`
`Preliminary Product Data Sheet
`Page 6
`
` Copyright 1997-2000 Oasis SiliconSystems AG
`
`DS8104PP2
`
`(cid:211)
`

`

`
`OS8104
`8.3.4
`Transmitting Data..............................................................................................................81
`8.3.4.1 Transmit Asynchronous Status Bytes ........................................................................................81
`8.3.4.2 Preparing Packet Data...............................................................................................................82
`8.3.4.3 Multi-Frame Packets and /AINT Handshaking............................................................................86
`8.3.4.4 Priority ......................................................................................................................................88
`8.3.4.5
`Idle SF Intervals ........................................................................................................................88
`9 CLOCK MANAGER....................................................................................................................89
`9.1
`bCM1 (Clock Manager 1 register) ............................................................................................89
`9.2
`bCM2 (Clock Manager 2 register) ............................................................................................90
`9.3 PLL Lock Status ......................................................................................................................91
`9.4 VREF and FLT Pins.................................................................................................................91
`9.5 Crystal Oscillator (XTI/XTO) ....................................................................................................91
`10 POWER MANAGEMENT ...........................................................................................................93
`10.1 Low Power Mode .....................................................................................................................93
`10.1.1 Entering Low Power Mode.................................................................................................93
`10.1.2 Leaving Low Power Mode .................................................................................................94
`10.2 Zero Power Mode ....................................................................................................................94
`10.2.1 Entering Zero Power Mode................................................................................................94
`10.2.2 WAKE_UP and R_TIMER Pins .........................................................................................94
`10.2.3 Leaving Zero-Power Mode ................................................................................................94
`11 HANDLING INTERRUPTS .........................................................................................................95
`11.1 bIE (Interrupt Enable register)..................................................................................................95
`11.2 Power-On Interrupt ..................................................................................................................96
`11.3 Behavior On Multiple Interrupts ...............................................................................................96
`12 ROUTING SYNCHRONOUS DATA............................................................................................97
`12.1 Incoming Network Data to Outgoing Network Data ..................................................................98
`12.2 Serial Source Port Inputs To Network ......................................................................................99
`12.3 Network to Serial Source Port Outputs...................................................................................101
`12.4 Synchronous Parallel Port Data Transfers .............................................................................104
`12.4.1 Synchronous Parallel Data To Network ...........................................................................104
`12.4.2 Network to Synchronous Parallel Data.............................................................................104
`12.5 Transparent Channel Data Routing........................................................................................106
`12.6 RE Address Reference 0xF8 .................................................................................................106
`13 CONTROL MESSAGES...........................................................................................................107
`13.1 Transmit Message Addressing...............................................................................................108
`13.1.1 Node Address (Logical Addressing).................................................................................108
`13.1.2 Node Position Address (Physical Addressing)..................................................................108
`13.1.3 Group Address/Groupcast ...............................................................................................108
`13.1.4 Special Group Address/Broadcast ...................................................................................109
`13.1.5 Address Ranges Vs. Addressing Modes ..........................................................................109
`13.1.6 bNAH, bNAL (Node Address Registers)...........................................................................109
`13.1.7 bGA (Group Address Register)........................................................................................110
`13.2 Controlling Transfer Of MOST Control Messages ..................................................................110
`13.2.1 bMSGC (Message Control Register)................................................................................110
`13.2.2 bMSGS (Message Status Register) .................................................................................111
`13.2.3 bXTS (Transmit Status Register) .....................................................................................112
`13.2.4 bXRTY (Transmit Retry Register) ....................................................................................112
`13.2.5 bXTIM (Transmit Retry Time Register) ............................................................................112
`13.2.6 mRCMB (Receive Control Message Buffer) ....................................................................113
`13.2.7 mXCMB (Transmit Control Message Buffer)....................................................................114
`13.3 Control Message Reception...................................................................................................115
`13.4 Control Message Transmission..............................................................................................116
`
`Preliminary Product Data Sheet
`
` Copyright 1997-2000 Oasis SiliconSystems AG
`
`DS8104PP2
`Page 7
`
`(cid:211)
`

`

`
`OS8104
`13.5 Message Types (Encoding And Description)..........................................................................117
`13.5.1 Received Control Message Types ...................................................................................117
`13.5.2 Transmit Message Types ................................................................................................118
`13.5.2.1 Normal Messages (Code 0x00)................................................................................................118
`13.5.2.2 Remote Read Message (Code 0x01)........................................................................................119
`13.5.2.3 Remote Write Message (Code 0x02) .......................................................................................119
`13.5.2.4 Resource Allocate Message (Code 0x03).................................................................................120
`13.5.2.5 Resource De-Allocate message (Code 0x04) ...........................................................................123
`13.5.2.6 Remote GetSource Message (Code 0x05) ...............................................................................124
`14 RESOURCE ADMINISTRATION..............................................................................................125
`14.1 mCRA (Channel Resource Allocation Table) .........................................................................125
`14.1.1 mCRA in Slave Nodes.....................................................................................................126
`14.1.2 mCRA in the Timing-Master ............................................................................................126
`14.2 Allocating Network Resources ...............................................................................................126
`14.3 De-Allocating Network Resources..........................................................................................128
`15 PACKET DATA TRANSFER....................................................................................................129
`15.1 Packet Transfer Registers .....................................................................................................129
`15.1.1 Address Registers ...........................................................................................................129
`15.1.1.1 bAPAH (Alternate Packet Address High Register) ....................................................................129
`15.1.1.2 bAPAL (Alternate Packet Address Low Register)......................................................................130
`15.1.2 bPLDT (Packet Transmit Length Register) ......................................................................130
`15.1.3 bPPI (Packet Priority Register)........................................................................................130
`15.1.4 bPCTC (Packet Control Register)....................................................................................131
`15.1.5 bPSTX (Packet Start Tx Register) ...................................................................................131
`15.1.6 bPCTS (Packet Status Register) .....................................................................................132
`15.1.7 mARP (Asynchronous Receive Packet Buffer) ................................................................132
`15.1.8 mAXP (Asynchronous Transmit Packet Buffer)................................................................133
`15.2 Asynchronous Interrupt Pin /AINT..........................................................................................133
`15.3 Packet Data Handling............................................................................................................134
`15.3.1 Preparing Packet Data For Transmission ........................................................................134
`15.3.2 Interrupt-Based Packet Data Handling.............................................................................135
`15.3.3 Packet Data Handling Based On Polling..........................................................................136
`16 OS8104 STARTUP...................................................................................................................137
`16.1 Set Up After Power Up Reset ................................................................................................138
`16.2 Master Mode .........................................................................................................................139
`16.3 Slave Mode ...........................................................................................................................140
`16.4 Version Number.....................................................................................................................140
`17 STAND-ALONE MODE ............................................................................................................141
`17.1 Entering Stand-Alone mode...................................................................................................141
`17.2 Registers ...............................................................................................................................141
`17.3 mSIMB (Stand-Alone Control Port Messaging Buffer)............................................................142
`17.4 Writing to External Peripheral................................................................................................143
`17.5 Reading from External Peripheral..........................................................................................145
`17.6 Message On Interrupt ............................................................................................................147
`18 ELECTRICAL CHARACTERISTICS ........................................................................................149
`18.1 Absolute Maximum Ratings ...................................................................................................149
`18.2 Guaranteed Operating Conditions..........................................................................................149
`18.3 DC Characteristics.................................................................................................................150
`18.4 Switching Characteristics.......................................................................................................151
`18.4.1 Clocks and Reset ............................................................................................................151
`18.4.2 Parallel Interface .............................................................................................................153
`18.4.3 Source Data Ports (Serial) External Clocking ..................................................................155
`
`Preliminary Product Data Sheet
`Page 8
`
` Copyright 1997-2000 Oasis SiliconSystems AG
`
`DS8104PP2
`
`(cid:211)
`

`

`
`OS8104
`18.4.4 Source Data Ports (Serial) Internal Clocking....................................................................156
`18.4.5 Control Port In SPI Mode.................................................................................................157
`18.4.6 Control Port In I2C Mode .................................................................................................158
`19 PACKAGING AND PINOUT .....................................................................................................159
`19.1 Pinout List .............................................................................................................................159
`19.2 State Of Pins in Low Power/Zero Power Mode.......................................................................160
`19.3 State Of Pins During Reset....................................................................................................162
`19.4 Equivalent Schematics For Pins ............................................................................................163
`19.4.1 Analog Pin (A)..........................................