United States Patent r191
`Koenck et al.
`
`[ti] Patent Number:
`[45] Date of Patent:
`
`4,709,202
`*Nov. 24, 1987
`
`[54] BATIERY PO明1ERED SYSTEM
`
`[75]
`
`Inventors: Steven E. Koenck; David C. Hacker,
`both of Cedar Rapids, Iowa
`
`[73] Assignee: Norand Corporation, Cedar Rapids,
`Iowa
`
`[ *] Notice:
`
`The portion of the term of this patent
`subsequent to Jun. 19, 2001 has been
`disclaimed.
`
`[21] Appl. No.: 876,194
`
`[22] Filed:
`
`Jun. 19, 1986
`
`Related U.S. Application Data
`[60] Division 。f Ser. No. 797,235, Nov. 12, 1985, which is a
`continuation-in-part of Ser. No. 612,588, May 21, 1984,
`Pat. No. 4,553,081, which is a continuation-in-part of
`Ser. No. 385,830, Jun. 7, 1982, Pat. No. 4,455,523.
`
`Int. Cl.4 …·…....................….................. H02J 7/00
`[51]
`[52] U.S. Cl. …··町……........…··……....... 320／，咽； 320/35;
`320/39; 320/48; 340/636
`[58] Field of Search ................... 320/2, 35, 39, 43, 48;
`340/636
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`3,771,132 11/1973 B1ewer ....”.......………........ 340/365
`3,823,388 7/1974 Chadima et al. ……….........” 340/365
`4,001,550 1/1977 Schatz .
`4,127,803 11/1978 Etienne ......”…·……….............. 320/2
`4,140,957 2/1979 Rapp …··…-……………·”.. 320/2
`4,203,103 5/1980 Osada .....…“…………··……... 340/636
`4,277,837 7/1981 Stuckert .......…........…·… 364月∞
`4,308,492 12/1981 Mori ...................“………........ 320/35
`4,455,523 6/1984 Koenck ..................…........ 320/48
`4,553,081 11/1985 Koenck ....…”…………··…..... 320/39
`
`OTHER PUBLICATIONS
`Norand Corporation Specification Sheet for Norand
`101-XL Portable Data System (two sides), 1978.
`Norand Corporation Brochure re Norand “ Sprint 100”
`Portable Order Entry Terminal (Four Sides), 1979.
`Norand Corporation Specification Sheet for Norand
`IOIXL “ Alpha-1 ” Portable Data System (two sides),
`1980.
`Primary Examiner-Patrick R. Salce
`Assistant Examiner-Anita M. Ault
`Attorney, Agent, or Firm-Neuman, Williams, Anderson
`& Olson
`ABSTRACT
`(57]
`In an exemplary embodiment, a battery conditioning
`system monitors battery conditioning and includes a
`memory for storing data based thereon; for example,
`data may be stored representative of available battery
`capacity as measured during a deep discharge cycle.
`With a microprocessor monitoring battery operation of
`a portable unit, a measure of remaining battery capacity
`can be calculated and displayed. Where the micro(cid:173)
`processor is permanently secured to the battery so as to
`receive operating power therefrom during storage and
`handling, the performance of a given battery in actual
`use can be accurately judged since the battery system
`can itself maintain a count of accumulated hours of use
`and other relevant parameters. Where an embodiment
`includes a main battery and a backup battery, the volt(cid:173)
`age of each may be individually measured, and each
`may be conditioned. Battery capacity of each may be
`measured. In a unique low voltage sensing circuit appli(cid:173)
`cable to power sources generally, an automatic voltage
`regulator may itself sense a low power condition with(cid:173)
`out requiring additional precision components. As an
`example only, such detected low power condition may
`be utilized to effect switch over to a backup battery or
`other auxiliary power supply.
`
`80 Claims, 19 Drawing Figures
`
`Apple v. Uniloc
`
`Page 1 of 56
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`

`

`U.S. Patent Nov. 24, 1987
`
`Sheet 1 of14 4,709,202
`
`FIG. I
`
`FIG.3
`
`22
`
`22
`
`17
`
`FIG. 2
`
`［二：二二；二：二］
`
`Apple v. Uniloc
`
`Page 2 of 56
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`

`

`U.S. Patent Nov. 24, 1987
`
`Sheet 2of14 4, 709,202
`
`RLJ
`
`一－一－－一一一一－－一－－，
`103
`
`LEA
`-+
`一C
`1
`
`一盹们
`
`nDTIM川 FL
`
`102 I BATTERY
`
`I B盯TERY
`I CHARGING
`J VOLTAGE
`CHARGING
`CONTROLLER! MONITOR
`
`104
`
`:
`
`20
`
`RECHARGE(cid:173)
`ABLE
`BATTERY
`V+ I MEANS
`
`BATTERY
`VOLTAGE
`MONITOR
`BATTERY
`CUR RE 问 T
`MONITOR
`BATTERY
`TEMPERATURE
`MONITOR
`pHm
`DUU
`fGI
`nu
`--···
`
`引电
`
`川JAmnun
`M巨响川B
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`rk
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`lIll －Ili－－』FIll －－－ rl｜ llIll－
`
`「I
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`t
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`－－－
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`－－ l」
`一一收wm
`一一州 bu
`－－丑 na阳
`一－h门 mu
`
`F3
`
`72
`
`TERMINAL
`PROCESSOR
`ANO MEMORY
`CIRCUITS
`
`－－－－
`
`｜一
`
`f
`
`-
`-
`
`－
`
`J 勺一 5
`
`474
`
`VOLTAGE
`REGULATOR
`AND RESET
`
`82
`
`I 51
`41七
`I 42
`I
`43 ’ 44
`I
`81
`I I DIGITAL
`I
`I INTERFACE
`
`I 104
`
`Ai
`
`a·,E-
`
`d-
`
`
`
`BATTERY
`PROCESSOR,
`TIMING AND
`MEMORY
`CIRCUITS
`
`102
`
`I RESET
`
`L一一一
`
`FIG. 5
`
`－－－－－－－－－－－－－－－－－－－－－－寸－－－－－－－－－－－－－－－－－－
`' BATTERY PACK AND
`\ ASSOCIATED
`'MONITORING AND
`CONDITIONING
`CIRCUITRY
`
`一一＿＿＿ J
`
`Apple v. Uniloc
`
`Page 3 of 56
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`

`

`U.S. Patent No飞 24, 1987
`
`Sheet3of14 4,709,202
`
`FIG.6
`
`UNACCEPTABLE OVERCHARGE
`RATE
`
`ACCEPTABLE
`OVERCHARGE RATE
`
`15
`
`35
`
`55
`75
`TEMP. 。 R
`
`95
`
`115
`
`FIG.7
`
`YCLE N0.5
`CYCLE N0.100
`CYCLE NO. 500
`
`TIME, HOURS
`
`FIG .8
`
`·122
`123
`
`二二~24
`一
`
`飞
`
`1
`
`20
`
`40
`
`100
`80
`60
`RATED CAPACITY %
`
`120
`
`CHARGE
`RATE
`C/5
`
`C/6.7
`
`C/10
`
`C应。
`
`VOLTS
`1.3
`
`1.2
`
`1 . a
`
`τ·· 1
`
`.0
`
`.9
`
`VOLTS
`1.2
`
`1.0
`
`.8
`.6
`
`Apple v. Uniloc
`
`Page 4 of 56
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`

`

`U.S. Patent Nov. 24, 1987
`
`Sheet4 of14
`
`4,709,202
`
`FIG. 9A
`
`+CHG
`
`DI
`
`V+
`
`VBATT
`
`131
`
`巳5
`
`142
`
`177
`
`163
`
`161
`
`162
`
`137
`
`Apple v. Uniloc
`
`Page 5 of 56
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`

`

`U.S. Pa臼nt Nov. 24, 1987
`
`Sheets of14
`
`4,709,202
`
`V+
`
`FIG. 98
`
`·140
`
`181
`
`PBS
`
`.142
`
`\
`
`在，、
`
`,,,--174
`
`Vee
`
`PA7
`
`OSCI
`
`OSC2
`
`IRQ
`
`PA3
`
`PB7
`
`PB6
`
`PA1
`
`RESIT PB3
`
`PC3
`
`PC2
`
`PC1
`
`1PC0
`Vss
`工
`
`AN3
`
`AN2
`
`AN1
`
`ANφ
`
`R15
`
`用6一（
`
`R17
`
`R18
`
`Apple v. Uniloc
`
`Page 6 of 56
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`

`

`U.S. Patent Nov. 24, 1987
`
`Sheet6 of14 4,709,202
`
`FIG .10
`
`/
`START
`CONVERSION
`
`n=7
`__J
`
`10-1
`
`10-2
`
`10-3
`
`SET 2n{
`BIT=" 1”
`
`.10-4
`
`10-8
`
`10-9
`
`Apple v. Uniloc
`
`Page 7 of 56
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`

`

`U.S. Patent Nov. 24, 1987
`
`Sheet 7 of 14
`
`4, 709,202
`
`FIG. II
`
`11~
`
`11-4
`
`11-1
`
`11-5
`
`MONITOR BATT.
`P础.AMEπ咫
`l!D巳CHARGE)
`
`11-6
`
`TIMER
`
`将险队ND
`
`11-7
`
`11 『9
`
`11-10
`
`.11 -11
`
`Apple v. Uniloc
`
`Page 8 of 56
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`

`

`U.S. Patent Nov. 24, 1987
`
`Sheets of 14
`
`4,709,202
`
`Fl G. 12
`
`12-24
`
`EJ
`
`『ζ
`
`句F』
`
`－ JE飞’
`
`BATTERY
`CHARGER
`MEANS
`
`12-12 气、
`
`12-14
`
`TERMINAL
`DISPLAY
`CIRCUIT
`
`TERMINAL
`PROCESSOR
`AND MEMORY
`CIRCUITS
`
`也21 飞＼
`
`BATTERY CHARGE AND
`E 、I "---12-18
`DEEP DISCHARGE CONTROLLER AND i
`I 4--12-10
`'
`BATTERY CONDITION
`MONITOR CIRCUITRY
`
`’
`
`，－一一－ 12-22
`
`RECHARGEABLE T、 12-20
`BATTERY MEANS
`
`Apple v. Uniloc
`
`Page 9 of 56
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`

`

`U.S. Patent Nov. 24, 1987
`
`Sheet9of14 4,709,202
`
`FIG. 13
`
`13 」 1
`
`CR1
`
`CHA阳：：；E
`N.L ·CONT同)L
`P3δ
`
`12-21 b
`
`/
`12-21e
`
`DISCHARGE
`P3·4
`
`12f,,
`
`0
`
`R36
`100K
`5%
`QS 、？七S
`VNOI04N37
`
`OMM
`
`Q7
`2N3904
`
`nvUH医－3
`
`Bn9』
`
`a 、
`
`Apple v. Uniloc
`
`Page 10 of 56
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`

`

`U.S. Patent Nov. 24, 1987
`
`Sheet 10 of14 4,709,202
`
`Fl G. 14
`
`14-2
`
`14-5
`
`R EAO STAR TING
`TIME
`
`I _......14-3
`
`TURN ON
`DISCHA邸E
`
`I .-14-4
`
`READ LB2 TIME
`
`14-6
`
`TURN OFF DISCHARGE
`TURN ON FAST CHA附E
`
`14-7
`
`CALCULATE DEEP
`DISCHARGEπME
`
`14-8
`
`DlSPt.AY BATTERY
`CAPACITY
`(PERCENT Cf
`EIGHT HOUR DEEP
`DISCHARGE TIMfl
`
`14-9
`
`Apple v. Uniloc
`
`Page 11 of 56
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`

`

`己·∞－MvmHBE22·N户 3 ∞叶
`
`mFgH＝。叫王 hfivo喝啤NON
`
`FIG. 15
`
`.1s-20
`
`ROM
`
`KEYBOARD
`
`15-16
`
`ARRAY
`GATE
`
`Apple v. Uniloc
`
`Page 12 of 56
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`Apple Ex. 1005
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`

`

`U.S. Patent Nov. 24, 1987
`
`Sb臼t 12 of14 4,709,202
`
`CHG IN
`
`LP
`
`4
`
`宁li
`
`- .
`
`Cl
`
`R37
`
`- .
`
`RESET
`
`？巳二1
`
`QS
`
`SWITCH Off
`
`- ’
`
`R21
`
`- .
`
`LOW PWR
`
`R56
`
`R33A
`
`+7V REG
`
`R33 日
`
`CHG F
`
`MBATS
`
`i-8 BAT 「
`
`16-3
`
`v+
`
`FIG.16A
`
`MB式r D巴G
`
`BBAT
`OISG
`
`MBATS
`
`Apple v. Uniloc
`
`Page 13 of 56
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`

`

`U.S. Patent
`
`Nov. 24, 1987
`
`Sheet 13 of 14
`
`4,709,202
`
`CHCIN
`
`LP
`
`+
`
`,.7y REG
`
`BBATS
`
`VREf
`
`R40
`
`R358
`
`16-8
`
`句ζ
`
`”。／
`
`，士一·τ中占
`
`z
`
`nF
`
`J7·去
`
`':°J 7-3
`
`J7－气二3
`
`J
`
`P3-2
`1气 k王2- r=-斗）~－王－2!
`
`ι
`
`厂「、公］ 1-3
`
`I
`
`;n 监牢Cl~乱！
`斗－马.~~仁号：1_:
`16-20 〓〓降23
`
`'J7
`
`BAT MUX
`
`Ai'OCLK
`
`FIG. 168
`
`Apple v. Uniloc
`
`Page 14 of 56
`
`Apple Ex. 1005
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`

`

`U.S. Patent No叽 24, 1987
`
`Sheet 14of14 4, 709,202
`
`FIG. 17
`
`17-1
`
`NORMAL OPERATION
`AT 4.65 VOL TS
`
`17乞
`
`READ LP AND
`A/D CONVERTER
`
`17-3
`
`PERFORM POWER
`CONTROL ALGORITHMS
`
`17-4
`
`NO
`
`17-6
`
`SET LOW PWR = I
`POWER SUPPLY= 2.5 VOLTS
`4.19 MHZ XTAL STOPS
`CPU STOPS
`
`17-7
`
`NO
`
`17-8
`
`SET LOW PWR = 0
`POWE.R SUPPLY= 4.65 VOLTS
`4.19 MHZ XTAL STARTS
`CPU RUNS
`
`Apple v. Uniloc
`
`Page 15 of 56
`
`Apple Ex. 1005
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`

`

`1
`
`4,709,202
`
`2
`
`12233445506
`
`L…
`
`…………………………
`
`…盟问……………
`
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`
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`mA…mJ咄m川剧mEm 巾，叩叫mmmr巾MWM阳mMmmmmdwwmmMmmhZUU
`
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`z…一……ι………………………－
`町…………－……
`
`m…
`
`………………川……一………
`
`h……………………………………………臼
`
`Apple v. Uniloc
`
`Page 16 of 56
`
`Apple Ex. 1005
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`

`

`4,709,202
`
`3
`The invention will now be described, by way of ex(cid:173)
`ample and not by way of limitation, with reference to
`the accompanying sheets of drawings; and other ob(cid:173)
`jects, features and advantages of the invention will be
`apparent from this detailed disclosure and from the 5
`appended claims.
`
`……
`
`4
`
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`
`Apple v. Uniloc
`
`Page 17 of 56
`
`Apple Ex. 1005
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`

`

`4,709,202
`
`6
`20, such that the battery means may be stored for long
`periods of time without loss of the data stored in the
`battery memory means. For example, the processor
`circuitry 30 including its associated memory means may
`require only a few percent of the current required by
`the processing system of the portable unit 10. For exam(cid:173)
`ple, a shelf life of from one to two months for the bat(cid:173)
`tery memory means is feasible.
`
`5
`capable of data communication with the central pro(cid:173)
`cessing unit 14 of the device 10. To this end, in the
`illustrated embodiment, as indicated in FIG. 3, the bat(cid:173)
`tery means 20 including the rechargeable battery cells
`carries therewith a printed circuit board 31 having flexi- 5
`ble electrically conductive straps 41 through 46 which
`automatically make firm and reliable electrical contact
`with connector strips such as indicated at 51 of the
`terminal device 10. Two of the conductive straps of the
`Description of FIG. 5
`set 41-46 may be connected with the opposite polarity 10
`FIG. 5 illustrates an overall exemplary circuit dia-
`terminals of the battery means 20 so as to supply battery
`gram for the embodiment of PIGS. 1through4. In FIG.
`voltage to the regulator means of the central processing
`5, reference numeral 71 indicates a terminal processor
`unit 14. The remaining straps of the set 41-46 may serve
`component including central processing unit 14 and
`to provide a communication channel between a battery
`processor unit of the processor circuitry 30 and the 15 associated memory circuits. Component 72 in FIG. 5
`represents terminal display circuits which may be asso-
`central processor unit 14 of the terminal device 10.
`Referring to FIG. 4, the battery pack assembly 18
`ciated with the display screen 12 of FIG. 1. Terminal
`may include an insulating casing part 60 which has an
`connectors such as 51 are also diagrammatically indi-
`aperture at 60a in FIG. 4 for exposing the conductor
`cated and are shown as being electrically connected
`straps 41 through 46 for resilient pressure engagement 20 with the flexible straps 41 through 46, respectively, of
`with respective cooperating terminal connectors such
`the battery pack assembly.
`as indicated at 51 in FIG. 2. As indicated in FIG. 2, the
`In FIG. 5, the battery pack or rechargeable battery
`dimensions of the battery compartment of the device 10
`means is again generally designated by reference nu-
`are closely matched to the dimensions of the battery
`meral 20, and the positive and negative output terminals
`pack assembly 18 so that the battery pack assembly 18 25 of the battery means 20 are indicated as bein~ connected
`can only be fitted within the battery compartment in
`with the terminal processor and memory circuits com-
`such a way that the straps 41 through 46 are in firm
`ponent 71 via electrically conductive straps 45 and 46.
`engagement with the respective terminal connectors
`Reference numeral 81 in FIG. 5 designates a digital
`such as 51.
`interface component which serves for the coupling of
`From FIGS. 2, 3 and 4, it will be understood that the 30 the terminal processor of component 71 with a battery
`processor of component 82 of the battery pack assembly
`processor circuitry 30 including the conductive straps
`41-46 is secured with the battery means 20 for remov-
`18. Simply for the sake of example, communication
`ability from the battery compartment as a unit. Thus the
`between the battery processor of component 82 and the
`battery pack assembly 18 has self-contained processor
`terminal processor of component 71 is indicated as tak-
`circuitry as indicated at 30. As will be explained herein- 35 ing plac坦 via three conductors which include respective
`conductive straps 41 through 43 of the battery pack
`after, this processor circuitry 30 is electrically coupled
`with the battery means 20 so as to receive operating
`assembly 18, FIG. 4. Further details of an exemplary
`power therefrom both while the battery means forms
`digital interface circuit for implementing component 81
`part of the portable system 10 and while the battery
`will be given in relation to a more detailed electric
`means is separate from the portable unit.τnus, even 40 circuit diagram to be described hereinafter. For the sake
`where the processor circuitry 30 is provided with a
`of correlation with the detailed circuit to be later de-
`memory requiring a constant supply of power, data is
`scribed, reference numeral 83 designates a voltage regu-
`not lost from the memory upon removal of the battery
`lator and re臼t circuit. Component 83 serves to supply a
`means from the portable device 10. Still further as will
`regulated operating voltage to the component 82 as
`be hereinafter explained the processor circuitry 30 in- 45 well as to circuits of the digital interface component 81
`eluding its memory may be operable with a battery
`in a specific preferred implementation of the present
`voltage substantially less than that required by the cen-
`invention to be described hereinafter. Component 82 in
`tral processor unit 14, so that data is not lost from the
`such specific example includes a memory which re-
`memory of the processing circuitry of the battery pack
`quires a continuous operating voltage in order to main-
`assembly even where the battery means has been dis- 50 tain a continuous history of the battery means 20. The
`charged so as to have a relatively low output voltage
`reset circuitry of component 83 is a dapted to supply a
`RESET signal which serves to indicate that the memory
`below the minimum required operating voltage for the
`central processing unit 14. In this way, the battery mem-
`means has had its operating voltage interrupted.
`ory means is enabled to retain an operating history of a
`Components 91, 92 and 93 in FIG. 5 represent battery
`particular rechargeable battery pack over the entire life 55 monitoring means operatively coupled with the battery
`of such battery pack, while on the other hand the pro-
`means 20 for the purpose of obtaining quantitative mea-
`cessor circuitry 30 is desig~ed so as to require a mini-
`sures of respective battery parameters. Where the re-
`mum space beyond the outline configuration of the
`spective parameter sensing means of components 91, 92
`rechargeable battery cells themselves. In FIG. 2, it will
`and 93 supply analog signals, digital to analog converter
`be observed that the casing 60 is relatively closely 60 means may be associated with the monitor circuitry for
`the purpose of obtaining the quantitative parameter
`spaced to the periphery of the battery cells such as 21
`and 22 in comparison to the cross sectional dimensions
`measurements in digital form. In a particular preferred
`of such battery cells, and that the processor circuitry 30
`arrangement to be hereafter described in detail, the
`is of a width dimension as viewed in FIG. 2 so as to at
`battery processor of component 82 may supply digital
`least partially fit within a nitch such as indicated at 63 65 reference signals via the line 95, and the digital refer-
`enc坦 value may be converted into a common analog
`between the two sets of battery cells. Still further, such
`processor circuitry 30 is selected so as to provide an
`reference signal for matching with the respective ana-
`essentially minimal power drain on the battery means
`log measurement values of components 91, 92 and 93. In
`
`Apple v. Uniloc
`
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`4,709,202
`
`8
`7
`means is discharged at a predetermined rate until such
`this particular embodiment, comparator circuits may be
`included in components 91, 92 and 93 for comparing the
`time as the battery means 20 exhibits a battery output
`voltage of a predetermined value, for example, four
`respective analog measurement signals with the com-
`volts where components 71 and 72 of the terminal de-
`mon analog reference value in a predetermined order,
`the logical output signals from the comparator means 5 vice require a minimum operating voltage of say 4.5
`volts. By way of example if the battery means has a
`being supplied via lines 9币， 96 and 98 to the processor
`means for signaling when the digitally generated analog
`nominal rated capacity of 2.2 amp hours, the battery
`may be discharged at a rate of 220 milliamperes (battery
`reference signal has reached a level exceeding the ana-
`log measurement value being compared therewith. The
`capacity C divided by ten). In this case a deep discharge
`digital measurement values so determined may be uti- IO cycle would be completed within not more than about
`ten to twelve hours. (See FIG. 8 which represents the
`lized as a basis for updating bat妃ry condition informa-
`tion in the memory of component 82.
`discharge characteristic of one nickel-cadmium cell.)
`A battery charging voltage input is indicated by the
`Charge current is coupled to the battery pack via
`symbol “+CHG”. Battery charging current is supplied
`conductive strap 44 of FIG. 5.
`to the rechargeable battery means 20 via a battery 15
`Description of FIGS. 6 and 7
`charging current path which is controlled by a battery
`By way of background, FIG. 6 is a plot illustrating
`charging controller circuit 101 which may receive a
`maximum charge rate as a function of temperature. It
`digital battery charge control signal via line 102 in FIG.
`will be observed that at relatively low temperatures, the
`5. According to a preferred embodiment to be described
`in detail hereafter, the battery charging current path 20 permissible charging rate is relatively low. Thus a bat-
`tery system adaptable to a wide range of environmental
`further includes a battery current sensing means which
`forms part of component 92. The arrangement is prefer-
`conditions, and yet utilizing a maximum charging rate is
`ably such that the battery current measured by compo-
`achieved when the charging rate can be adjusted ac-
`nent 92 during a charging operation does not include
`cording to quantitative measurement of battery temper-
`any charging current which may be supplied to the 25 ature during the charging cycle.
`terminal device including components 71 and 72 in
`Specifically for the case of a nickel-cadmium battery
`FIG. 5. Thus the battery processor of component 82
`pack overcharging is the point at which the majority of
`during a char~ing operation receives from component
`charge current generates oxygen at the positive elec-
`92 a quantitative measure of actual charging current
`trode rather than increasing the state of charge of the
`supplied to the battery means itself. A battery charging 30 cell. This point occurs at approximately the 75% state
`of charge level. As oxygen is generated, the internal
`voltage monitor 103 is operatively coupled with the
`battery charging voltage input “+ CHG” and is opera-
`pressure of the cell increases, which ultimately deter-
`tive to supply a quantitative measure of battery charg-
`mines the amount of overcharge the cell can withstand.
`ing voltage to the processor circuitry of component 82.
`The maximum allowable rate is a strong function of cell
`For example, in a preferred arrangement, the digital 35 temperature. This is due to the fact that the generated
`reference value supplied by line 95 in FIG. 5 is utilized
`oxygen must re-combine with cadmium at the negative
`periodically to generate an analog reference value for
`electrode to prevent oxygen build-up and hence internal
`comparison with the analog reading of battery charging
`pressure increase. The rate of re-combination is dictated
`voltage of component 103. In this case, a comparator
`by cell temperature due to the viscosity of the electro-
`circuit of component 103 signals via output line 104 40 lyte and the rate of the chemical reaction at the negative
`electrode. If the allowable overcharge rate for a given
`when the analog reference value exceeds the currently
`occurring analog value of the battery charging voltage.
`cell temperature is exceeded, the cell pressure may
`Thus, during a battery charging cycle, the battery pro-
`exceed the pressure relief valve safety level, causing
`cessor of component 82 is supplied with battery operat-
`venting- and potentially expelling electrolyte, which
`ing information from which an optimum battery charg- 45 drastically reduces cell life.
`ing current can be selected. In particular, by sensing
`FIG. 7 illustrates the effect of repetitive shallow cy-
`cling on the output voltage of a given cell of a nickel-
`battery temperature during the battery charging opera-
`tion, it is possible to provide a battery system which is
`cadmium battery pack. Curves 121, 122 and 123 show
`adaptable to operation under a wide range of environ-
`the variation in output voltage over an operating cycle
`mental conditions while yet assuring optimum effi- 50 for respective increasing numbers of shallow operating
`ciency in carrying out a battery T回harging operation.
`cycles. Specifically curve 121 shows the variation in
`For further assuring the optimum conditioning and
`output voltage over time in hours for shallow discharge
`maximum operating life of the battery system, FIG. 5
`cycle number 5, while curve 122 represents the corre-
`illustrates a battery deep discharge controller compo-
`sponding variation at shallow cycle number 100 and
`nent 110 as being electrically connected with the bat- 55 curve 123 shows the result at cycle number 500. Not
`tery means and being controlled by an input line 111 for
`only does repetitive shallow discharge produce a volt-
`effecting a deep discharge conditioning of the battery
`age depression effect as illustrated in FIG. 7, but this
`means 20 at suitable times during the operating life of
`type of operation of the battery pack also causes a grad-
`the battery means. In accordance with the teachings of
`ual and consistent degradation of cell capacity.
`the present invention, during the deep discharge cycle 60
`Description of FIG. 8
`of the battery means, battery current is continuously
`FIG. 8 illustrates the discharge characteristic for a
`measured by the battery current monitoring component
`nickel-cadmium cell. A deep discharge of the cell is
`92 so as to enable the battery processor and memory
`considered to have taken place at region 124 where the
`circuits of component 82 to derive a quantitative mea-
`sure of the available capacity of the battery means. In a 65 output voltage begins to decrease relatively rapidly. A
`deep discharge cycle may be considered to have been
`relatively simple determination of battery capacity, the
`battery means 20 may be first fully charged, and then
`effected when the cell voltage falls to a value of one
`volt, for example. A deep discharge, at a normal rate of
`subject to a deep discharge cycle wherein the battery
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`Apple v. Uniloc
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`

`9
`battery usage, say battery capacity divided by twenty
`(C/20), might require more than twenty hours of porta-
`ble operation without a recharging cycle.
`
`10
`remain, giving a resultant digital to analog voltage
`range of:
`
`4,709,202
`
`5
`
`Description of FIGS. 9A and 9B
`FIGS. 9A and 9B illustrate a more detailed circuit
`implementation in accordance with the block diagram
`of FIG. 5. In FIG. 9A the battery pack is schematically
`indicated at 20 and is shown as h~ving .a precisio~ resis-
`tance element 131 permanently m senes therew由扣r 10
`the purpose of sensing battery current during charging
`and discharging operations. By way of example, ele-
`ment 131 may have a resistance value of one-tenth ohm
`with a precision of one percent. The battery pack 20
`
`255
`ov. ~二 DIA output 三 τiT 忡ef (= 1.497 V)
`
`v,, 号手－ = 5.8 巾
`
`so:
`digital output 0=0 volts
`digital output 255 = 1.497 volts
`With this digital to analog converter as a building
`block a successive approximation analog to digital con(cid:173)
`
`~号：：~：指~E~击：~：~！~i~ IS ~E~jt.~摇摇旦旦嚣苦苦
`
`The successive approximation algorithm depends on
`series is sufficiently high so that only a negligible bat-
`the assumption that the analog voltage being measured
`does not change appreciably during the conversion
`tery current flows in this voltage sensing circuit. A
`battery temperature sensing transducer 134 is shown as 20
`sequence. The nature of the exemplary application in-
`being physically disposed in heat transfer relation to the
`battery pack 20. A precision resistance element 135 is
`herently has characteristics of slowly changing parame-
`shown in series with the transducer l34 for the purpose
`ters with the exception of the discharge current, which
`can change abruptly and significantly. The solution to
`of supplying a voltage representative of battery temper-
`25 this potential difficulty is a low-pass filter amplifier
`ature during a charging operation.
`which serves to integrate or average any rapidly chang-
`For the purpose of sensing charging voltage during a
`ing ~urrent fluctuation干
`battery charging operation, precision resistance ele-
`ments 136 and 137 are illustrated as being c四mected
`Smce the analog to digital converter has a conversion
`with the battery charging voltage input “+ CHG”. The
`range of 0 to 1.497 volts, the four analog signals to be
`resistance values of the voltage divider are selected 30 measured must be scaled appropriately to yield a conve-
`nient step resolution by offering measurability over the
`such that the voltage across resistance element 137 will
`accurately represent the charging voltage during a bat-
`necessary range of values. The scaling values and step
`tery charging operation. Analog to digital converter
`resolutions may be selected as follows:
`means is associated with the respective battery parame-
`1. Channel 0: Charge voltage
`ter sensing elements so as to convert the measurements 35
`step resolution=80 mv
`into digital form. In the particular circuit embodiment
`maximum range: 20.40 volts
`illustrated in FIGS. 9A and 9B, this conversion opera-
`2. Channel 1: Discharge current
`tion is carried out with the use of programmed proces-
`step resolution=2 ma
`sor circuitry 140, FIG. 9B. The processor circuitry 140
`maximum range: 510 ma
`controls an eight-bit R/2R ladder network 141 having 40 3. Channel 2: Battery terminal voltage
`an analog output at 142. The analog output line 142 is
`step resolution= 25 mv
`connected to comparators 151 through 154 shown in
`maximum range: 6.375 volts
`FIG. 9A and supplies a common analog reference volt-
`4. Channel 3: Battery temperature
`age to the non-inverting inputs of these comparators.
`step.resolution=2° K.
`
`The inverting inputs 161 through 1“ of the compara- 45 maximum ra吨e: 509K = 236° C.
`
`Particularly m the case of channel two it might be
`tors 151 through 154 are coupled with the respective
`noted that a four-cell nickel-cadmium battery pack can
`battery parameter sensing circuits. In a specific imple-
`have a terminal voltage that exceeds 6.375 vol饵， which
`mentation, the processing circuitry 140 is implemented
`is the maximum range of channel two. In the present
`with a power supply voltage of three volts which ·may
`be obtained from a very accurate stable voltage refer- 50 example, however, no additional useful information
`would be provided if the battery processor could deter-
`ence supply/amplifier device 150. By utilizing a voltage
`reference as the power source for the processing cir-
`mine when battery voltage exceeded 6.375 volts.
`As previously mentioned, battery discharge current is
`cuitry 140, the output ports associated with the ladder
`network provide an accuracy c。mparable to that of a
`subject to rapid fluctuations. Accordingly, the channel
`conventional digital to analog converter. In the pa时icu- 55 one current monitor means includes an integration cir-
`lar embodiment illustrated there is a ninth bit in the
`cuit as indicated at 170 in FIG. 9A. The integration
`most-significant bit location of the ladder network 141.
`circuit 170 has its input connected with the cuηent
`This is provided so as to adapt the ladder network out-
`sensing resistance element 131 and its output connected
`put at 142 to the input common mode voltage range of
`with input line 163 of comparator 153, FIG. 9A.
`the comparators 151 through 154. Under worst case 60
`Referring to FIG. 9A, an implementation of the bat-
`tery charging controller 101 of FIG. 5 comprises an
`conditions, the battery terminal voltage may reach 4.0
`volts which limits the common mode input voltage to
`analog control line 171 leading to an inverting input of
`2.5 volts, approximately. To achieve eight-bit resolu-
`a comparator 172 which controls a battery charging
`current regulating circuit 173. The battery charging
`tion, the full digital to analog analog voltage range must
`be accommodated by the comparators 151 through 154. 65 current is controlled by the pr。因ssor circuitry 140,
`By configuring the digital to analog converter network
`FIG. 9B, with the use of an additional four bit R/2R
`141 as a nine-bit ladder with the most significant bit a
`ladder network 174. The ladder network 174 supplies an
`logic zero, the lower eight bits of the nine-bit ladder
`analog command signal via line 171 for controlling
`
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`12
`11
`deep discharge cycle, in order that the battery pack can
`components 172 and 173. Thus, the analog command
`maintain its full rated capacity and exhibit maximum
`signal can have one of sixteen discrete voltage levels.
`operating life. A suggested discharge cycle to meet this
`The output voltage range is from zero volts to 15/16
`times the reference voltage level or 2.81 volts, with
`requirement is discharging the battery at a C/lO rate to
`5 a terminal voltage of 4.0 volts for a four-cell configura-
`steps of 187.5 millivolts.
`tion. A discharge control circuit for this purpose is
`An operational amplifier 176, FIG. 9A, is coupled
`indicated at 180 in FIG. 9A, the control input 181 being
`with the battery current sensing resistor 131 and pro-
`controlled from the processor circuitry 140 as indicated
`vides an amplification such that a voltage step of 187.5
`millivolts at input 171 of comparator 172, FIG. 9A, is
`in FIG. 9B.
`matched by a battery current step of thirty-two milliam- 10 A deep discharge of battery pack 20 would not nor-
`peres in resistance element 131. Thus, fo~ a battery
`mally occur in the typical usage contemplated for the
`current in element 131 of thirty-two milliamper＇筒， a
`illustrated embodiment since normally the battery pack
`voltage 以 output line 177 of 187.5 millivolts is supplie~
`and associated portable sy阳n is used less than fourteen
`to the non-inverting input of comparator 172. The mint-
`hours per day, while the design operating time for the
`mum charge current level is theoretically zero; how- 15 battery pack is typically twenty hours. Furthermore,
`ever, finite input offset voltages present in the amplifier