(12) United States Patent
`Casebolt et al.
`
`I lllll llllllll Ill lllll lllll lllll lllll lllll 111111111111111111111111111111111
`US006625790B 1
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 6,625, 790 Bl
`*Sep.23,2003
`
`(54) METHOD AND APPARATUS FOR
`DETECTING THE TYPE OF INTERFACE TO
`WHICH A PERIPHERAL DEVICE IS
`CONNECTED
`
`(75)
`
`Inventors: Mark W. Casebolt, Seattle, WA (US);
`Lord Nigel Featherston, Redmond,
`WA(US)
`
`(73) Assignee: Microsoft Corporation, Redmond, WA
`(US)
`
`5,644,790 A
`5,754,890 A
`5,793,999 A
`5,828,905 A
`5,832,244 A
`5,857,112 A
`5,928,347 A
`5,935,224 A
`6,006,295 A
`6,460,094 Bl
`
`7/1997
`5/1998
`8/1998
`10/1998
`11/1998
`1/1999
`7/1999
`8/1999
`12/1999
`* 10/2002
`
`..................... 395/883
`Li et al.
`Holmdahl et al.
`.......... 395/883
`Mori .......................... 395/309
`Rao
`........................... 395/883
`Jolley et al. ................ 395/309
`Hashemi et al. ............ 395/828
`Jones ......................... 710/129
`Svancarek et al. . . . . . . . . . . . . 710/63
`Jones et al. . . . . . . . . . . . . . . . . . . . 710/62
`Hanson et al. ... ... ... .. ... ... 710/8
`
`FOREIGN PATENT DOCUMENTS
`
`( *) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`EP
`WO
`WO
`
`0 860 781 A2
`WO 97/31386
`WO 97/17214
`
`2/1998
`8/1997
`4/1999
`
`This patent is subject to a terminal dis(cid:173)
`claimer.
`
`(21) Appl. No.: 09/409,683
`
`(22) Filed:
`
`Oct. 1, 1999
`
`Related U.S. Application Data
`
`( 63) Continuation-in-part of application No. 09/112,171, filed on
`Jul. 8, 1998, now Pat. No. 6,460,094.
`Int. Cl.7 .................................................. G06F 9/45
`(51)
`(52) U.S. Cl. ................................. 716/8; 716/9; 716/10;
`716/11
`(58) Field of Search ............................. 716/4, 8; 712/1,
`712/230; 710/8, 26, 63, 108, 262, 269,
`305, 306; 379/142.15
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`4,500,933 A
`4,785,469 A
`5,043,938 A
`5,473,264 A
`5,481,696 A
`5,548,782 A
`5,577,213 A
`5,612,634 A
`
`2/1985 Chan . ... ... ... .. ... ... ... ... .. . 360/69
`11/1988 Joshi et al.
`................. 375/110
`8/1991 Ebersole ..................... 364/900
`12/1995 Mader et al.
`................. 326/30
`1/1996 Lomp et al. ................ 395/500
`8/1996 Michael et al. ............. 395/835
`11/1996 Avery et al. ................ 395/280
`3/1997 MacKenna . ... ... ... ... ... .. . 326/62
`
`OTHER PUBLICATIONS
`
`Universal Serial Bus Specification, Rev. 1.1, Section 7.1.5:
`Device speed identification, pp. 113 and 114, Sep. 23, 1998.
`
`* cited by examiner
`
`Primary Examiner-Vuthe Siek
`Assistant Examiner---Naum Levin
`(74) Attorney, Agent, or Firm-Joseph R. Kelly; Westman,
`Champlin & Kelly, P.A.
`
`(57)
`
`ABSTRACT
`
`A peripheral device is connectable to a computer having one
`of a first interface and a second interface. The first interface
`communicates with the peripheral device over a differential
`data connection having a first data conductor and a second
`data conductor. The second interface communicates with the
`peripheral device over a clock conductor and a single ended
`data connection which includes a data conductor. The
`peripheral device includes an interface detection component
`coupled to at least one of first and second communication
`conductors used to communicate between the peripheral
`device and the computer. The interface detection component
`is configured to detect which of the first and second inter(cid:173)
`faces the peripheral device is connected to.
`
`33 Claims, 7 Drawing Sheets
`
`142~
`
`vcc
`
`1S4
`
`INTERFACE CONTROL
`SHOWN IN LOW SPEED CONFIGURATION
`
`146
`
`148
`
`PSr.!
`COMMUNICATIONS
`
`152
`
`TO
`COMPUTER
`20
`
`LGE-1011 / Page 1 of 15
`LGE v. Fundamental
`
`

`

`U.S. Patent
`
`Sep.23,2003
`
`Sheet 1 of 7
`
`US 6,625, 790 Bl
`
`FIG. 1
`
`REMOVABLE
`STORAGE
`29
`
`OPTICAL
`DISK
`31
`
`MONITOR
`47
`
`COMPUTER20
`
`VIDEO ADAPTER
`48
`
`t - - - - - '
`
`Optical Disk Drive
`30
`
`Magnetic Disk
`Drive28
`
`HARO DRIVE 27
`
`INTF 32 t--L....-.....-'
`
`CPU
`
`21
`
`ROM24
`810$26
`
`RAM
`25
`
`OPERATING
`SYSTEM 35
`
`23
`
`SERIAL
`PORT
`INTERFACE
`46
`
`PS2/USB
`PORT45
`
`NETWORK
`ADAPTER 53
`
`MEMORY22
`
`PROGRAM
`MODULE 37
`
`APPLICATION
`PROGRAMS36
`1-------' PROGRAM DATA 38
`
`KEYBOARD MOUSE
`40
`42
`
`REMOTE
`COMPUTER49
`
`MEMORY SO
`
`LGE-1011 / Page 2 of 15
`
`

`

`U.S. Patent
`
`Sep.23,2003
`
`Sheet 2 of 7
`
`US 6,625,790 Bl
`
`108
`
`VCC114
`112
`
`100
`
`USB
`INTERFACE 102
`
`COMPUTER 20
`
`21
`
`HIGH SPEED USB
`PERIPHERAL DEVICE
`
`HOST
`D-PROCESSOR
`r-t-t--.~--H-~l--~-1
`
`1 0
`
`116
`
`118
`
`FIG. 2A
`
`108
`
`112
`
`USB
`INTERFACE 102
`
`COMPUTER20
`
`21
`
`120
`
`LOW SPEED USB
`PERIPHERAL DEVICE
`
`HOST
`D- PROCESSOR
`r--1H--,-~~~~__:~
`
`106 122
`
`116
`
`118
`
`FIG. 28
`
`LGE-1011 / Page 3 of 15
`
`

`

`U.S. Patent
`US. Patent
`
`Sep.23,2003
`Sep. 23, 2003
`
`Sheet 3 of 7
`Sheet 3 0f 7
`
`US 6,625, 790 Bl
`US 6,625,790 B1
`
`.....
`21
`N
`
`20
`
`~
`<(
`0
`
`~
`()
`0
`....J
`(.)
`
`co
`N .....
`
`
`a::
`~'\
` \
`PROCESSOR
`0
`1-- en
`en en
`HOST
`0W
`:z: (.)
`0
`0:::
`Q..
`
`INTERFACE
`
`~
`.....
`
`w
`(.)
`N <(
`Cf) LL
`a. 0:: w ()
`1-- >
`z
`
`()
`
`
`
`(.)
`(.)
`
`>
`
`0
`.....
`~
`
`a:>
`.....
`N
`
`<O
`0
`
`CX)
`0
`......
`
`CX)
`l"')
`
`.....
`
`<O
`.....
`l"')
`
`0
`.....
`.....
`
`0
`FIG.2C
`N
`•
`(9
`-
`LL
`
`~
`
`0
`
`()~,
`
`(.)
`>
`
`N
`.....
`l"')
`
`(.)
`(.)
`>
`
`
`....J
`
`P82PERIPERAL
`~w
`DEVICE
`N W (.)
`~
` 124
`(/) a.. >
`.....
`a..- w
`ffi Cl
`Q..
`
`LGE-1011 / Page 4 of 15
`
`LGE-1011 / Page 4 of 15
`
`

`

`lo-"
`~
`Q
`\0
`~
`(It
`N
`O'I
`5J'.
`rJ'J.
`e
`
`-..J
`0 .....,
`.i;;..
`
`~ .....
`'Jl =(cid:173)~
`
`8
`N c
`~
`N
`~ '?
`'Jl
`
`~ = ......
`~ ......
`~
`•
`\JJ.
`d •
`
`FIG. 3
`
`20
`COMPUTER
`TO
`
`152
`
`·158
`
`PS2 CLOCK/USS D+
`
`PS2 DATA/USB 0-
`
`COMMUNICATIONS
`PS/2
`
`148
`
`INTERFACE ENGINE
`USB SIE
`
`160
`
`144
`
`146
`
`SHO\NN IN LOW SPEED CONFIGURATION
`
`INTERFACE CONTROL
`
`154
`
`VCC
`
`ADAPTER
`
`PS/2
`
`150
`
`vcc
`
`142~
`
`LGE-1011 / Page 5 of 15
`
`

`

`U.S. Patent
`
`Sep.23,2003
`
`Sheet 5 of 7
`
`US 6,625, 790 Bl
`
`COUNTING
`
`CONTACT
`BOUNCE
`DELAY
`
`FIG. 4
`
`172
`
`178
`
`COUNTING
`
`ANY VALID USS
`COMMUNICATION
`
`siPS2_DETECTED
`
`siUSB_DETECTED
`
`LGE-1011 / Page 6 of 15
`
`

`

`lo-"
`~
`Q
`\0
`~
`(It
`N
`a-..
`-..a-..
`rJ'J.
`e
`
`-..J
`0 .....,
`O'I
`~ .....
`'Jl =(cid:173)~
`
`8
`N c
`~
`N
`~ '?
`'Jl
`
`~ = ......
`~ ......
`~
`•
`\JJ.
`d •
`
`FIG. 5
`
`20
`COMPUTER
`TO
`
`152
`
`·158
`
`PS2 CLOCK/USS D+
`
`PS2 DATA/USB D-
`
`160
`
`188
`
`154
`
`vcc
`ADAPTER
`
`PS/2
`
`-'
`I
`I
`I
`I
`I
`I
`
`VCC
`--
`
`-
`
`150
`
`192
`
`-
`
`-
`
`-
`
`COMMUNICATIONS
`PS/2
`
`148
`
`INTERFACE ENGINE
`USB SIE
`
`146
`
`PULL-UP CONTROL
`
`....--->-~~~~~~-.
`
`186
`
`184
`
`L
`I
`I
`I
`I
`'--J
`I
`\.
`----
`190
`
`INTERFACE CONTROL
`
`182~
`
`SHOWN IN LOW SPEED CONFIGURATION
`
`LGE-1011 / Page 7 of 15
`
`

`

`U.S. Patent
`
`Sep.23,2003
`
`Sheet 7 of 7
`
`US 6,625, 790 Bl
`
`1mSec
`
`FIG. 6
`
`(COUNTING
`
`siUNCERTIAN
`USB A TT ACH(D-)
`
`SEO OR)
`
`KSTATE
`
`TOGGLE
`TEST
`FAIL
`
`202
`
`TERMINAL
`COUNT
`
`siTOGGLE _OM
`ATTACH/DETACH
`
`use
`TOGGLE
`PATERERN
`10101
`
`PS/2
`TOGGLE
`PATTERN
`11111
`
`LGE-1011 / Page 8 of 15
`
`

`

`US 6,625,790 Bl
`
`1
`METHOD AND APPARATUS FOR
`DETECTING THE TYPE OF INTERFACE TO
`WHICH A PERIPHERAL DEVICE IS
`CONNECTED
`
`REFERENCE TO CO-PENDING APPLICATION
`
`The present application is a continuation-in-part of pend(cid:173)
`ing U.S. patent application Ser. No. 09/112,171, filed Jul. 8,
`1998 now U.S. Pat. No. 6,460,094 entitled "METHOD AND
`APPARATUS FOR DETECTING THE TYPE OF INTER(cid:173)
`FACE TO WHICH A PERIPHERAL DEVICE IS CON(cid:173)
`NECTED" and assigned to the same assignee as the present
`application, and which is hereby incorporated by reference.
`
`BACKGROUND OF THE INVENTION
`
`10
`
`15
`
`2
`the host computer. The open-collector or open-drain circuit
`(commonly a transistor) is typically implemented inside the
`microprocessor. Another pull-up resistor is required inside
`the peripheral device as well. The peripheral device corn-
`s municating over a PS2 interface is responsible for providing
`a clock signal on the clock conductor, regardless of the
`direction of data flow on the data conductor. The host
`computer pulls the clock conductor to a logic low level to
`inhibit communication from the peripheral device, and it can
`also pull the data conductor low to signal to the peripheral
`device that the host computer intends to transmit data to the
`peripheral device.
`The USE interface also uses two conductors which
`include differential data signal conductors D+ and D-.
`In the USE interface at the USE port (i.e., at the host
`computer or USE hub), the two conductors are pulled to a
`logic low level via 15 k ohm resistors. In the peripheral
`device, the D+ conductor is pulled to approximately 3.3
`volts via a 1.5 k ohm resistor if the peripheral device is a
`20 high-speed USE peripheral device. The D- conductor is
`pulled to 3.3 volts via a 1.5 k ohm resistor if the peripheral
`device is a low-speed USE peripheral device. When a
`peripheral device is attached to the USE port, the USE host
`determines whether it is a low-speed or high-speed device
`25 by determining which of the D+ or D- conductors is pulled
`to the logical high level.
`Thus, it can be seen that the two interfaces have different
`hardware structures, and communicate using different soft(cid:173)
`ware protocols. Traditionally, separate peripheral devices
`have been provided, one being configured to communicate
`with a USE interface, and the other being configured to
`communicate with a PS2 interface. This requires the manu(cid:173)
`facturer of such peripheral devices to offer two different
`types of peripheral devices in order to support these two
`35 different interfaces.
`
`30
`
`The present invention relates to a peripheral device con(cid:173)
`nectable to a computer. More particularly, the present inven(cid:173)
`tion relates to a peripheral device configured to detect the
`type of interface to which it is connected.
`A wide variety of peripheral devices are currently con(cid:173)
`figured to be connectable to computers. Such peripheral
`devices commonly include user input devices, such as
`keyboards, point and click devices (traditionally referred to
`as a computer mouse) and other similar types of devices.
`The computer to which such devices are connected com(cid:173)
`municates with the devices through one of a number of
`interfaces. Interfaces commonly used to connect to such
`peripheral devices include a serial interface (such as an
`RS232 interface) and a PS2 interface. Indeed, the PS2
`interface has long been a standard for connecting keyboards
`and mice to computers.
`However, recently, another serial interface referred to as
`a universal serial bus (USE) interface has been introduced.
`The USE interface accommodates a wide variety of com(cid:173)
`puter peripherals, including, for example, keyboards and
`mice. However, a conventional computer is typically pro(cid:173)
`vided with only one interface (such as a PS2 or USE
`interface) for communication with peripheral devices. 40
`Therefore, if the computer is provided with a PS2 interface,
`the keyboard or mouse must be configured to support
`communication with the computer according to a protocol
`defined by the PS2 interface. Similarly, if the computer is
`provided with the USE interface, the keyboard or mouse 45
`must be configured to communicate according to a protocol
`defined by the USE interface.
`In order to do this, a conventional computer peripheral
`device contains a microprocessor which runs a software
`program to carry out the functions of that particular periph(cid:173)
`eral device. In the device such as a keyboard or mouse, the
`software program includes an interface between the periph(cid:173)
`eral device and the host computer, through which the periph(cid:173)
`eral device communicates with the host computer. Such
`communication often includes receiving commands from ss
`the host computer and transmitting data and status informa(cid:173)
`tion to the host computer.
`As discussed above, the PS2 and USE interfaces have
`different hardware and software requirements, which must
`be met by the microprocessor in the peripheral device so that 60
`the peripheral device can communicate with the host com(cid:173)
`puter. The PS2 interface uses two conductors which include
`a separate clock conductor and a separate data conductor.
`These conductors are driven by the computer through an
`open-collector or open-drain circuit, and have a pull-up 65
`resistor (typically in the range of 2 k ohms to 10 k ohms)
`pulling the conductor to a rail voltage (such as VCC) inside
`
`SUMMARY OF THE INVENTION
`The present invention defines a method and apparatus in
`the peripheral device such that the peripheral device can
`determine which type of interface it is connected to, and
`configure itself accordingly.
`The peripheral device is connectable to a computer having
`one of a first interface and a second interface. The first
`interface communicates with a peripheral device over a
`differential data connection having a first data conductor and
`a second data conductor. The second interface communi(cid:173)
`cates with the peripheral device over a clock conductor and
`a single-ended data connection, which includes a data con(cid:173)
`ductor. The peripheral device has first and second commu-
`so nication conductors configured for connection to the first
`and second data conductors in the differential data connec-
`tion and to the first data conductor in the single ended data
`connection and the clock conductor. The peripheral device
`includes an interface detection component configured to
`detect which of the first and second interfaces the peripheral
`device is connected to. The peripheral device also includes
`a controller component configured to communicate between
`the peripheral device and the computer according to a
`protocol corresponding to the detected interface.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a block diagram of an exemplary environment
`in which an input device in accordance with the present
`invention can be used.
`FIGS. 2A-2C illustrate conventional high-speed and low(cid:173)
`speed USE peripheral devices and a PS2 peripheral device
`coupled to a USE interface and a PS2 interface, respectively.
`
`LGE-1011 / Page 9 of 15
`
`

`

`US 6,625,790 Bl
`
`3
`FIG. 3 illustrates a peripheral device in accordance with
`one embodiment of the present invention.
`FIG. 4 is a state diagram illustrating the operation of the
`peripheral device shown in FIG. 3.
`FIG. 5 is a block diagram of a peripheral device in 5
`accordance with another embodiment of the present inven(cid:173)
`tion.
`FIG. 6 is a state diagram illustrating the operation of the
`peripheral device shown in FIG. 5.
`
`10
`
`4
`Although the exemplary environment described herein
`employs a hard disk, a removable magnetic disk 29 and a
`removable optical disk 31, it should be appreciated by those
`skilled in the art that other types of computer readable media
`which can store data that is accessible by a computer, such
`as magnetic cassettes, flash memory cards, digital video
`disks, Bernoulli cartridges, random access memory (RAM),
`read only memory (ROM), and the like, may also be used in
`the exemplary operating environment.
`A number of program modules may be stored on the hard
`disk, magnetic disk 29, optical disk 31, ROM 24 or RAM 25,
`including an operating system 35, one or more application
`programs 36, other program modules 37, and program data
`38. A user may enter commands and information into the
`15 personal computer 20 through input devices such as a
`keyboard 40 and pointing device (or mouse) 42. Other input
`devices (not shown) may include a microphone, joystick,
`game pad, satellite dish, scanner, or the like. These and other
`input devices are often connected to the processing unit 21
`20 through one of a plurality of ports. For instance, keyboard 40
`and mouse 42 are connected through a PS2 or USE interface
`45. In the illustrative embodiment, interface (or port) 45 is
`coupled to the system bus 23. User input devices may also
`be connected by other interfaces, such as a sound card, a
`25 parallel port, or a game port. A monitor 47 or other type of
`display device is also connected to the system bus 23 via an
`interface, such as a video adapter 48. In addition to the
`monitor 47, personal computers may typically include other
`peripheral output devices such as speakers and printers (not
`30 shown).
`The personal computer 20 may operate in a networked
`environment using logic connections to one or more remote
`computers, such as a remote computer 49. The remote
`computer 49 may be another personal computer, a server, a
`35 router, a network PC, a peer device or other network node,
`and typically includes many or all of the elements described
`above relative to the personal computer 20, although only a
`memory storage device 50 has been illustrated in FIG. 1. The
`logic connections depicted in FIG. 1 include a local area
`40 network (LAN) 51 and a wide area network (WAN) 52. Such
`networking environments are commonplace in offices,
`enterprise-wide computer network intranets and the Internet.
`When used in a LAN networking environment, the per(cid:173)
`sonal computer 20 is connected to the local area network 51
`45 through a network interface or adapter 53. When used in a
`WAN networking environment, the personal computer 20
`typically includes a modem 54 or other means for establish(cid:173)
`ing communications over the wide area network 52, such as
`the Internet. The modem 54, which may be internal or
`50 external, is connected to the system bus 23 via the serial port
`interface 46. In a network environment, program modules
`depicted relative to the personal computer 20, or portions
`thereof, may be stored in the remote memory storage
`devices. It will be appreciated that the network connections
`55 shown are exemplary and other means of establishing a
`communications link between the computers may be used.
`FIGS. 2A-2C illustrate conventional peripheral devices
`coupled to conventional interfaces. FIG. 2A illustrates a
`high-speed USE peripheral device 100 connected through
`60 USE interface 102 to CPU 21 of host computer 20. It should
`be noted that high-speed USE peripheral device 100 can be
`any suitable peripheral device, such as keyboard 40 or
`mouse 42 or another suitable peripheral device. Peripheral
`device 100 is connected to USE interface 102 and commu-
`65 nicates therewith over two conductors 104 and 106. Con(cid:173)
`ductors 104 and 106 are connected to corresponding con(cid:173)
`ductors 108 and 110 through USE connector 112.
`
`DETAILED DESCRIPTION OF IBE
`PREFERRED EMBODIMENTS
`The present invention includes a method and apparatus,
`implemented in a peripheral device, by which the peripheral
`device detects whether it is coupled to a PS2 interface or a
`USE interface. A peripheral device, in accordance with one
`aspect of the present invention, is configured initially to
`expect a first interface and senses the state of the interface
`to configure itself appropriately.
`FIG. 1 and the related discussion are intended to provide
`a brief, general description of a suitable computing envi(cid:173)
`ronment in which the invention may be implemented.
`Although not required, the invention will be described, at
`least in part, in the general context of computer-executable
`instructions, such as program modules, being executed by a
`personal computer or other computing device. Generally,
`program modules include routine programs, objects,
`components, data structures, etc. that perform particular
`tasks or implement particular abstract data types. Moreover,
`those skilled in the art will appreciate that the invention may
`be practiced with other computer system configurations,
`including hand-held devices, multiprocessor systems,
`microprocessor-based or programmable consumer
`electronics, network PCs, minicomputers, mainframe
`computers, and the like. The invention is also applicable in
`distributed computing environments where tasks are per(cid:173)
`formed by remote processing devices that are linked through
`a communications network. In a distributed computing
`environment, program modules may be located in both local
`and remote memory storage devices.
`With reference to FIG. 1, an exemplary environment for
`the invention includes a general purpose computing device
`in the form of a conventional personal computer 20, includ(cid:173)
`ing processing unit 21, a system memory 22, and a system
`bus 23 that couples various system components including
`the system memory to the processing unit 21. The system
`bus 23 may be any of several types of bus structures
`including a memory bus or memory controller, a peripheral
`bus, and a local bus using any of a variety of bus architec(cid:173)
`tures. The system memory includes read only memory
`(ROM) 24 a random access memory (RAM) 25. A basic
`input/output 26 (BIOS), containing the basic routine that
`helps to transfer information between elements within the
`personal computer 20, such as during start-up, is stored in
`ROM 24. The personal computer 20 further includes a hard
`disk drive 27 for reading from and writing to a hard disk (not
`shown), a magnetic disk drive 28 for reading from or writing
`to removable magnetic disk 29, and an optical disk drive 30
`for reading from or writing to a removable optical disk 31
`such as a CD ROM or other optical media. The hard disk
`drive 27, magnetic disk drive 28, and optical disk drive 30
`are connected to the system bus 23 by a hard disk drive
`interface 32, magnetic disk drive interface 33, and an optical
`drive interface 34, respectively. The drives and the associ(cid:173)
`ated computer-readable media provide nonvolatile storage
`of computer readable instructions, data structures, program
`modules and other data for the personal computer 20.
`
`LGE-1011 / Page 10 of 15
`
`

`

`US 6,625,790 Bl
`
`5
`
`6
`appropriately. This inhibits communication from peripheral
`device 124. Host processor 21 can also pull the data con(cid:173)
`ductor 108 low by manipulating transistor 138 in order to
`signal peripheral device 124 that host processor 21 intends
`to transmit data.
`FIG. 3 illustrates a peripheral device 142 in accordance
`with one embodiment of the present invention. Peripheral
`device 142 includes a communication controller 144 which,
`in turn, includes a USE SIE interface engine 146 and a PS2
`communications controller 148. Peripheral device 142 also,
`in one illustrative embodiment, includes pull-up resistor 150
`which pulls the PS2 data/USE D- signal line to a predeter(cid:173)
`mined voltage potential (such as VCC). Peripheral device
`142 also includes, in one illustrative embodiment, a cable
`with USE connector 152.
`It should be noted that, in FIG. 3, the PS2 data and USE
`D- lines are indicated as being carried by signal line or
`conductor 160 while the PS2 clock and USE D+ signals are
`indicated as being carried by conductor 158. Of course, the
`USE D+ signal can be carried by the same conductor as the
`PS2 data signal and the USE D- signal can be carried by the
`same conductor as the PS2 clock signal. Also, while pull-up
`resistor 150 is shown coupled to conductor 160 (which
`corresponds to the USE D- signal), it could also be coupled
`to the conductor which corresponds to the USE D+ signal
`where the USE device is a high speed device, rather than a
`low speed device. However, the present discussion will
`proceed with respect to the embodiment illustrated in FIG.
`3, for the sake of simplicity.
`FIG. 3 further illustrates a PS2 adapter 154 in accordance
`with one embodiment of the present invention. Adapter 154
`includes a USE connector 156 which mates with USE
`connector 152. Adapter 154 connects the signal lines 158
`and 160 to an output connector 162 which is suitable for
`being coupled to a connector or cable from computer 20. In
`one illustrative embodiment, connectors 152 and 156 are
`implemented as a USE series A plug and receptacle, respec(cid:173)
`tively. Connector 162 is implemented as a PS2 mini-din
`40 connector.
`Adapter 154, in the illustrative embodiment, also includes
`a pair of pull-up resistors 164 and 166. When adapter 154 is
`coupled to peripheral device 142, pull-up resistor 164 pulls
`the PS2 clock/USE D+ signal line to VCC. Resistor 166
`pulls the PS2 data/USE D- signal line to VCC as well. The
`pull-ups in adapter 154 eliminate the necessity for the
`microprocessor on peripheral device 142 to control these
`dynamically. This saves firmware code space and also
`reduces necessary pin count on the microprocessor by one or
`two pins. This provides a significant cost savings.
`Table 1 below illustrates the configuration of the two
`signals provided by both USE and PS2 devices. Table 1
`illustrates the signals for a USE low speed device.
`
`30
`
`5
`Conductors 104 and 106 carry signals denoted D+ and D(cid:173)
`in a high-speed USE device. Signals D+ and D- are differ(cid:173)
`ential digital data signals with which peripheral device 100
`communicates with computer 20.
`In a high-speed USE arrangement, conductor 104, which
`carries signal D+, is pulled to a logical high level (such as
`a +5 Volt supply or other desired supply voltage potential
`hereinafter referred to as VCC or the VCC rail) by a pull-up
`resistor 114. Resistor 114 is preferably valued such that the
`voltage potential to which conductor 104 is pulled is 10
`approximately 3.3 volts. Therefore, resistor 114 can, for
`instance, be a 7.5 k ohm resistor connected to a 5 volt VCC
`rail.
`In USE interface 102 on computer 20, both conductors
`108 and 110 (which correspond to the D+ and D- signals) 15
`are pulled to a logic low level by two 15 k ohm resistors 116
`and 118. When peripheral device 100 is initially attached to
`computer 20 through USE interface 102, computer 20 can
`determine that peripheral device 100 is a high-speed USE
`peripheral device because the conductor 104 corresponding 20
`to signal D+ is pulled to a logical high level, while conductor
`106 which corresponds to signal D- is not.
`FIG. 2E illustrates the connection of a low-speed USE
`peripheral device 120 to computer 20. Some items are
`similar to those shown in FIG. 2A, and are similarly num- 25
`bered. However, rather than having conductor 104
`(corresponding to signal D+) pulled to a logical high level
`with resistor 114, conductor 106 (which corresponds to
`signal D-) is pulled to a logical high level with resistor 122.
`Thus, computer 20 determines that peripheral device 120 is
`a low-speed USE device.
`FIG. 2C illustrates another peripheral device 124 con(cid:173)
`nected to computer 20. Peripheral device 124 is configured
`to communicate with computer 20 through a PS2 interface 35
`126. PS2 peripheral device 124 communicates with com(cid:173)
`puter 20 over a pair of conductors 104 and 106, which
`correspond to a data signal and a clock signal. Conductors
`104 and 106 are connected to transistors 131 and 133, which
`are configured as open-collector or open-drain switches
`controlled by the microprocessor in peripheral device 124.
`Conductors 104 and 106 are connected to conductors 108
`and 110 through PS2 connector 128. Conductors 104 and
`106 are pulled to a logical high level at peripheral device 124
`by resistors 130 and 132 which are typically in a 2 k-10 k 45
`ohm range.
`In PS2 interface 126, conductors 108 and 110 are also
`pulled to a logical high level by resistors 134 and 136, which
`are also typically in a 2 k-10 k ohm range. Conductors 108
`and 110 are also coupled to ground by transistors 138 and 50
`140, which are typically open-drain or open-collector and
`driven by appropriate circuitry in processor 21. It should
`also be noted that transistors 138 and 140 can typically be
`implemented inside processor 21, or discretely.
`With the open-collector configured interface, when a 55
`logical 1 is written to either conductor 108 or 110, the
`conductor is not actively driven high. Instead, it is pulled
`high, to nearly the rail voltage VCC, via the pull-up resistors
`134 and 136. In this manner, either host processor 21 or
`peripheral device 124 can drive the conductor low without
`the concern of the conductor already being actively driven
`high.
`Peripheral device 124 is responsible for providing the
`clock signal over conductors 106 and 110, to host processor
`21, regardless of the direction of data flow over conductors
`104 and 108. Host processor 21 can pull the conductor 110
`carrying the clock signal low by controlling transistor 140
`
`TABLE 1
`
`D+/CLK
`
`0-/DAT
`
`USE
`
`L
`
`L
`
`H
`
`H
`
`L
`
`H
`
`L
`
`H
`
`SEO
`(Single
`Ended 0)
`or Reset
`J, Idle
`
`K,Xmit
`Resume
`SEl
`
`PS/2
`
`Host
`Inhibit
`
`Host
`Inhibit
`Host Xmit
`
`Idle,
`
`l/O
`State
`
`0
`
`2
`
`3
`
`60
`
`65
`
`LGE-1011 / Page 11 of 15
`
`

`

`US 6,625,790 Bl
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`7
`
`TABLE 1-continued
`
`l/O
`State
`
`D+/CLK
`
`0-/DAT
`
`USE
`
`PS/2
`
`(Single
`Ended 1)
`
`Confirm
`Connect
`
`25
`
`FIG. 4 is a state diagram illustrating the operation of
`peripheral device 142 shown in FIG. 3 and will be described 10
`with reference to FIG. 3 and Table 1. Communication
`controller 144 begins by starting the initialization process, as
`indicated by state 170 in FIG. 4. After power-up, commu(cid:173)
`nication controller 144 waits for a time-out period (such as
`10-100 milliseconds). This allows time for contact bounce 15
`during mating of the connectors illustrated in FIG. 3. This is
`indicated by state 172 in FIG. 4.
`After reaching the designated time-out period, communi(cid:173)
`cation controller 144 enters an indeterminate state 174. In
`the indeterminate state, controller 144 "assumes" that it is 20
`connected to a USE interface. In other words, controller 144
`is configured to receive a valid USE communication, or
`USE reset signaling. In the event that controller 144 is in the
`indeterminate state 174 and receives valid USE 1.0 or 1.1
`communications, controller 144 determines that it has
`detected a USE interface and moves to state 176. The USE
`interface engine 146 in controller 144 then takes over
`communications between peripheral device 142 and com(cid:173)
`puter 20.
`In the indeterminate state 174, controller 144 also peri- 30
`odically polls for the presence of a PS2 interface by moni(cid:173)
`toring the state of signal lines 158 and 160. In one specific
`embodiment, controller 144 looks for 1/0 state 3 in Table 1
`(or the SEl condition) on signal lines 158 and 160. If such
`a condition is detected, controller 144 moves to state 178 35
`and determines whether the SEl condition is detected for a
`sufficient time period (such as in excess of three
`milliseconds). If not, control reverts back to indeterminate
`state 174.
`However, if the SEl condition is maintained for the
`necessary time period, and the terminal count is reached,
`controller 144 determines that it has detected a PS2 interface
`and moves to state 180. This causes USE functions to be
`terminated, and PS2 communications controller 148 takes
`over communication between peripheral device 142 and
`computer 20. It will be noted that in this case, PS2 adapter
`154 will be plugged into peripheral device 142 and computer
`20. Thus, pull-up resistors 164 and 166 are present on both
`signal lines 158 and 160. Therefore, as long as the host
`computer 20 is not inhibiting the device communications (by
`holding one or both of the clock and data lines low), the
`interface is immediately identified as a PS2 interface, and
`communications are implemented according to the PS2
`specification.
`The embodiment illustrated in FIGS. 3 and 4 has a 55
`number of advantages. No external USE pull-up resistors
`are required. Instead, resistor 150 is simply hard wired to
`VCC. This allows the elimination of pull-up resistor control,
`and reduces pin count. Similarly, since the PS2 adapter 154
`provides pull-up resistors 164 and 166, no internal control is 60
`required for PS2 pull-up resistors. This results in fewer
`components in the peripheral device controller. This also
`renders the device simpler and less costly. Similarly, this
`embodiment provides immediate conformance and response
`to USE 1.1 interface signaling requirements.
`It has been found that the above embodiment works very
`well on a vast majority of host computers. However, some
`
`8
`computers were discovered to hold PS2 interface commu(cid:173)
`nication lines in an inhibited state for extensive periods of
`time, even on power-up. This can make it difficult to detect
`and respond to initial communication sequences in a timely
`5 manner. Similarly, where a peripheral device 142 is "hot
`plugged" into the host computer, the inhibition of the PS2
`communication by the host computer can make it difficult
`for the detection system d