(12> Ulllted States Patent
`Ghia et al.
`
`US006366128B1
`(16) Patent N6.=
`US 6,366,128 B1
`(45) Date 0f Patent:
`Apr. 2, 2002
`
`OTHER PUBLICATIONS
`
`Electrical Characteristics of LoW Voltage Differential Sig
`naling (LVDS) Interface Circuits, TIA/EIA—644, Mar. 1996.
`Jon Brunetti and Brian Von HerZen, “Multi—Drop LVDS
`With VirteX—E FPGAs,” XAPP231 (Version 1.0) Sep. 23,
`1999.
`“LVDS M 1'91 p C
`R p
`Appl'
`'
`'
`” p b
`u t1 ro
`onnections
`e ort
`1cat1on
`u -
`lished by Texas Instruments, Jul. 1999.
`
`(54) CIRCUIT FOR PRODUCING LOW-VOLTAGE
`DIFFERE TIAL SIG ALS
`N
`N
`(75) Inventors. Atu] V_ Ghia San Jose. Suresh M_
`Mellon sunn’yvale. Da’vid P_ Schultz
`San Jos’e an of CA’WS)
`’
`’
`(73) Assignee. XlllIlX, 1116., San Jose, CA (US)
`'
`-
`"
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U-S-C- 154(k)) by 0 days-
`
`(21) Appl, N()_j 09/655,168
`(22) Filed:
`Sep. 5, 2000
`
`7
`(51) Int. Cl. ................... .. H03K 19/094; H03K 19/173
`(52) US. Cl. ........................... .. 326/83; 326/44; 326/40;
`326/49
`(58) Field of Search ............................ .. 326/83, 86, 87,
`326/38, 40, 44, 45, 46, 49, 30
`
`(56)
`
`References Cited
`
`US' PATENT DOCUMENTS
`5,355,035 A 4 10/1994 V0ra et a1_ ________________ __ 327/433
`5,812,461 A * 9/1998 Komarek et a1, ____ __ 365/189_05
`5,958,026 A
`9/1999 Goetting et al.
`
`FOREIGN PATENT DOCUMENTS
`
`*
`
`.
`
`.
`
`cued by exammer
`Primary Examiner—Michael Tokar
`Assistant Examiner—Daniel D. Chang
`(74) Attorney, Agent, or Firm—Arthur J. Behiel; Edel M.
`Young
`(57)
`
`ABSTRACT
`
`Described are systems for producing differential logic sig
`nals. These systems can be adapted for use With different
`loads by Programming one or more Programmable elements
`One embodiment includes a series of driver stages, the
`outputs of Which are connected to one another. The driver
`stages turn on successively to provide increasingly powerful
`differential ampli?cation. This progressive increase in
`ampli?cation produces a corresponding progressive
`decrease in output resistance, Which reduces the noise asso
`ciated With signal re?ection. The systems can be incorpo
`rated into programmable IOBs to enable PLDs to provide
`differential out ut si nals.
`p
`g
`
`JP
`
`60260254
`
`* 6/1987
`
`................ .. 326/30
`
`23 Claims, 10 Drawing Sheets
`
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`EN_T
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`
`

`

`US. Patent
`
`Apr. 2, 2002
`
`Sheet 1 0f 10
`
`US 6,366,128 B1
`
`
`
`FIG. 1
`
`TX_A
`
`FIG. 2
`
`(PRIOR ART)
`
`Huawei V. FISI Exhibit No. 1026 - 2/17
`
`

`

`U.S. Patent
`
`Apr. 2, 2002
`
`Sheet 2 0f 10
`
`US 6,366,128 B1
`
`‘5 300
`
`TX_A - TX B
`
`+250 TO 400 mV
`0v (DIFF)
`-250 TO -4OO mV
`
`FIG. 3
`(PRIOR ART)
`
`|
`I
`
`DX '
`
`’ XDRVR
`
`PRE
`DRVR
`P
`
`XDS
`
`CBIT
`£5
`CBIT EN_DS
`@
`
`FIG. 4
`
`

`

`US. Patent
`
`Apr. 2, 2002
`
`Sheet 3 0f 10
`
`US 6,366,128 B1
`
`405 \‘
`
`X_DS/
`
`’.
`
` ||I
`
`D_|N
`
`I
`_ _____
`
`VCCO
`
`I
`:
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`1
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`V (1500 L: __________
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`514
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`1
`
`DX
`
`D
`
`D/
`
`V
`
`530
`
`,.
`
`DX/
`
`Huawei V. FISI Exhibit No. 1026 - 4/17
`
`

`

`U.S. Patent
`
`Apr. 2, 2002
`
`Sheet 4 0f 10
`
`US 6,366,128 B1
`
`[415
`
`TX_A
`
`TX B
`
`PCOM
`
`NBIAS
`
`NCOM
`
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`QBIIVTTEWW
`
`
`
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`
`|||||| isillimJ ulsiillmwll m mw _ _ % 2
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`FIG. 5B
`
`

`

`U.S. Patent
`
`Apr. 2, 2002
`
`Sheet 5 0f 10
`
`US 6,366,128 B1
`
`[410
`
`TX_A
`
`TX_B
`
`

`

`U.S. Patent
`
`Apr. 2, 2002
`
`Sheet 6 0f 10
`
`US 6,366,128 B1
`
`/ 600
`
`+
`63;
`_
`
`I
`I
`
`—TX_A
`
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`

`

`U.S. Patent
`US. Patent
`
`Apr. 2, 2002
`Apr. 2, 2002
`
`Sheet 7 0f 10
`Sheet 7 0f 10
`
`US 6,366,128 B1
`US 6,366,128 B1
`
`'/ 700
`
`528
`
`VCCO
`
`D/
`
`D1/
`
`D2/
`
`530
`
`DX/
`
`FIG. 7A
`FIG. 7A
`
`Huawei V. FISI Exhibit No. 1026 - 8/17
`
`
`
`

`

`US. Patent
`
`Apr. 2, 2002
`
`Sheet 8 0f 10
`
`US 6,366,128 B1
`
`VCCO
`
`AXT
`
`TXB
`
`FIG. 7B
`
`Huawei V. FISI Exhibit No. 1026 - 9/17
`
`

`

`US. Patent
`
`Apr. 2, 2002
`
`Sheet 9 0f 10
`
`US 6,366,128 B1
`
`HAS
`
`HAS
`
`NGATE
`
`850
`
`NBMS
`
`804
`
`806
`
`808
`
`Huawei V. FISI Exhibit No. 1026 - 10/17
`
`

`

`US. Patent
`
`Apr. 2, 2002
`
`Sheet 10 0f 10
`
`US 6,366,128 B1
`
`BIAS
`
`BIAS/
`
`852
`
`NGATE
`
`NBIAS
`
`VCCO
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`NBIAS
`
`854
`
`Huawei V. FISI Exhibit No. 1026 - 11/17
`
`

`

`US 6,366,128 B1
`
`1
`CIRCUIT FOR PRODUCING LOW-VOLTAGE
`DIFFERENTIAL SIGNALS
`
`FIELD OF THE INVENTION
`
`This invention relates generally to methods and circuits
`for providing high-speed, loW-voltage differential signals.
`
`BACKGROUND
`
`The Telecommunications Industry Association (TIA)
`published a standard specifying the electrical characteristics
`of loW-voltage differential signaling (LVDS) interface cir
`cuits that can be used to interchange binary signals. LVDS
`employs loW-voltage differential signals to provide high
`speed, loW-poWer data communication. The use of differ
`ential signals alloWs for cancellation of common-mode
`noise, and thus enables data transmission With exceptional
`speed and noise immunity. For a detailed description of this
`LVDS Standard, see “Electrical Characteristics of LoW
`Voltage Differential Signaling (LVDS) Interface Circuits,”
`TIA/EIA-644 (March 1996), Which is incorporated herein
`by reference.
`FIG. 1 (prior art) illustrates an LVDS generator 100
`connected to an LVDS receiver 110 via a transmission line
`115. Generator 100 converts a single-ended digital input
`signal DiIN on a like-named input terminal into a pair of
`complementary LVDS output signals on differential output
`terminals TXiA and TXiB. A 100-ohm termination load
`RL separates terminals TXiA and TXiB, and sets the
`output impedance of generator 100 to the level speci?ed in
`the above-referenced LVDS Standard.
`LVDS receiver 110 accepts the differential input signals
`from terminals TXiA and TXiB and converts them to a
`single-ended output signal DiOUT. The LVDS Standard
`speci?es the properties of LVDS receiver 110. The present
`application is directed to differential-signal generators: a
`comprehensive discussion of receiver 110 is not included in
`the present application.
`FIG. 2 (prior art) schematically depicts LVDS generator
`100 of FIG. 1. Generator 100 includes a preampli?er 200
`connected to a driver stage 205. Preampli?er 200 receives
`the single-ended data signal DiIN and produces a pair of
`complementary data signals D and D/ (signal names termi
`nating in “/” are active loW signals). Unless otherWise
`speci?ed, each signal is referred to by the corresponding
`node designation depicted in the ?gures. Thus, for example,
`the input terminal and input signal to generator 100 are both
`designated DiIN. In each instance, the interpretation of the
`node designation as either a signal or a physical element is
`clear from the context.
`Driver stage 205 includes a PMOS load transistor 207 and
`an NMOS load transistor 209, each of Which produces a
`relatively stable drive current in response to respective bias
`voltages PBIAS and NBIAS. Driver stage 205 additionally
`includes four drive transistors 211, 213, 215, and 217.
`If signal DiIN is a logic one (e.g., 3.3 volts), preampli?er
`200 produces a logic one on terminal D and a logic Zero
`(e.g., Zero volts) on terminal D/. The logic one on terminal
`D turns on transistors 211 and 217, causing current to How
`doWn through transistors 207 and 211, up though termina
`tion load RL, and doWn through transistors 217 and 209 to
`ground (see the series of arroWs 219). The current through
`termination load RL develops a negative voltage betWeen
`output terminals TXiA and TXiB.
`Conversely, if signal DiIN is a logic Zero, preampli?er
`200 produces a logic Zero on terminal D and a logic one on
`
`10
`
`15
`
`25
`
`2
`terminal D/. The logic one on terminal D/ turns on transistors
`213 and 215, causing current to How doWn through transistor
`207, transistor 215, termination load RL, transistor 213, and
`transistor 209 to ground (see the series of arroWs 221). The
`current through termination load RL develops a positive
`voltage betWeen output terminals TXiA and TXiB.
`FIG. 3 (prior art) is a Waveform diagram 300 depicting the
`signaling sense of the voltages appearing across termination
`load RL of FIGS. 1 and 2. LVDS generator 100 produces a
`pair of differential output signals on terminals TXiA and
`TXiB. The LVDS Standard requires that the voltage
`betWeen terminals TXiA and TXiB remain in the range of
`250 mV to 450 mV, and that the voltage midWay betWeen the
`tWo differential voltages remains at approximately 1.2 volts.
`Terminal TXiA is negative With respect to terminal TXiB
`to represent a binary one and positive With respect to
`terminal B to represent a binary Zero.
`Aprogrammable logic device (PLD) is a Well-known type
`of IC that may be programmed by a user (e.g., a circuit
`designer) to perform speci?ed logic functions. Most PLDs
`contain some type of input/output block (IOB) that can be
`con?gured either to receive external signals or to drive
`signals off chip. One type of PLD, the ?eld-programmable
`gate array (FPGA), typically includes an array of con?g
`urable logic blocks (CLBS) that are programmably inter
`connected to each other and to the programmable IOBs.
`Con?guration data loaded into internal con?guration
`memory cells on the FPGA de?ne the operation of the FPGA
`by determining hoW the CLBS, interconnections, block
`RAM, and IOBs are con?gured.
`IOBs con?gured as output circuits typically provide
`single-ended logic signals to external devices. As With other
`types of circuits, PLDs Would bene?t from the performance
`advantages offered by driving external signals using differ
`ential output signals. There is therefore a need for IOBs that
`can be con?gured to provide differential output signals.
`There is also a need for LVDS output circuits that can be
`tailored to optimiZe performance for different loads.
`
`SUMMARY
`
`The present invention addresses the need for differential
`signal output circuits that can be tailored for use With
`different loads. In accordance With one embodiment, one or
`more driver stages can be added, as necessary, to provide
`adequate poWer for driving a given load. Driver stages are
`added by programming one or more programmable
`elements, such as memory cells, fuses, and antifuses.
`A differential driver in accordance With another embodi
`ment includes a multi-stage delay element connected to a
`number of consecutive driver stages. The delay element
`produces tWo or more pairs of complementary input signals
`in response to each input-signal transition, each successive
`signal pair being delayed by some amount relative to the
`previous signal pair. The pairs of complementary signals are
`conveyed to respective driver stages, so that each driver
`stage successively responds to the input-signal transition.
`The output terminals of the driver stages are connected to
`one another and to the output terminals of the differential
`driver. The differential driver thus responds to each input
`signal transition With increasingly poWerful ampli?cation.
`The progressive ampli?cation produces a corresponding
`progressive reduction in output resistance, Which reduces
`the noise normally associated With signal re?ection.
`Extendable and multi-stage differential ampli?ers in
`accordance With the invention can be adapted for use in
`PLDs. In one embodiment, adjacent pairs of IOBs are each
`
`45
`
`55
`
`65
`
`

`

`US 6,366,128 B1
`
`3
`provided With half of the circuitry required to produce LVDS
`signals. Adjacent pairs of IOBs can therefore be used either
`individually to provide single-ended input or output signals
`or can be combined to produce differential output signals.
`This summary does not limit the invention, Which is
`instead de?ned by the appended claims.
`
`BRIEF DESCRIPTION OF THE FIGURES
`
`FIG. 1 (prior art) illustrates an LVDS generator 100
`connected to an LVDS receiver 110 via a transmission line
`115.
`FIG. 2 (prior art) schematically depicts LVDS generator
`100 of FIG. 1
`FIG. 3 (prior art) is a Waveform diagram 300 depicting the
`signaling sense of the voltages appearing across termination
`load RL of FIGS. 1 and 2.
`FIG. 4 depicts an extensible differential ampli?er 400 in
`accordance With an embodiment of the invention.
`FIG. 5A is a schematic diagram of predriver 405 of FIG.
`
`10
`
`15
`
`4
`
`FIG. 5B is a schematic diagram of driver 415 of FIG. 4.
`FIG. 5C is a schematic diagram of extended driver 410 of
`FIG. 4.
`FIG. 6 depicts a multi-stage driver 600 in accordance With
`another embodiment of the invention.
`FIG. 7A schematically depicts a predriver 700 in Which a
`predriver is connected to delay circuit 605 of FIG. 6 to
`develop three complementary signal pairs.
`FIG. 7B schematically depicts differential-ampli?er
`sequences 610 and 615 and termination load 620, all of FIG.
`6.
`
`25
`
`FIGS. 8A and 8B schematically depict a programmable
`bias-voltage generator 800 in accordance With an embodi
`ment of the invention.
`
`35
`
`DETAILED DESCRIPTION
`
`FIG. 4 depicts an extensible differential ampli?er 400 in
`accordance With an embodiment of the invention. Ampli?er
`400 includes a predriver 405 connected to a pair of driver
`stages 410 and 415. The combination of predriver 405 and
`driver 415 operates as described above in connection With
`FIGS. 2 and 3 to convert the single-ended input on terminal
`DiIN into differential output signals on lines TXiA and
`TXiB. In accordance With the invention, driver 410 can be
`activated as needed to provide additional drive poWer. In one
`embodiment, drivers 410 and 415 reside Within a pair of
`adjacent programmable IOBs (collectively labeled 417) and
`lines TXiA and TXiB connect to the respective input/
`output (I/O) pads of the pair. This aspect of the invention is
`detailed beloW.
`The program state of a con?guration bit 420 determines
`Whether ampli?er 400 is enabled, and the program state of
`a second con?guration bit 425 determines Whether the driver
`stage of ampli?er 400 is extended to include driver 410. An
`exemplary con?guration bit is described beloW in connec
`tion With FIG. 8A.
`If bit 420 is programmed to provide a logic one on “enable
`differential signaling” line ENiDS, then predriver 405 and
`driver 415 function in a manner similar to that described
`above in connection With FIG. 2. If desired, the drive
`circuitry can be extended to include driver 410 by program
`ming bit 425 to provide a logic one on “extended differential
`signaling” line XiDS. The signals on lines XiDS and
`ENiDS are logically combined using an AND gate 430 to
`
`45
`
`55
`
`65
`
`4
`produce an “enable termination load” signal ENiT to driver
`415. This signal and its purpose are described beloW in
`connection With FIG. 5B.
`FIG. 5A is a schematic diagram of an embodiment of
`predriver 405 of FIG. 4. Predriver 405 includes a pair of
`conventional tri-state drivers 500 and 502. A conventional
`inverter 504 provides the complement of signal ENiDS.
`Ampli?er 400 is inactive When signals ENiDS and
`ENiDS/ are loW and high, respectively. These logic levels
`cause tristate drivers 500 and 502 to disconnect input
`terminal DiIN from respective tristate output terminals T1
`and T2. Signal ENiDS and its complementary signal
`ENiDS/ also connect terminals T1 and T2 to respective
`supply voltages VCCO and ground by turning on a pair of
`transistors 506 and 508. Thus, terminals T1 and T2 do not
`change in response to changes on input terminal DiIN
`When differential signaling is disabled. In the case Where
`ampli?er 400 is implemented using IOBs in a programmable
`logic device, ampli?er 400 may be disabled to alloW the
`IOBs to perform some other input or output function.
`Ampli?er 400 is active When signals ENiDS and
`ENiDS/ are high and loW, respectively. These logic levels
`cause tristate drivers 500 and 502 to connect input terminal
`DiIN to respective tristate output terminals T1 and T2.
`Signal ENiDS and its complementary signal ENiDS/ also
`disconnect terminals T1 and T2 from respective supply
`voltages VCCO and ground by turning off transistors 506
`and 508. Thus, terminals T1 and T2 change in response to
`signal DiIN When differential signaling is enabled.
`Tristate output terminals T1 and T2 connect to the respec
`tive input terminals of an inverting predriver 510 and a
`non-inverting predriver 512. Predriver 510 includes a pair of
`conventional inverters 514 and 516. Inverter 514 produces a
`signal D, an inverted and ampli?ed version of the signal on
`line T1; inverter 516 provides a similar signal to a test pin
`518. Predriver 512 includes three conventional inverters
`520, 522, and 524. Predriver 512 produces a signal D/, the
`complement of signal D. Inverter 524 provides a similar
`signal to a test pin 526.
`Each inverter Within predrivers 510 and 512 is a CMOS
`inverter in Which the ratios of the PMOS and NMOS
`transistors are as speci?ed. These particular ratios Were
`selected so that signals D and D/ transition simultaneously,
`or very nearly so. Different ratios may be appropriate,
`depending upon the process used to produce ampli?er 400.
`Adjusting layout and process parameters to produce syn
`chroniZed complementary signals is Within the skill of those
`in the art.
`As discussed above in connection With FIG. 4, ampli?er
`400 can be extended to include additional drive circuitry,
`Which may be needed to drive some loads While remaining
`in compliance With the LVDS Standard. Returning to FIG.
`5A, a pair of NOR gates 528 and 530 facilitates this
`extension by producing a pair of complimentary extended
`data signals DX and DX/ When signal XiDS/ is a logic Zero,
`indicating the extended driver is enabled. Extended-data
`signal DX is substantially the same as signal D, and
`extended data signal DX/ is substantially the same as signal
`D/. Signals DX and DX/ are conveyed to extended driver
`410, the operation of Which is detailed beloW in connection
`With FIG. 5C.
`FIG. 5B is a schematic diagram of driver 415 of FIG. 4.
`Driver 415 is similar to driver stage 205 of FIG. 2, like
`numbered elements being the same. Unlike driver 205,
`hoWever, driver 415 includes a programmable termination
`load 540. Further, load transistors 207 and 209 of FIG. 2 are
`
`

`

`US 6,366,128 B1
`
`5
`replaced With pairs of parallel transistors, so that transistors
`211 and 215 connect to VCCO via respective PMOS tran
`sistor 532 and 533, instead of via a single transistor 207, and
`transistors 213 and 217 connect to ground via respective
`NMOS transistors 534 and 535, instead of via a single
`transistor 209.
`Employing pairs of load transistors alloWs driver 415 to
`be separated into tWo similar parts 536 and 538, each
`associated With a respective one of terminals TXiA and
`TXiB. Such a con?guration is convenient, for example,
`When driver 415 is implemented on a PLD in Which termi
`nals TXiA and TXiB connect to neighboring I/O pins.
`Each part 536 and 538 can be implemented as a portion of
`the IOB (not shoWn) associated With the respective one of
`terminals TXiA and TXiB. Termination load 540 can be
`part of either IOB, neither IOB, or can be split betWeen the
`tWo. In one embodiment, transistor 542 is included in the
`IOB that includes part 536, and transistor 543 is included in
`the IOB that includes part 538.
`Programmable termination load 540 includes a pair of
`transistors 542 and 543, the gates of Which connect to
`terminal ENiT. As shoWn in FIG. 4, the signal ENiT is
`controlled through AND gate 430 by con?guration bits 420
`and 425. Termination load 540 is active (conducting) only
`When differential signaling is enabled in the non-extended
`mode. This condition is speci?ed When con?guration bit 420
`is set to a logic one and con?guration bit 425 is set to a logic
`Zero.
`Driver 415 includes a number of terminals that provide
`appropriate bias voltages. Terminals PBIAS and NBIAS
`provide respective bias levels establish the gain driver 415,
`and common terminals PCOM and NCOM conventionally
`establish the high and loW voltage levels on output terminals
`TXiA and TXiB. Driver 415 shares the bias and common
`terminals With extended driver 410 (See FIG. 5C).
`The bias levels PBIAS and NBIAS are important in
`de?ning LVDS signal quality. In one embodiment, NMOS
`transistors 534 and 535 are biased to operate in saturation to
`sink a relatively stable current, Whereas PMOS transistors
`532 and 533 are biased to operate in a linear region.
`Operating transistors 532 and 533 in a linear region reduces
`the output resistances of those devices, and the reduced
`resistance tends to dissipate signal re?ections returning to
`terminals TXiA and TXiB. Reduced re?ections translate
`into reduced noise, and reduced noise alloWs signals to be
`conveyed at higher data rates. Circuits for developing appro
`priate bias levels for the circuits of FIGS. 5A—7B are
`discussed beloW in connection With FIGS. 8A and 8B.
`FIG. 5C is a schematic diagram of one embodiment of
`extended driver 410 of FIG. 4. Extended driver 410 includes
`a pair of driver stages 544 and 546 and a programmable
`termination load 548. Driver stages 544 and 546 can be
`included, for example, in respective adjacent IOBs on a
`PLD. Termination load 548 can be part of either IOB, neither
`IOB, or can be split betWeen the tWo. The various terminals
`of FIG. 5C are connected to like-named terminals of FIGS.
`5A and 5B.
`Driver stage 544 includes a PMOS load transistor 550, a
`pair of NMOS differential-driver transistors 552 and 554
`having their gates connected to respective extended-driver
`input signals DX and DX/, a diode-connected PMOS tran
`sistor 556, and a PMOS transistor 558 connected as a
`capacitor 14 betWeen terminal VCCO and terminal PCOM.
`Transistors 550, 552, and 554 combined amplify the
`extended-driver signals DX and DX/ to produce an ampli
`?ed output signal on output terminal TXiA. In one
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`embodiment, transistor 556 is diode-connected betWeen
`terminals PCOM and VCCO to establish the appropriate
`level for line PCOM, Which is common to both drivers 410
`and 415. Finally, transistor 558 can be siZed or eliminated as
`desired to minimiZe noise on line PCOM. Driver stage 546
`is identical to driver stage 544, except that lines DX and DX/
`are connected to the opposite differential driver transistors.
`Consequently, the signals on output terminals TXiA and
`TXiB are complementary. Driver stages 544 and 546 thus
`supplement the drive strength provided by driver stage 415.
`As shoWn in FIG. 4, the extend-differential-signaling
`signal XiDS is a logic one When CBIT 425 is programmed.
`HoWever, programming CBIT 425 causes AND gate 430 to
`output a logic Zero, disabling termination load 532 of FIG.
`5B. Thus, programming CBIT 425 substitutes termination
`load 548 for termination load 532, thereby increasing the
`termination load resistance to an appropriate level. In one
`embodiment, the resistance of termination load 532 is
`selected so that the resulting output signal conforms to the
`LVDS Standard.
`FIG. 6 depicts a multi-stage driver 600 in accordance With
`another embodiment of the invention. Driver 600 includes a
`multi-stage delay circuit 605, a ?rst sequence of differential
`ampli?ers 610, a second sequence of differential ampli?ers
`615, and a termination load 620. For illustrative purposes,
`the ampli?ers of sequences 610 and 615 are referred to as
`“high-side” and “loW-side” ampli?ers, respectively. In dif
`ferent embodiments, each ampli?er sequence 610 and 615
`can be implemented as a portion of the IOB (not shoWn)
`associated With the respective one of terminals TXiA and
`TXiB. Termination load 620 can be part of either IOB,
`neither IOB, or can be split betWeen the tWo.
`Delay circuit 605 receives a pair of complementary sig
`nals D and D/ on a like-named pair of input terminals. A
`sequence of delay elements—conventional buffers 625 in
`the depicted example—provides a ?rst pair of delayed
`complementary signals D1 and D1/ and a second pair of
`delayed complementary signals D2 and D2/.
`Sequence 610 includes three differential ampli?ers 630,
`631, and 632, the output terminals of Which connect to one
`another and to output terminal TXiA. The differential input
`terminals of each of these high-side ampli?ers connect to
`respective complementary terminals from delay circuit 605.
`That is, the non-inverting (+) and inverting (—) terminals of
`differential ampli?er 630 connect to respective input termi
`nals D and D/, the non-inverting and inverting terminals of
`differential ampli?er 631 connect to respective input termi
`nals D1 and D1/, and the non-inverting and inverting ter
`minals of differential ampli?er 632 connect to respective
`input terminals D2 and D2/. When the signal on terminal D
`transitions from loW to high, each of ampli?ers 630, 631,
`and 632 consecutively joins in pulling the voltage level on
`terminal TXiA high as the signal edges on terminals D and
`D/ propagate through delay circuit 605. Conversely, When
`the signal on terminal D transitions from high to loW, each
`of ampli?ers 630, 631, and 632 consecutively joins in
`pulling the voltage level on terminal TXiA loW.
`Sequence 615 includes three differential ampli?ers 634,
`635, and 636, the output terminals of Which connect to one
`another and to terminal TXiB. Sequence 615 is similar to
`sequence 610, except that the differential input terminals of
`the various loW-side differential ampli?ers are connected to
`opposite ones of the complementary signals from delay
`circuit 605. Thus, When the signal on terminal D transitions
`from loW to high, each of ampli?ers 634, 635, and 636
`consecutively joins in pulling the voltage level on terminal
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`US 6,366,128 B1
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`7
`TXiB loW as the signal edges on terminals D and D/
`propagate through delay circuit 605, and When the signal on
`terminal D transitions from high to loW, each of ampli?ers
`634, 635, and 636 consecutively joins in pulling the voltage
`level on terminal T'XiB high.
`Driver stage 600 is similar to driver stage 415 of FIGS. 4
`and 5A, except that driver stage 600 progressively increases
`the drive strength used to provide ampli?ed signals across
`termination load 620, and consequently progressively
`reduces the output resistance of driver stage 600. Progres
`sively reducing the output resistance of ampli?er 600
`reduces the amplitude of re?ected signals. This effect, in
`turn, reduces the noise and increases the useable data rate of
`the LVDS circuitry. While illustrated as having three driver
`stages, other embodiments of ampli?er 600 include more or
`feWer stages. FIG. 7A schematically depicts a predriver 700
`in Which predriver 405, detailed in FIG. 5A, is connected to
`delay circuit 605 of FIG. 6 to develop the three comple
`mentary signal pairs (e.g., D and D/) of FIG. 6. The various
`elements of predriver 405 are described above in connection
`With FIG. 5A, like-numbed elements being identical. In one
`embodiment, each buffer 625 is an instance of non-inverting
`delay circuit 512. FIG. 7B schematically depicts differential
`ampli?er sequences 610 and 615 and termination load 620,
`all of FIG. 6. The differential ampli?ers in sequences 610
`and 615 are substantially identical, eXcept the D and D/ input
`terminals are reversed. The folloWing description is limited
`to a single differential ampli?er (630) for brevity. Differen
`tial ampli?er 630 includes a PMOS load transistor 700, an
`NMOS load transistor 705, and a pair of active transistors
`710 and 715 having their respective gates connected to data
`inputs D and D/. One embodiment of ampli?er 400 of FIG.
`4 employs driver stage 600 in place of driver 415 (detailed
`in FIG. 5B). Ampli?er sequence 610 may include a capacitor
`725 betWeen PCOM and VCCO, and ampli?er sequence 615
`may include a capacitor 730 connected betWeen NCOM and
`ground. These capacitors can be siZed to minimiZe noise.
`FIGS. 8A and 8B schematically depict a programmable
`bias-voltage generator 800 in accordance With an embodi
`ment of the invention. A key 802 in the bottom right-hand
`corner of FIG. 8A shoWs the relative arrangement of FIGS.
`8A and 8B.
`The portion of generator 800 depicted in FIG. 8A may be
`divided into three general areas: bias-enable circuitry 804,
`NBIAS pull-up circuitry 806, and NBIAS pull-doWn cir
`cuitry 808. As their respective names imply, bias-enable
`circuitry 804 determines Whether bias generator 800 is
`active, NBIAS pull-up circuitry 806 can be used to raise the
`NBIAS voltage level, and NBIAS pull-doWn circuitry 808
`can be used to reduce the NBIAS voltage level. The NBIAS
`pull-up and pull-doWn circuitry are programmable to alloW
`users to vary the NBIAS voltage as desired.
`Bias-enable circuitry 804 includes a con?guration bit
`(CBIT) 810, an inverter 812, a PMOS transistor 814, and, in
`FIG. SE, a PMOS transistor 815 and a pair of NMOS
`transistors 816 and 817. CBIT 810 is conventional, in one
`embodiment including an SRAM con?guration memory cell
`818 connected to a level-shifter 820. Level-shifter 820 is
`used because bias generator 800 is a portion of the output
`circuitry of a PLD, and operates at higher voltage (e.g., 3.3
`volts) than the core circuitry (e.g., 1.5 volts) of the PLD:
`level-shifter 820 increases the output voltage of SRAM cell
`816 to an appropriate voltage level. Some embodiments that
`employ loWer core voltages use thicker gate insulators in the
`transistors of the I/O circuitry. The gate insulators of differ
`ing thickness can be formed using a conventional dual-oxide
`process. In one embodiment in Which the circuits depicted in
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`FIGS. 5A—8B are part of the output circuitry of a PLD, each
`of the depicted devices employs relatively thick gate insu
`lators.
`Generator 800 is activated by programming SRAM cell
`818 to include a logic one, thereby causing bias-enable
`circuitry 804 to output a logic one on line BIAS. This logic
`one connects high-supply-voltage line HiSUP to supply
`voltage VCCO through transistor 814 and disconnects line
`PBIAS from VCCO to enable line PBIAS to carry an
`appropriate bias voltage. The inverted signal BIAS/ from
`inverter 812, a logic Zero When active, disconnects lines
`NBIAS and NGAT E from ground, thereby alloWing those
`lines to carry respective bias voltages. The logic levels on
`lines PBIAS and NBIAS are one and Zero, respectively,
`When SRAM cell 818 is set to logic Zero.
`NBIAS pull-up circuitry 806 has an input terminal VBG
`connected to a conventional band-gap reference, or some
`other suitable voltage reference. The voltage level and line
`VBG turns on a PMOS transistor 822 that, in combination
`With diode-connected transistors 824 and 826, produces bias
`voltage levels on lines NGAT E and NBIAS. Terminal VBG
`also connects to a pair of transmission gates 828 and 830,
`each consisting of NMOS and PMOS transistors connected
`in parallel. The transmission gates are controlled by con
`?guration bits similar to CBIT 810. For example, transmis
`sion gate 828 can be turned on by programming CBITiA to
`contain a logic one. The logic one produces a logic one on
`line A and, via an inverter 834, a logic Zero on line Al.
`Transmission gate 828 passes the reference voltage on line
`VBG to the gate of a PMOS transistor 836, thereby reducing
`the resistance betWeen VCCO and line NBIAS;
`consequently, the voltage level on line NBIAS rises. Tran
`sistor 838 can be turned on and both of transmission gate
`828 and transistor 836 can be turned off by programming
`CBITiA to contain a logic Zero. Transmission gate 830
`operates in the same manner as transmission gate 828, but is
`controlled by a different CBIT (CBITiB) and an associated
`inverter. One or both of transmission gates 828 and 830 can
`be turned on to raise the voltage level on line NBIAS.
`NBIAS pull-doWn circuitry 808 includes a pair of pro
`grammable pull-doWn circuits 840 and 842 that can be
`programmed independently or collectively to reduce the bias
`voltage on terminal NBIAS. Pull-doWn circuits 840 and 842
`Work the same Way, so only circuit 840 is described.
`Pull-doWn circuit 840 includes three transistors 844, 846,
`and 848. The gates of transistors 844 and 846 connect to
`terminals C and C/, respectively, from a con?guration bit
`CBITiC and an associated inverter 849. When CBITiC is
`programmed to contain a logic Zero, transistors 844 and 848
`are turned off, isolating line NBIAS from