EIA TIA圃 b4句 96 麟塁 323勾b日日 057-3弓79 a匂？盤翠
`
`ANSI/TIAIEIA-644-1995
`Approved: November 15, 1995
`
`TIA/EIA
`STANDARD
`
`Electrical Characteristics of Low
`Voltage Differe阻tialSig且ali11g(L VDS)
`Interface Circ日its
`
`MARCH 1996
`
`TIA/EIA蜘 644
`
`TELECOMMUNICATIONS INDUSTRY ASSOCIATION
`
`

`

`E工A T工A回 b句句 96 盤蜜 323切らむ口 0573弓8日 569
`
`NOTICE
`
`百 A/EIAEn~neering Stan也rds朗 dPublications釘 edesigned to serve the public interest through
`ぬ凶朗自1gmisunderstandings betw附 1manufacturers and purchasers, facilitating interchangeability
`and improvement of products, and assisting the purchaser in selecting and obt垣ningwith minimum
`delay the pro戸rproduct for his particular need. Existence of suぬ Standardsand Publications shall
`not in any resp切 tprecl叫 eany member or nonmember of TIA/EIA合・ommanuぬcturingor selling
`products not confonning to such Standards and Publications, nor shall the existence of釦 ch
`Standards and Publications preclude their voluntary use by出.oseother than TIA厄IAmembers,
`whether the standard is to be used either domestically or internationally.
`
`Standards and Publications are adopted by TIA/EIA in accordance wi出 theAmerican National
`Standards Institute (ANSI) pate凶 policy.By such action, TIA厄IAdoes not assume any liability
`to any patent owner, nor does it邸 sumeany obligation whatever to parties adopting the Standard
`or Publication.
`
`百語sS泊n伽rddc踏 notp山-portto addr回 sall鵠 fetyproblems associated with its use or all applicable
`r噂 血.toryr叫uirements.It is the respo凶 bilityof the user of this Standard to establish appropriate
`d町 and岡 地 practicesand to determine the applicability of re思dato守 limitationsbeおお itsuse.
`
`σrom S泊ndardsPropo絹 1No. 3357, form叫atedunder the cognizance of theτ'R-30.2 Subcommittee
`onD1主・DCEint町faces.)
`
`Published by
`
`cTELECOMMUNICATIONS以 DUSTRYASSOCIATION 1996
`Standards and Technology Department
`2500 Wilson Boulevard
`Arlington, VA 22201
`
`PRICE: Please ref er to current
`Catalog of EIA, JED EC, and TIA STANDARDS and ENGINEERING PUBLICATIONS
`。rcall Global Engineering Documents, USA and Canada (1・800-854・7179)
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`仰吋
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`・n
`削
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`MmN
`
`AU
`
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`

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`＼）／
`
`E工A TIA輔 b勾勾可 b 麟調ヨ Eヨ句 600 057ヨ可aL 旬。T5 欝富
`
`TIN日A“644
`
`監しECTRICALCHARACTERISTICS OF LOW VOLT A窃藍
`
`。IFFERENTIAL SIGNALI髄G (LVDS)
`
`INTERFACE CIRCUIτs
`
`CONTENTS
`
`Page
`
`1 SCOPE .....................................................................・・・・・・・・・・”・ e・・・・・・・・・・・.......................1
`
`2 NORMAγIVE REFERENCεs ....・ H ・....・ H ・−…..........................................................2
`
`3 DEFINITIONS, ABBREVIATIONS, AND SYMBOLS ....・ H ・...・ H ・H ・.....・ H ・.......・... 3
`
`3.1
`
`3.2
`
`3.3
`
`3.4
`
`3.5
`
`Data signaling rate ....・ H ・....・ H ・−….................................................................... 3
`
`DTE. ...・ H ・.....・ H ・...・ H ・.....・ H ・....・ H ・...・ H ・−−…….....・ H ・・・・・・・・・a・..........・ H ・−…....・ H ・...・ H ・−…... 3
`
`DCE .....・ H ・....・ H ・…....・ H ・−−…....・ H ・........・ H ・....・ H ・...・ H ・.....・ H ・....・ H ・−…...・ H ・−・…....・ H ・−…. 3
`
`LVDS ........・ H ・−…....・ H ・....・ H ・−−‘・ H ・H ・...・ H ・.....・ H ・−…....・ H ・....・ H ・...・ H ・...・ H ・.....・ H ・....・ H ・. 3
`
`Star （＊）・・ H ・H ・−…...・ H ・.....・ H ・−…・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・‘．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．． 3
`
`4 APPLICABIし昨Y....・ H ・....・ H ・....・ H ・....・ H ・...・ H ・−…・・ H ・H ・....・ H ・H ・....・ H ・.....・ H ・....・ H ・....・ H ・.... 4
`
`4.1
`
`4.2
`
`General applicability ......・ H ・.....・ H ・−−…… H ・H ・...・ H ・−−…...・ H ・.....・ H ・−−…… H ・H ・...・ H ・−−‘ 4
`
`Data signaling rate ....・ H ・...・ H ・−・・・・・・・・・・・・・・・・・・ e・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・........... 5
`
`5 ELECTRICAL CHARACTERISTICS ........・ H ・....・ H ・−−−…....・ H ・−…・・ H ・H ・....・ H ・....・ H ・− 6
`
`5.1
`5.1.1
`5.1 .2
`5.1 .3
`5.1 .4
`
`5.2
`5.2.1
`5.2.2
`
`5.2.3
`5.2.4
`
`Generator characteristics ...・ H ・....・ H ・−−…....・ H ・...・ H ・....・ H ・−−・・ H ・H ・...・ H ・−…...・ H ・− 7
`γest termination measurements ...・・ H ・H ・...・ H ・H ・H ・...・ H ・...・ H ・...・ H ・....・ H ・−−−…． 8
`Short-circuit measurements................................................................... 9
`Output signal waveform ...… H ・H ・＂..・ H ・...............・ H ・.....・ H ・.....・ H ・H ・H ・.....・ H ・＇＂ 10
`Dynamic output signal balance ...・ H ・....・ H ・−−−… H ・H ・...・ H ・−−…...・ H ・−−…...・ H ・... 11
`
`Load characteristics ...・ H ・H ・H ・...・ H ・.....・ H ・...・ H ・...・ H ・−・…...・ H ・....・ H ・....・ H ・−−…...・ H ・... 12
`Receiver input current-voltage measurements .......・ H ・...・ H ・H ・...・ H ・−…. 12
`Ter開inatingreceiver input current-voltage measurements
`and input impedance measurements.…… H ・H ・....・ H ・...・ H ・....・ H ・............. 1 3
`Receiver input sensitivity measurements ...・ H ・−…...・ H ・...・ H ・....・ H ・...・ H ・.... 15
`Media termination ....・ H ・−…・・......・ H ・...・ H ・H ・.....・ H ・.......・ H ・....・ H ・−−−…....・ H ・−−−… 17
`
`

`

`EIA TIA輔 b44 9b 麟襲 323匂bOO 口573司82 331 盤謬
`
`γIA/EIA-644
`
`co持TE闘TS
`
`Pa笥e
`
`5.3
`5.3.1
`5.3.1.1
`5.3.1.2
`5.3.1.3
`5.3.2
`5.3.3
`
`Interconnecting media electrical characteristics ....・ H ・H ・H ・−… H ・H ・−…...・ H ・... 18
`Cable media .....・ H ・...・ H ・........・ H ・−…＂＂・ H ・.........…...・ H ・−−…...・ H ・.... 18
`Maximum dc loop resistance ...・ H ・−…...・ H ・−… H ・H ・....・ H ・−… H ・H ・−… H ・H ・... 18
`Characteristic impedance ..・ H ・−…....・ H ・−−… H ・H ・...・ H ・...・ H ・−−…… H ・H ・−… 18
`Additional parameters ....・ H ・...・ H ・...・ H ・−…....・ H ・....・ H ・−…......・.......・ H ・...・... 18
`PC Board trace media ....… H ・H ・....・ H ・...・ H ・...・ H ・H ・H ・. . ...・ H ・.....・ H ・.....・ H ・.. 18
`Other media.............................................................................................. 18
`
`5.4
`5.4.1
`5.4.2
`5.4.3
`
`System paramete陪....・ H ・........・ H ・...・ H ・.....・ H ・...・ H ・....・ H ・.....・ H ・....・ H ・−…........・ H ・... 19
`Multiple receiver operation ....・ H ・H ・......・ H ・・・・・・・・ H ・...・ H ・...・・ H ・H ・−−…...・ H ・−−…・・ 19
`Failsafe operation ..…....・ H ・....・ H ・.....・ H ・...・ H ・....・ H ・.......・ H ・....・ H ・H ・H ・−−−・・ H ・H ・...マ 20
`Total load limit.......................................................................................... 20
`
`6 ENVIRONMENTAL CONSTRAINTS ....・ H ・....・ H ・....・ H ・....・ H ・....・ H ・...・ H ・....・ H ・＂...・ H ・. 21
`
`7 CIRCUIT PROTECTION ....・ H ・−…....・ H ・＂＂・ H ・...・ H ・−…‘ H ・H ・....・ H ・....・ H ・....・ H ・.........・ H ・...22
`
`8 OPTIONAL GROUNDING AR再ANGEMENTS........・ H ・...・ H ・....・ H ・.....・ H ・−…....・ H ・. 23
`
`8.1
`8.1. 1
`8.1.2
`
`Signal common ....・ H ・....・ H ・.........・ H ・........・ H ・....・ H ・....・ H ・−…....・ H ・−…… H ・H ・−… H ・H ・.. 23
`Configuration “A’：..................................................................................... 23
`Configuration “B’＇ .......................................・・・・・・・・・・・・・・・・・・・・・・・・・・・・・...; .............. 24
`
`8.2
`
`Shield ground.……....・ H ・...・ H ・−…・...........凶 H ・H ・.....・ H ・....・ H ・........・ H ・...・ H ・−…....・ H ・. 24
`
`ANNEX A (informative) ....・ H ・....・ H ・....・ H ・....・ H ・−…....・ H ・...・ H ・−…....・ H ・...・ H ・−・・ H ・H ・...・ H ・.....・ H ・−−− 25
`
`Interconnecting cable .....・ H ・...・ H ・.....・ H ・−−…...・ H ・....・ H ・...・ H ・...・ H ・............…....・ H ・.. 25
`Length ....・ H ・....・ H ・...・ H ・.........・ H ・−…...・ H ・・・・・・・ H ・−…...・ H ・.................…...・ H ・−−… 25
`Typical cable characteristics ...・ H ・....・ H ・...・ H ・H ・......・ H ・.....・ H ・−−…...・ H ・.....・ H ・.. 26
`Parallel interface cable..................................................................... 26
`Parallel cable, physical characteristics ...・ H ・...・ H ・..・ H ・H ・−−…...・ H ・. 26
`Parallel cable, electrical characteristics .....・ H ・・・・・・・・・・・・・・・・・ H ・−−…・ 26
`Serial interface cable ....・ H ・....・ H ・....・ H ・....・ H ・....・ H ・−…....・ H ・...・ H ・.....・ H ・−… 27
`Serial cable, physical characteristics ...・ H ・..・ H ・H ・.....・ H ・....・ H ・−….. 27
`Serial cable, electrical characteristics ...・ H ・H ・.....・ H ・H ・H ・.....・ H ・... 27
`Cable termination ..・ H ・−…...・ H ・..................・ H ・...・ H ・−…...・ H ・...・ H ・....・ H ・H ・−−−−… 27
`
`Cable length vs. data signaling rate guidelines .......・ H ・....・ H ・........・ H ・.....・ H ・. 28
`
`Co-directional and contra岨 directionaltiming information....................... 28
`
`ii
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`

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`EI A T工A畑 山 勾 司 b 障調 323匂600 0573983 27品 盤
`
`CONTENτs
`
`γIA/EIA-644
`
`Page
`
`ANNξX B (informativeト．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．‘ 29
`
`8.1
`8.1 .1
`8.1.2
`8.1.3
`
`Compatibility with other interface standards ......・ H ・−・...・ H ・H ・−−……...・ H ・........ 29
`Generator output levels ......・ H ・−−…...・ H ・.....・ H ・......・ H ・.....・ H ・....・ H ・...・ H ・......・ H ・. 29
`Compatibility with IEEE 1596.3 ...・ H ・H ・H ・−−…...・ H ・.....・ H ・....・ H ・...・ H ・.....・... 31
`Compatibility with other interface standards ...・ H ・−−−…・….....・ H ・.....・ H ・.... 31
`
`8.2
`
`8.3
`
`8.4
`
`Power dissi戸ationof generators ....・ H ・...・ H ・−…....・ H ・...・ H ・−……...・ H ・...・ H ・H ・..... 31
`
`Re陥tedTINEIA standards ....・ H ・−−… H ・H ・−…......・ H ・......・ H ・−−…… H ・H ・−…....・ H ・−… 32
`
`Other related interface standards ...・ H ・.....・ H ・−…・ H ・H ・.....・ H ・… H ・H ・....・ H ・....・ H ・. 32
`
`
`−1・1・1
`
`
`

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`EIA TIA輔ら匂勾 96 鶴喜 323匂600 0573弓＆勾 1 G勾
`
`TIAIEIA-644
`
`Figure
`
`Title
`
`Page
`
`し1STOF FIGURES
`
`Figure 1
`Figure 2
`Figure 3
`Figure 4
`Figure 5
`Figure 6
`Figure 7
`Figure 8
`Figure 9
`Figure 10
`Figure 11
`Figure 12
`Figure 13
`Figure 14
`Figure 15
`Figure 16
`Figure 17
`Figure 18
`Figure 19
`Figure 8.1
`
`Application ofしVOSinterface circuits ...…...・ H ・.....・ H ・....・ H ・...・ H ・.....・ H ・−−… 4
`L VOS interface circu社・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・日、 6
`Signaling sense ....・ H ・H ・......・ H ・−…....・ H ・............・・ H ・H ・−−−−…..............・ H ・−…...・ H ・− 7
`Test termination measurements ...・ H ・....・ H ・...・ H ・−…....・ H ・−…....・ H ・...・ H ・... 8
`Short-circuit measurements to circuit common ...…...・ H ・.........・ H ・H ・.....9
`Short-circuit measurements ....・ H ・H ・H ・−…....・ H ・−…....・ H ・....・ H ・....・ H ・H ・a・....・ H ・9
`Output signal waveform.…....・ H ・....・ H ・....・ H ・....・ H ・....・ H ・−” H ・H ・....・ H ・....・ H ・...・ H ・10
`Dynamic output signal balance waveform ...・ H ・...・ H ・....・ H ・・・・・・・ H ・......・ H ・... 11
`Receiver input current咽 voltagemeasurements ...・ H ・.....・ H ・.....・ H ・.....・ H ・..12
`T erminat1ng receiver input current-voltage measurements ......・ H ・....13
`Terminating receiver input current vs. input voltage range ......・ H ・−−… 14
`Receiver input sensitivity measurements ...・ H ・.....・ H ・.....・ H ・......・ H ・...・ H ・....15
`Receiver input sensitivity te剖 circu託......................................................16
`Point-to-point application with external termination ...…， H ・H ・−−…...・ H ・.. 17
`Point-to-point application with internal termination .........・ H ・...・ H ・H ・H ・.. 17
`Multiple receiver operation備 multidropapplication ......・ H ・.....・ H ・...・ H ・.. 19
`Uncomplicated point-to・pointapplication ....・ H ・...・ H ・H ・....・ H ・.....・ H ・....・ H ・..20
`Optional grounding arrangements” configuration ”A・＇.....・ H ・−… H ・H ・..23
`Optional grounding arrangements働 configuration”B’’ H ・H ・H ・H ・...・ H ・−… 24
`Generator output levels ....・ H ・....・ H ・....・ H ・....・ H ・...・ H ・.....・ H ・...・ H ・.........・ H ・...・ H ・.30
`
`LIST OF TABLES
`
`Table
`
`Title
`
`Page
`
`Table 1
`
`γable 2
`
`Receiver input current-voltage measurements for
`terminating receivers ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・.........................................13
`Receiver minimum and maximum operating voltages ....・ H ・...・ H ・...・ H ・.16
`
`iv
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`

`

`EIA TIA圃 b匂勾 96 璽鵠 ヨ23勾600 0573985・日句口鶴欝
`
`TIA/EIA司 644
`
`)
`
`FO開EWORD
`
`(This foreword is not pa片ofthis Standard)
`
`This Standar? was formulated under the cognizance of TIA Subcommittee TR-30.2 on
`Data Transmission Interfaces.
`
`This Standard specifies low voltage differential signaling （しVOS)generators and
`receivers capable of aper副ingat data signaling rates up to 655 Mbit/s, devices may be
`designed for data signaling rates less than 655 Mbit/s, 100 Mbit/s for example, when
`economically required for that application.
`
`This Standard was developed in response to a demand from the data communications
`community for a general purpose high speed interface standard for use in high
`throughput OTιDCE interfaces.
`
`The voltage levels specified in this Standard were specified such that maximum
`flexibility would be provided, while providing a low power, high speed, differential
`interface. Generator output characteristics are independent of power supply, and may
`be designed for standard +5 V, +3.3 V or even power supplies as low as +2.5 V.
`Integrated circuit technology may be BiCMOS, CMOS, or GaAs technology. The low
`voltage (330 mV) swing limits power dissipation, while also reducing radiation of EMI
`signals. Differential signaling provides multiple benefits over single鋼 endedsignaling,
`notably common mode rejection, and magnetic canceling.
`
`τhe de electrical levels are similar to electrical levels described in the IEEE 1596.3
`standard, and will inter-operate at ce吋aindata signaling rates.
`
`This Standard includes two annexes, both are informative only. Annex A provides
`guidelines for application, addressing data signaling rate and cable length issues.
`Annex B provides comparison information with other interface standards, and
`references to this Standard.
`
`V
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`

`

`TIA/EIA欄 644
`
`EIA TIA四 64句 可b 盤塁審 323句600 0573986 T87 麟審
`
`BLANK PAG歪
`
`ノ
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`VI
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`

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`EIA TIA-6匂匂 96 麟璽 323句60日 日573987 弓るヨ欝襲警
`
`TIA/EIA・644
`
`1 SCOPE
`
`（＼
`
`This Standard specifies the electrical characteristics of low voltage differential
`signaling interface circuits, normally implemented in integrated circuit technology, that
`may be employed when s予ecifiedfor the interchange of binary signals between:
`Data Terminal Equipment (DTE) and Data Circuit働 TerminatingEq~ipment (DCE),
`Data Terminal Equipment (DTE) and Data Terminal Equipment (DT巨），
`or in any point-to-point interconnection of binary signals between equipment.
`
`The interface circuit includes a generator connected by a balanced interconnecting
`media to a load consisting of a termination impedance and a receiver(s}. The interface
`configuration is an uncomplicated point寸0・point interface. The electrical
`characteristics of the circuit are specified in terms of required voltage, and current
`values obtained from direct measurements of the generator and receiver (load)
`components at the interface points.
`
`The logic function of the generator and the receiver is not defined by this Standard, as
`it is application dependent. The generators and receivers may be inverting, non-
`inverting, or may include other digital blocks such as paralleトto”serialor serial-to-
`parallel converters to boost the data signaling rate on the interchange circuit as
`required by the application.
`
`Minimum performance requirements for the balanced interconnecting media are
`furnished. Guidance is given in annex A, A.2 with respect to limitations on data
`signaling rate imposed by the parameters of the cable length, attenuation, and
`crosstalk for individual installations for a typical cable media interface.
`
`It is intended that this Standard will be referenced by other standards that specify the
`complete interface (i.e., connector, pin assigriments, function) for applications where
`the electrical characteristics of a low voltage differential signaling interface circuit is
`required. This Standard does not specify other characteristics of the DTE-DCE
`interface (su~h as signal qりality,protocol, bus structure, and/or timing) essential for
`proper operation across the interface.
`
`When this Standard is referenced by other standards or specifications, it should be
`noted that certain options are available. The戸reparerof those standards and
`specifications must determine and specify those optional features that are required for
`that application.
`
`

`

`E工A TIA田 b句”可 b 麿翠 323叫b日日日573守88 85T 麗翠
`
`TIAIEIA‘644
`
`2 NO詞糊ATIV監 R藍FER臨NCES
`
`The following Standard contains provisions which, through reference in this text,
`constitute provisions of this Standard. At the time of publication, the edition indicated
`was valid. All standards are subject to revision, and paはiesto agreements based on
`this Standard are encouraged to investigate the possibility of applying the most recent
`edition of the standard indicated below. ANSI and TIA maintain registers of currently
`valid national standards published by them.
`
`ANSI/TIA/El A・422・B-1994 Electrical Characteristics of Balanced Voltage Digital
`Interface Circuits
`
`EIA・485 Standard for Electrical Characteristics of Generators and Receivers for Use
`的 BalancedDigital Mutt，伊ointSystems
`
`ANSI/T凶／EIA・612・1993 Electrical Characteristics for an Interface at Data Signaling
`Rates up to 52 Mbi.ぬ
`
`／
`
`2
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`

`

`E工A T工A回 b4勾 9b 盤塑 323句b[J[J 日573弓8弓 7・96 墜塁審
`
`TIA/EIA-644
`
`3 DEFI詞ITIONS, SY蹴臨OLS AND ABBREVIATIONS
`
`For the purposes of this Standard, the following definitions, symbols and abbreviations
`apply:
`
`3.1 Data signaling rate
`
`Data signaling rate, expressed in the units biVs (bits per second), is the significant
`parameter. It may be different from the equipment’s data transfer rate, which employs
`the same units. Data signaling rate is defined as 1/tui where tui is the minimum
`interval between two significant instants.
`
`3.2 DT震
`
`Data Terminal Equipment
`
`3.3 DCE
`
`Data Circuit-Terminating Equipment
`
`3.4 LVDS
`
`Low Voltage Differential Signaling
`
`3.5 Star （つ
`
`Star (*) -represents the opposite input condition for a parameter. For example, the
`symbol Q represents the receiver output state for one input condition, while Q*
`repr~sents the output state for the opposite input state.
`
`3
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`

`

`ιIA TIA咽 b峠持 可b 盤鐙 jゴ己 3斗bOO O!:J.r'.3守可 U 時08 露麹
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`TIA/EIA幽 644
`
`4 APPLICABILITY
`
`4.1 General applicability
`
`The provisions of this Standard may be applied to the circuits employed at the
`interface between equipments where information being conveyed is in the form of
`binary signals.
`
`Typical points of applicability for this Standard are depicted in figure 1.
`
`D C E
`
`。T
`
`E
`
`B
`
`8
`
`しegend:
`DTE = Data Terminal Equipment
`DCE = Data Circuit-termination Equipment
`G = Generator
`R出 Receiver
`B詰 Balancedinterconnecting media
`
`Figure 1・.Application of L VOS interface circuits
`
`The LVDS interface is intended for use where any of the following conditions prevail:
`
`a. The data signaling rate is too great for effective unbalanced (single-
`ended) operation.
`
`b. The data signaling rate exceeds the capability of TIA/EIA・422噂 B,
`EIA”485, or TIA/EIA-612 balanced (differential) electrical interfaces.
`
`c. The balanced interconnecting media is exposed to extraneous noise
`sources that may cause an unwanted voltage up to ±1 V measured
`differentially between the signal conductor and circuit common at the
`load end of the cable with a 50 n resistor substituted for the generator.
`
`d. It is necessary to minimize electromagnetic emissions and interference
`with other signals.
`
`e. Inversion of the signals may be required; e.g., plus MARK to minus
`MARK may be obtained by inverting the balanced interconnecting media.
`
`4
`
`

`

`EIA TIA圃 b匂H 96 盤翠 323勾600 0573苛苛 3 3句句麗翠
`
`TIA/EIA網 644
`
`4.2 Data signaling rate
`
`The L VOS interface circuit will normally be utilized on data and timing, or control
`circuits where the data signaling rate is up to a recommended maximum limit of
`655 Mbit/s. This limit is determined by the generator transition time characteristics, the
`media characteristics, and the distance between the generator and the load. Certain
`applications may impose a different (lower or higher) limit for the maximum data
`signaling rate. This may be accomplished by specifying a りifferentminimum generator
`transition time specification, a different percentage of transition time vs. unit interval at
`the load, or by a different assumption of the maximum balanced interconnecting media
`signal distortion which is length dependent.
`
`The theoretical maximum limit is calculated at 1 .923 Gbit/s, and is derived from a
`calculation of signal transition time at the load assuming a loss-less balanced
`interconnecting media. The recommended signal transition time (tr or tf) at the load
`should not exceed 0.5 of the unit interval to preserve signal quality. This Standard
`specifies that the transition time of the generator into a test load be 260 ps or slower.
`Therefore, with the fastest generator transition time, and a loss鵬 less balanced
`interconnecting media, and applying the 0.5 restriction, yields a minimum unit interval
`of 520 ps or 1.923 Gbit/s theoretical maximum data signaling rate.
`
`NOTES
`1・655Mbit/s is the maximum data signaling rate for a serial channel, and
`employing a parallel bus structure (4, 8, 16, 32, etc. 帽 buswidth) can easily
`extend the obtainable equivalent bit rate into the Gbit/s range.
`
`2・ The recommended maximum data signaling rate is derived from a
`calculation of signal transition time at the load. For example, if a cable media is
`selected, a maximum signal rise time degradation is assumed to be 500 ps,
`since cables are not loss-less (500 ps represents a typical amount of rise time
`distortion on 5 meters of cable media). Therefore, allowing a 500 ps
`degradation of the signal in the interconnecting cable yields a 760 P.S (fastest)
`signal at the load. Therefore, with the fastest generator transition time, and a
`cable with only 500 ps of signal degradation (transition time), and applying the
`0.5 restriction, yields a minimum unit interval of 1.520 ns or 655 Mbit/s
`recommended maximum data signaling rate.
`
`Generators and receivers meeting this Standard need not operate over the entire data
`signaling rate range specified. They may be designed to operate over narrower
`ranges that satisfy more economically specified applications, for example at lower data
`
`signaling rates. When a generator is limited to a narrower rang。of data si9naling
`
`rates, the transition time of the generator may be slowed accordingly to limit noise
`generation. For example, at 100 Mbit/s the generator’s transition time should be in the
`range of 500 ps to 3 ns (5% to 30% of the unit interval), and the signal transition time at
`the load should not exceed 5 ns (50% of the unit interval).
`
`While a restriction of maximum cable length in not specified, recommendations are
`given on how to determine the maximum data signaling rate for a typical cable media
`application ( see A.2).
`
`5
`
`

`

`EIA TIA輔ら勾匂 96 璽韓亀 3234600 口573992 280
`
`TIA/EIA駒 644
`
`5 ELECTRICAL CHARACTERISTICS
`
`γheしVOSinterface circuit is shown in figure 2. The circuit consists of three pa吋s:the
`generator (G), the balanced interconnecting media, and the load.γhe load is
`composed of a termination impedance and a receiver(s) (R). The receiver may
`incorporate the termination impedance internal to the Integrated Circりitpackage. The
`electrical characteristics of the generator and receiver are specified in terms of direct
`electrical measurements while the balanced interconnecting media is described in
`terms of its electrical characteristics.
`
`...-1可
`BALANCED
`INTERCONNECTING
`MEDIA
`
`LOAD
`
`...-)
`
`可 MEDI；：：可 RECEIVER
`
`I I:> ~A
`
`:B
`
`) TERMINATION
`
`［.ふ弘 I
`
`ヂ
`
`:B’
`
`」＿c
`
`Vcpd
`
`c’
`
`Legend:
`G = Generator
`A= Generator interface point
`B = Generator inte吋acepoint
`C = Generator circuit common
`ZT = Termination impedance
`Vcpd = Common potential difference
`
`R = Receiver
`A’出 Receiverinterface point
`B’m Receiver interface point
`C' = Receiver circuit common
`
`Figure 2・LVDS interface circuit
`
`6
`
`

`

`EIA γ工A-6句” 司b 盤露 323句b日D 0573句『3 117 露翠
`
`TIA/EIA働 644
`
`5.1 Generator characteristics
`
`The generator electrical characteristics are specified in accordance with the
`measurements illustrated in figures 4 to 8 and described in 5.1.1 through 5.1.4. The
`generator circuit meeting these requirements results in a balanced source that will
`produce a differential voltage across a test termination load of 100 n in the range of
`250 mV to 450 mV.
`
`The signaling sense of the voltages appearing across the termination resistor is
`defined in figure 3 as follows:
`
`a. The A terminal of the generator shall be negative with respect to the B
`terminal for a binary 1 or OFF state.
`
`b. The A terminal of the generator shall be positive with respect to the B
`terminal for a binary O or ON state.
`
`γhe logic function of the generator and the receiver is beyond the scope of this
`Standard, and therefore is not defined.
`
`OFF
`
`VB
`
`0
`ON
`
`OFF
`
`院二子；訂＝ 100n
`
`9 C
`
`Figure 3 ・Signaling sense
`
`.......... +1.2 V
`typical
`
`+250 to
`+400 mV
`
`ov (Diff.)
`
`-250 to
`・400mV
`
`7
`
`

`

`EIA TIA岬 b匂句 96 盤譲 3234600 057399匂 日53 醸趨
`
`TIA/EIA-644
`
`5.1.1 Test termination measurements {figure 4)
`
`With a test load of two resistors, 49.9 n ±1% each, connected in series between the
`generator output terminals, the steady-state magnitude of the differential output
`voltage (Vt), shall be greater than or equal to 247 mV [99.8 n -1% (2.5 mA}J and less
`than or equal to 454 mV [99.Sn +1% (4.5 mA}]. For the opposite binary state, the
`polarity of Vt shall be reversed (Vt*). The steady-state magnitude of the difference
`between Vt and Vt* shall be 50 mV or less.
`247 mV三 IVt Is 454 mV
`247 mV s I Vt* I s 454 mV
`
`I Vt I -I Vt* I s 50 m V
`
`τhe steady”state magnitude of the generator o仔setvoltage (Vos), measured between
`the center point of the test load and the generator circuit common shall be greater than
`or equal to 1.125 V and less than or equal to 1.375 V for either binary state. The
`steady-state magηitude of the difference of Vos for one binary state and Vos* for the
`opposite binary state shall be 50 mV or less.
`1.125 V s Vos s 1.375 V
`1.125 V s Vos台三 1.375V
`
`I Vos I・ I Vos台 Is50 mV
`
`STEADY STATE
`LOGIC INPUT
`(i OR 0)
`
`B
`
`ぷア思…向rameter
`
`Figure 4・Testtermination measurements
`
`8
`
`

`

`EIA TIA四 644 96 露璽 3234 b口8 05739・95 T9T 臨蜜
`
`TIA/EIA司 644
`
`5.1.2 Short梅 circuit measurements (figures 5, and 6)
`
`With the generator output terminals short-circuited to the generator circuit common, the
`magnitudes of the currents (Isa and lsb) following through each output terminal shall
`not exceed 24.0 mA for either binary st剖e(see figure 5).
`
`I Isa I :s; 24.0 mA
`I lsb I :s; 24.0 mA
`
`STEADY STATE
`LOGIC INPUT
`(1 OR 0)
`
`グ ＝ … Paramet
`
`Figure 5・Short-circuitmeasurements to circuit common
`
`With the generator output terminals short-circuited to each other, the magnitude of the
`current (lsab) following through the output terminals shall not exceed 12.0 mA for
`either binary state (see figure 6).
`
`I lsab i壬 12.0mA
`
`STEADY STATE
`LOGIC INPUT
`(1 OR 0)
`
`A
`
`B
`
`ー グ 吋 …m酷 r
`
`円gure 6 倫 Short-circuit measurements
`
`9
`
`

`

`EIA
`
`TIA圃 b句句
`
`藤喜弓ら
`
`32346日日
`
`日5739司b
`
`弓2b
`
`聾襲
`
`TIA/EIA”644
`
`5.1.3
`
`Output signal waveform
`
`(figure 7)
`
`During transitions of the generator output between alternating binary states (one-zero-
`one働 zero,etc.), the differential voltage measured across the 99.8 n ±1% test load (RL)
`and a maximum lum担edcapacitance test load of 5 pF (CL) connected as shown in
`figure 7, shall be such that the voltage monotonically changes between 0.2 and 0.8 of
`Vss and is less than or equal to 0.3 of the unit interval (at the maximum data signaling
`rate to be employed up to 200 Mbit/s). Above 200 Mbit/s the transition time shall be
`greater than or equal to 260 ps and less than or equal to 1.5 ns. Thereafter, the signal
`voltage shall not vary more than ±20% of the steady-state value (Vring}, until the next
`binary transition occurs. Edge rates less than 260 ps are not recommended to
`minimize adverse effects of switching noise. Vss is defined as the voltage difference
`between the two steady-state values of the generator output (Vss = 21Vtl).
`Measure問entequipment used for compliance testing shall provide a bandwidth of
`1 GHz minimum.
`
`For data signaling ratesぎ200Mbit/s ( tuiミ5ns):
`tr ~ 0.3 tui， 甘 豆 0.3tui
`For data signaling rates 芝200 Mbit/s ( tui三5ns)
`
`and豆655Mbit/s (tuiミ1.526ns):
`260 ps話 tr三 1.5ns,
`A
`
`260 ps豆 tf話 1.5ns
`
`CL
`
`RL
`
`B
`
`0.8Vss ・+・
`
`I Vring
`I ±20% Vss
`.＼.烹 0.8Vss
`
`OV Differential
`
`AL TERNA TING
`LOGICINPUγ
`(1,0, 1,0，…）
`
`一事
`
`il陶
`
`j喝ドー・岬− tui 一目白静i
`
`0.2Vss ・t"' "i＂＂”！？”。ぬ S
`一新 tr持一 →； tf I喝 ー
`
`Figure 7・Outputsignal waveform
`
`10
`
`

`

`EIA TI A田ら匂句 96 盤璽 323460日 日573弓可？ 862
`
`TIA/EIA-644
`
`5.1.4 Dynamic output signal balance {figure 8)
`
`During transitions of the generator output between alternating binary states (one-zero-
`one-zero, etc.), the resulting imbalance of the offset voltage (Vos) measured between
`the matched 49. 9 n土1% test load resistors (RL) to circuit common (C) and with a
`maximum lumped capacitance test load of 5 pF (CL) connected as shown in figure 8,
`should not vary more than 150 mVpp (peak-to・peak). Measurement equipment used
`for compliance testing shall provide a bandwidth of 1 GHz minimum.
`
`A
`C
`
`C
`B
`
`ト＼
`
`AL TERNA TING
`LOGIC INPUT
`(1,0, 1,0, ... )
`
`一一
`
`A
`
`Vss
`
`円 tui !
`
`A-8
`
`OV Differential
`
`GND
`
`Figure 8 ・Dynamicoutput signal balance waveform
`
`11
`
`

`

`E工A TIA国 b44 弓b 露璽 323句b日B 0573998 7T司墜警護
`
`TIA/εIA-644
`
`5.2 Load characteristics
`
`The load is defined as an impedance between A’and B’and is composed of a
`termination impedance and a receiver as shown in figure 2.
`
`The electrical characteristics of a receiver without an internal termination impedance
`are specified in terms of measurements illustrated in figures .9, 12 and 13, and
`d~scribed in 5.2.1 and 5.2.3. Alternatively, the electrical characteristics of a receiver
`with an internal termination impedance is specified in terms of measurements
`illustrated in figures 1 O to 13, and described in 5.2.2 through 5.2.3. A circuit meeting
`these requirements results in a differential receiver having a high input impedance
`(non-terminating receiver), and a small input threshold between ± 100 mV.
`
`γhe media termination is specified in terms of measurements described in 5.2.4 and
`5.2.2 for receivers that integrate the termination impedance.
`
`The total load limit is specified in 5.4.3, and additional guidance is provided in 5.4.1
`and 5.4.2 on multiple receiver operation and failsafe operation respec甘ully.
`
`5.2.1 Receiver input current欄 voltage measurements (figure 9)
`
`With the voltage Via {or Vib) ranging from O V to÷2.4 V while Vib (or Via) is held at
`+1.2 V士50mV, the resultant input cur陪 ntlia (or lib) shall be no greater than 20 μA in
`magnitude. These measurements apply with the receiver's power supply in both
`power-on and power-off conditions.
`
`NOTE 3・Some integrated circuit manufacturers may impose additional
`restrictions that may be required to meet this specification under the power-off
`condition.
`
`I lia i：豆 20μA
`I lib I ~ 20 μA
`
`ぷア＝ Meas
`
`Figure 9 ” Receiver input current-voltage measurements
`
`12
`
`

`

`EIA TIA-b勾匂 9 b 盤醤 323勾b百O []573弓弓弓 b.:Iゐ 麟 翠
`
`TIA/EIA・644
`
`5.2.2 Terminating receiver input current-voltage measurements and
`input impedance measurements (figures 10 and 11)
`
`With the applied voltage (Vin) and forced current (lin) listed in table 1 applied to the
`corresponding inputs, the resultant differential input voltage magnitude (Vid) shall be
`between the values listed in table 1. The test circuit is shown in figure 10 and applies
`only to receivers that provide an internal termination impedance. These
`measurements apply with the receiver's power supply in both power-on and power-off
`conditions.
`
`NOTE 4・Some integrated circuit manufacturers may impose additional
`
`restrictions that may be required to meet this specification under the power”。ff
`225 mV豆 iVid I話 596mV
`
`condition.
`
`Table 1 ・ Receivermput current-voltage measurements
`for terminating receivers
`
`Switch
`Position
`S1 -S2
`
`Applied
`Voltage
`Vin
`(V)
`2.4
`2.4
`2.4
`2.4
`
`Forced
`しoopCurrent
`lin
`(mA}
`・2.5
`・4.5
`” 2.5
`・4.5
`
`Resulting
`Differential
`Resulting
`Input Voltage Input Voltage
`Vr
`Range -Vid
`(V)
`(mV)
`A’− 8’ 2.070 to 2.175 ー＋225to +330
`A’・ 8’
`1.806 to 1.995 十405to +596
`綱 225to刷 330
`B’− A'
`2.070 to 2.175
`B’− A’ 1.806 to 1.995 ・405to・596
`0 .225 to O .330 ・225to欄 330
`A' -B'
`A’輔自’
`0.405 to 0.594 ・405to ・596
`0.225 to 0.330 +225toゃ330
`B＇・ A’
`B' -A’ 0.405 to 0.594 +405 to +596
`NOTE5・Currentinto a terminal is positive, and current out of a terminal is negative.
`
`。 暢 2.5
`。 ・4.5
`。 -2.5
`。 ・4.5
`
`B・
`
`ょア＝同red阿 部 蜘
`
`Figure 10 ・Terminating receiver input current-voltage measurements
`
`13
`
`

`

`EIA
`
`TIA岨 b匂匂
`
`守b 罷璽
`
`3234600
`
`日57勾000
`
`T55
`
`100
`200
`400
`300
`/ I VID I刷。ifferentialInput Voltage -mV
`
`500
`
`600
`
`TIA/ElA幽 644
`
`4.5
`
`4.0
`
`3.5
`
`3.0
`
`2.5
`
`2.0
`0
`
`《E − WCO』