-- ~
`-· ~ . : L•.:11.
`_7CYPRESS
`
`enCoRe USB TM CY7C63722/23
`CY7C63742/43
`PRELIMINARY
`
`CY7C63722/23
`CY7C637 42/43
`enCoReTM USB
`Combination Low-Speed USB & PS/2
`Peripheral Controller
`
`Cypress Semiconductor Corporation
`
`•
`
`3901 North First Street
`
`•
`
`San Jose
`
`• CA 95134
`
`•
`
`408-943-2600
`May 25, 2000
`
`PA_0000786
`
`

`

`enCoReTM USB CY7C63722/23
`~ ~YPRESS~~P ;;;;;;;;RE;;;;;;;;L;;;;;;;;/M;;;;;;;;/;;;;;;;;N ;;;;;;;;~ ;;;;;;;;R ;;;;;;;;Y ~~~~~~C;;;;;;;;Y;;;;;;;;7;;;;;;;;C;;;;;;;;6;;;;;;;;3;;;;;;;;7;;;;;;;;42;;;;;;;;/;;;;;;;;43;;;;;;;;;;
`
`TABLE OF CONTENTS
`1.0 FEATURES ..................................................................................................................................... 5
`2.0 FUNCTIONAL OVERVIEW ............................................................................................................. 6
`2.1 enCoRe USB - The New USB Standard ....................................................................................... 6
`3.0 LOGIC BLOCK DIAGRAM ............................................................................................................. 7
`4.0 PIN CONFIGURATIONS ................................................................................................................. 7
`5.0 PIN ASSIGNMENTS ....................................................................................................................... 7
`6.0 PROGRAMMING MODEL ............................................................................................................... 8
`6.1 Program Counter (PC) ................................................................................................................... 8
`6.2 8-bit Accumulator (A) .................................................................................................................... 8
`6.3 8-bit Index Register (X) .................................................................................................................. 8
`6.4 8-bit Program Stack Pointer (PSP) ............................................................................................... 8
`6.5 8-bit Data Stack Pointer (DSP) ...................................................................................................... 8
`6.6 Address Modes .............................................................................................................................. 9
`6.6.1 Data ........................................................................................................................................................ 9
`6.6.2 Direct ..................................................................................................................................................... 9
`6.6.3 Indexed .................................................................................................................................................. 9
`7.0 INSTRUCTION SET SUMMARY ................................................................................................... 10
`8.0 MEMORY ORGANIZATION .......................................................................................................... 11
`8.1 Program Memory Organization .................................................................................................. 11
`8.2 Data Memory Organization ......................................................................................................... 12
`8.3 1/0 Register Summary ................................................................................................................. 13
`9.0 CLOCKING .................................................................................................................................... 14
`9.1 Internal / External Oscillator Operation ..................................................................................... 15
`9.2 External Oscillator ....................................................................................................................... 15
`10.0 RESET ......................................................................................................................................... 15
`10.1 Low Voltage Reset (LVR) .......................................................................................................... 16
`10.2 Brown Out Reset (BOR) ............................................................................................................ 16
`10.3 Watch Dog Reset (WDR) ........................................................................................................... 16
`11.0 SUSPEND MODE ........................................................................................................................ 16
`11.1 Clocking Mode on Wake-up from Suspend ............................................................................. 17
`11.2 Wake-up Timer ........................................................................................................................... 17
`12.0 GENERAL PURPOSE 1/0 PORTS ............................................................................................. 18
`12.1 Auxiliary Input Port .................................................................................................................... 20
`13.0 USB SERIAL INTERFACE ENGINE (SIE) ................................................................................. 20
`13.1 USB Enumeration ...................................................................................................................... 21
`13.2 USB Port Status and Control .................................................................................................... 21
`14.0 USB DEVICE ............................................................................................................................... 22
`14.1 USB Address Register .............................................................................................................. 22
`14.2 USB Control Endpoint ............................................................................................................... 22
`14.3 USB Non-Control Endpoints (2) ............................................................................................... 23
`14.4 USB Endpoint Counter Registers ............................................................................................ 23
`15.0 USB REGULATOR OUTPUT ...................................................................................................... 24
`
`2
`
`PA_0000787
`
`

`

`enCoReTM USB CY7C63722/23
`~ ~YPRESS~~P ;;;;;;;;RE;;;;;;;;L;;;;;;;;/M;;;;;;;;/;;;;;;;;N ;;;;;;;;~ ;;;;;;;;R ;;;;;;;;Y ~~~~~~C;;;;;;;;Y;;;;;;;;7;;;;;;;;C;;;;;;;;6;;;;;;;;3;;;;;;;;7;;;;;;;;42;;;;;;;;/;;;;;;;;43;;;;;;;;;;
`
`TABLE OF CONTENTS (continued)
`16.0 PS/2 OPERATION ....................................................................................................................... 24
`17.0 SERIAL PERIPHERAL INTERFACE (SPI) ................................................................................. 25
`17 .1 Operation as an SPI Master ...................................................................................................... 26
`17.2 Master SCK Selection ................................................................................................................ 26
`17 .3 Operation as an SPI Slave ........................................................................................................ 27
`17.4 SPI Status and Control .............................................................................................................. 27
`17.5 SPI Interrupt ............................................................................................................................... 28
`17.6 SPI modes for GPIO pins .......................................................................................................... 28
`18.0 12-BIT FREE-RUNNING TIMER ................................................................................................. 29
`19.0 TIMER CAPTURE REGISTERS ................................................................................................. 30
`20.0 PROCESSOR STATUS AND CONTROL REGISTER ............................................................... 32
`21.0 INTERRUPTS .............................................................................................................................. 33
`21.1 Interrupt Vectors ........................................................................................................................ 34
`21.2 Interrupt Latency ....................................................................................................................... 35
`21.3 Interrupt Sources ....................................................................................................................... 35
`21.3.1 USB Bus Reset or PS/2 Activity ...................................................................................................... 35
`21.3.2 Free Running Timer Interrupts ........................................................................................................ 35
`21.3.3 USB Endpoint Interrupts .................................................................................................................. 35
`21.3.4 SPI Interrupt ...................................................................................................................................... 35
`21.3.5 Capture Timer Interrupts ................................................................................................................. 35
`21.3.6 GPIO Interrupt ................................................................................................................................... 35
`21.3. 7 Wake-up lnterru pt ............................................................................................................................. 37
`22.0 USB MODE TABLES .................................................................................................................. 37
`23.0 ABSOLUTE MAXIMUM RATINGS ............................................................................................. 40
`24.0 DC CHARACTERISTICS ............................................................................................................ 41
`25.0 SWITCHING CHARACTERISTICS ............................................................................................. 42
`26.0 ORDERING INFORMATION ....................................................................................................... 47
`27.0 PACKAGE DIAGRAMS .............................................................................................................. 47
`
`LIST OF FIGURES
`Figure 8-1. Program Memory Space with Interrupt Vector Table .................................................. 11
`Figure 9-1. Clock Oscillator On-chip Circuit ................................................................................... 14
`Figure 9-2. Clock Configuration Register (Address OxF8) ............................................................. 14
`Figure 10-1. Watch Dog Reset (WDR) .............................................................................................. 16
`Figure 12-1. Block Diagram of GPIO Port (one pin shown) ........................................................... 18
`Figure 12-2. Port O Data (Address OxOO) .......................................................................................... 19
`Figure 12-3. Port 1 Data (Address Ox01) .......................................................................................... 19
`Figure 12-4. GPIO Port O ModeO Register (Address OxOA) ............................................................ 19
`Figure 12-5. GPIO Port O Mode1 Register (Address OxOB) ............................................................ 20
`Figure 12-6. GPIO Port 1 ModeO Register (Address OxOC) ............................................................ 20
`Figure 12-7. GPIO Port 1 Mode1 Register (Address OxOD) ............................................................ 20
`Figure 12-8. Port 2 Data Register (Address Ox02) .......................................................................... 20
`Figure 13-1. USB Status and Control Register (Address Ox1 F) .................................................... 21
`Figure 14-1. USB Device Address Register (Address Ox10) .......................................................... 22
`Figure 14-2. USB EPO Mode Register (Address Ox12) .................................................................... 22
`
`3
`
`PA_0000788
`
`

`

`enCoReTM USB CY7C63722/23
`~ ~YPRESS~~P ;;;;;;;;RE;;;;;;;;L;;;;;;;;/M;;;;;;;;/;;;;;;;;N ;;;;;;;;~ ;;;;;;;;R ;;;;;;;;Y ~~~~~~C;;;;;;;;Y;;;;;;;;7;;;;;;;;C;;;;;;;;6;;;;;;;;3;;;;;;;;7;;;;;;;;42;;;;;;;;/;;;;;;;;43;;;;;;;;;;
`
`LIST OF FIGURES (continued)
`Figure 14-3. USB Endpoint EP1, EP2 Mode Registers (Addresses Ox14, Ox16) .......................... 23
`Figure 14-4. USB Device Counter Registers (Addresses Ox11 h, Ox13h, Ox15) ............................ 23
`Figure 16-1. Diagram of USB - PS/2 System Connections ............................................................. 25
`Figure 17-1. SPI Block Diagram ........................................................................................................ 26
`Figure 17-2. SPI Data Register (Address Ox60) ............................................................................... 26
`Figure 17-3. SPI Control Register (Address Ox61) .......................................................................... 27
`Figure 17-4. SPI Data Timing ............................................................................................................ 28
`Figure 18-1. Timer LSB Register (Address Ox24) ........................................................................... 29
`Figure 18-2. Timer MSB Register (Address Ox25) ........................................................................... 29
`Figure 18-3. Timer Block Diagram .................................................................................................... 29
`Figure 19-1. Capture Timers Block Diagram ................................................................................... 30
`Figure 19-2. Capture Timer A-Rising, Data Register (Address Ox40) ........................................... 31
`Figure 19-3. Capture Timer A-Falling, Data Register (Address Ox41) ........................................... 31
`Figure 19-4. Capture Timer B-Rising, Data Register (Address Ox42) ........................................... 31
`Figure 19-5. Capture Timer B-Falling, Data Register (Address Ox43) ........................................... 31
`Figure 19-6. Capture Timers Configuration Register (Address Ox44) .......................................... 31
`Figure 19-7. Capture Timers Status Register (Address Ox45) ....................................................... 31
`Figure 20-1. Processor Status and Control Register (Address OxFF) .......................................... 32
`Figure 21-1. Global Interrupt Enable Register Ox20h (read/write) ................................................. 33
`Figure 21-2. USB End Point Interrupt Enable Register (Address Ox21) ....................................... 33
`Figure 21-3. Interrupt Controller Logic Block Diagram .................................................................. 34
`Figure 21-4. Port O Interrupt Enable Register (Address Ox04) ....................................................... 36
`Figure 21-5. Port 1 Interrupt Enable Register (Address Ox05) ....................................................... 36
`Figure 21-6. Port O Interrupt Polarity Register (Address Ox06) ..................................................... 36
`Figure 21-7. Port 1 Interrupt Polarity Register (Address Ox07) ..................................................... 36
`Figure 21-8. GPIO Interrupt Diagram ............................................................................................... 36
`Figure 25-1. Clock Timing ................................................................................................................. 43
`Figure 25-2. USB Data Signal Timing ............................................................................................... 43
`Figure 25-3. Receiver Jitter Tolerance ............................................................................................. 44
`Figure 25-4. Differential to EOP Transition Skew and EOP Width ................................................ 44
`Figure 25-5. Differential Data Jitter .................................................................................................. 44
`Figure 25-7. SPI Slave Timing, CPHA=O .......................................................................................... 45
`Figure 25-6. SPI Master Timing, CPHA=O ........................................................................................ 45
`Figure 25-8. SPI Master Timing, CPHA=1 ........................................................................................ 46
`Figure 25-9. SPI Slave Timing, CPHA=1 .......................................................................................... 46
`
`LIST OF TABLES
`Table 8-1. 1/0 Register Summary ...................................................................................................... 13
`Table 11-1. Wake-up Timer Adjust Settings .................................................................................... 18
`Table 12-1. Ports O and 1 Output Control Truth Table ................................................................... 19
`Table 13-1. Control Modes to Force D+/D- Outputs ....................................................................... 22
`Table 17-1. SPI Control Register Definitions ................................................................................... 27
`Table 17-2. SPI Pin Assignments ..................................................................................................... 28
`Table 19-1. Capture Timer Prescalar Settings (Step size and range for FCLK = 6 MHz) ............ 32
`Table 21-1. Interrupt Vector Assignments ....................................................................................... 34
`Table 22-1. USB Register Mode Encoding ...................................................................................... 37
`Table 22-2. Decode table for Table 22-3: "Details of Modes for Differing Traffic Conditions" ... 38
`Table 22-3. Details of Modes for Differing Traffic Conditions ....................................................... 39
`
`4
`
`PA_0000789
`
`

`

`~ -.,~
`-;CYPRESS
`1.0
`Features
`
`PRELIMINARY
`
`enCoReTM USB CY7C63722/23
`CY7C637 42/43
`
`• enCoRe™ USB - enhanced Component Reduction
`-
`Internal oscillator eliminates the need for an external crystal or resonator
`-
`Interface can auto-configure to operate as PS/2 or USB without the need for external components to switch between
`modes (no GPIO pins needed to manage dual mode capability)
`Internal 3.3V regulator for USB pull-up resistor
`-
`-Configurable GPIO for real-world interface without external components
`• Flexible, cost-effective solution for applications that combine PS/2 and low-speed USB, such as mice, gamepads,
`joysticks, and many others.
`• USB Specification Compliance
`- Conforms to USB Specification, Version 1.1
`-Conforms to USB HID Specification, Version 1.1
`-Supports 1 Low-Speed USB device address and 3 data endpoints
`-
`Integrated USB transceiver
`-3.3V regulated output for USB pull-up resistor
`• 8-bit RISC microcontroller
`- Harvard architecture
`-6-MHz external ceramic resonator or internal clock mode
`-12-MHz internal CPU clock
`-
`Internal memory
`- 256 bytes of RAM
`-6 Kbytes of EPROM (CY7C63722, CY7C63742)
`-8 Kbytes of EPROM (CY7C63723, CY7C63743)
`Interface can auto-configure to operate as PS/2 or USB
`-
`-No external components for switching between PS/2 and USB modes
`- No GPIO pins needed to manage dual mode capability
`• 1/0 ports
`- Up to 16 versatile General Purpose 1/0 (GPIO) pins, individually configurable
`-High current drive on any GPIO pin: 50 mA/pin current sink
`- Each GPIO pin supports high-impedance inputs, internal pull-ups, open drain outputs or traditional CMOS outputs
`- Maskable interrupts on all 1/0 pins
`• SPI serial communication block
`- Master or slave operation
`-2 Mbit/s transfers
`• Four 8-bit Input Capture registers
`-Two registers each for two input pins
`-Capture timer setting with 5 pre-scaler settings
`-Separate registers for rising and falling edge capture
`-Simplifies interface to RF inputs for wireless applications
`• Internal low-power wake-up timer during suspend mode
`- Periodic wake-up with no external components
`• Optional 6-MHz internal oscillator mode
`-Allows fast start-up from suspend mode
`• Watch dog timer (WDT)
`• Low Voltage Reset at 3.75V
`• Internal brown-out reset for suspend mode
`• Improved output drivers to reduce EMI
`• Operating voltage from 4.0V to 5.5VDC
`
`5
`
`PA_0000790
`
`

`

`enCoReTM USB CY7C63722/23
`CY7C637 42/43
`
`PRELIMINARY
`
`~ -.,~
`-;CYPRESS
`• Operating temperature from Oto 70 degrees Celsius
`• CY7C63722/23 available in 18-pin PDIP
`• CY7C63742/43 available in 24-pin SOIC, 24-pin PDIP
`• Industry standard programmer support
`
`2.0
`
`Functional Overview
`
`enCoRe USB - The New USB Standard
`2.1
`Cypress has re-invented its leadership position in the low-speed USB market with a new family of innovative microcontrollers.
`lntroducing ... enCoRe USB-"enhanced Component Reduction." Cypress has leveraged its design expertise in USB solutions to
`create a new family of low-speed USB microcontrollers that will enable peripheral developers to design new products with a
`minimum number of components. At the heart of our enCoRe TM USB technology is the breakthrough design of a crystal-less
`oscillator. By integrating the oscillator into our chip, an external crystal or resonator is no longer needed. We have also integrated
`other external components commonly found in low-speed USB applications such as pull-up resistors, wake-up circuitry, and a
`3.3V regulator. All of this adds up to a lower system cost.
`
`The CY7C63722/23 and CY7C63742/43 are 8-bit RISC One Time Programmable (OTP) microcontrollers. The instruction set has
`been optimized specifically for USB and PS/2 operations, although the microcontrollers can be used for a variety of other embed(cid:173)
`ded applications.
`The CY7C637xx features up to 16 general purpose 1/0 (GPIO) pins to support USB, PS/2 and other applications. The 1/0 pins
`are grouped into two ports (Port O to 1) where each pin can be individually configured as inputs with internal pull-ups, open drain
`outputs, or traditional CMOS outputs with programmable drive strength of up to 50 mA output drive. Additionally, each 1/0 pin can
`be used to generate a GPIO interrupt to the microcontroller. Note the GPIO interrupts all share the same "GPIO" interrupt vector.
`
`The CY7C637xx microcontrollers feature an internal 5% accurate 6-MHz clock source. Optionally, an external 6-MHz ceramic
`resonator can be used to provide a higher precision reference for USB operation. This clock generator reduces the clock-related
`noise emissions (EMI). The clock generator provides the 6- and 12-MHz clocks that remain internal to the microcontroller.
`The CY7C637xx is offered with two EPROM options to maximize flexibility and minimize cost. The CY7C637x2 has 6 Kbytes of
`EPROM. The CY7C637x3 has 8 Kbytes of EPROM. All versions have 256 bytes of data RAM for stack space, user variables, and
`USB FIFOs.
`These parts include low-voltage reset logic, a watch dog timer, a vectored interrupt controller, a 12-bit free-running timer, and
`capture timers. The low-voltage reset (LVR) logic detects when power is applied to the device, resets the logic to a known state,
`and begins executing instructions at EPROM address OxOOOO. LVR will also reset the part when Vee drops below the operating
`voltage range. The watch dog timer can be used to ensure the firmware never gets stalled for more than approximately 8 ms.
`The microcontroller supports 10 maskable interrupts in the vectored interrupt controller. Interrupt sources include the USB
`Bus-Reset, the 128-µs and 1.024-ms outputs from the free-running timer, three USB endpoints, two capture timers, an internal
`wake-up timer and the GPIO ports. The timers bits cause periodic interrupts when enabled. The USB endpoints interrupt after
`USB transactions complete on the bus. The capture timers interrupt whenever a new timer value is saved due to a selected GPIO
`edge event. The GPIO ports have a level of masking to select which GPIO inputs can cause a GPIO interrupt. For additional
`flexibility, the input transition polarity that causes an interrupt is programmable for each GPIO pin. The interrupt polarity can be
`either rising or falling edge.
`The free-running 12-bit timer clocked at 1 MHz provides two interrupt sources as noted above (128 µsand 1.024 ms). The timer
`can be used to measure the duration of an event under firmware control by reading the timer at the start and end of an event,
`and subtracting the two values. The four capture timers save a programmable 8 bit range of the free-running timer when a GPIO
`edge occurs on the two capture pins (PO.O, P0.1 ).
`The CY7C637xx includes an integrated USB serial interface engine {SIE) that supports the integrated peripherals. The hardware
`supports one USB device address with three endpoints. The SIE allows the USB host to communicate with the function integrated
`into the microcontroller. A 3.3V regulated output pin provides a pull-up source for the external USB resistor on the D- pin.
`
`The USB D+ and D- USB pins can alternately be used as PS/2 SCLK and SDATA signals, so that products can be designed to
`respond to either USB or PS/2 modes of operation. PS/2 operation is supported with internal pull-up resistors on SCLK and
`SDATA, the ability to disable the regulator output pin, and an interrupt to signal the start of PS/2 activity. No external components
`are necessary for dual USB and PS/2 systems, and no GPIO pins need to be dedicated to switching between modes. Slow edge
`rates operate in both modes to reduce EMI.
`
`6
`
`PA_0000791
`
`

`

`~ - . ,~
`-;CYPRESS
`3.0
`Logic Block Diagram
`
`PRELIMINARY
`
`enCoReTM USB CY7C63722/23
`CY7C637 42/43
`
`Internal
`Oscillator
`
`Xtal
`Oscillator
`
`EPROM
`6K/8K Byte
`
`8-bit
`RISC
`core
`
`Brown-out
`Reset
`
`1 - - - - - - - - -1
`
`Watch
`Dog
`Timer
`
`Low
`Voltage
`Reset
`
`Interrupt
`Controller
`
`USB
`Engine
`
`Port 1
`GPIO
`
`Port 0
`GPIO
`
`3.3V
`Regulator
`
`USB &
`PS/2
`Xcvr
`
`VREG
`
`D+,D-
`
`P1 .O-P1 .7 P0.0-P0.7
`
`4.0
`
`Pin Configurations
`
`CY7C63722/23
`18-pin PDIP
`
`PO.O
`P0.1
`P0.2
`P0.3
`P1.0
`
`VPP
`VREG
`XTALIN/P2.1
`
`1
`2
`3
`4
`5
`
`7
`8
`9
`
`P0.4
`18
`17 P0.5
`P0.6
`16
`P0.7
`15
`P1.1
`14
`13 D+/SCLK
`12 D-/SDATA
`vcc
`11
`10
`XTALOUT
`
`Top View
`
`CY7C63742/43
`24-pin SOIC/PDIP
`
`P1.2
`P1 .4
`P1.6
`vss
`VPP
`VREG
`XTALIN/P2.1
`
`6
`7
`8
`9
`10
`11
`12
`
`P0.7
`P1.1
`P1.3
`P1.5
`P1.7
`D+/SCLK
`D-/SDATA
`vcc
`XTALOUT
`
`18
`17
`16
`15
`14
`13
`
`5.0
`
`Name
`
`Pin Assignments
`CY7C63722/23 CY7C63742/43
`18-Pin
`24-Pin
`
`1/0
`
`Description
`
`12
`13
`
`15
`16
`
`USB differential data lines (D- and D+), or PS/2 clock and data sig-
`nals (SDATA and SCLK)
`
`GPIO Port O capable of sinking up to 50 mA/pin, or sinking controlled
`low or high programmable current. Can also source 2 mA current,
`provide a resistive pull-up, or serve as a high impedance input. PO.O
`and P0.1 provide inputs to Capture Timers A and B, respectively.
`10 Port O capable of sinking up to 50 mA/pin, or sinking controlled
`low or high programmable current. Can also source 2 mA current,
`provide a resistive pull-up, or serve as a high impedance input.
`6-MHz ceramic resonator or external clock input, or P2.1 input
`6-MHz ceramic resonator return pin or internal oscillator output
`Programming voltage supply, ground for normal operation
`
`Voltage supply
`Voltage supply for 1.5-kQ USB pull-up resistor (3.3V nominal). Also
`serves as P2.0 input.
`Ground
`
`7
`
`PA_0000792
`
`D-/SDATA,
`D+/SCLK
`
`P0[7:0]
`
`1/0
`
`1/0
`
`1, 2, 3, 4,
`15, 16, 17, 18
`
`1, 2, 3, 4,
`21,22,23,24
`
`P1[7:0]
`
`1/0
`
`5, 14
`
`5, 6, 7, 8,
`17, 18, 19, 20
`
`IN
`OUT
`
`XTALIN/P2.1
`XTALOUT
`Vpp
`
`Vee
`VREG/P2.0
`
`Vss
`
`9
`10
`7
`11
`8
`
`6
`
`12
`13
`10
`14
`11
`
`9
`
`

`

`~ -.,~
`-;CYPRESS
`6.0
`Programming Model
`
`PRELIMINARY
`
`enCoReTM USB CY7C63722/23
`CY7C637 42/43
`
`Refer to the CYASM Assembler User's Guide for more details on firmware operation with the CY7C637xx microcontrollers.
`
`Program Counter (PC)
`6.1
`The 13-bit program counter (PC) allows access for up to 8 Kbytes of EPROM using the CY7C637xx architecture. The program
`counter is cleared during reset, such that the first instruction executed after a reset is at address OxOOOO. This is typically a jump
`instruction to a reset handler that initializes the application.
`The lower 8 bits of the program counter are incremented as instructions are loaded and executed. The upper 5 bits of the program
`counter are incremented by executing an XPAGE instruction. As a result, the last instruction executed within a 256-byte "page"
`of sequential code should be an XPAGE instruction. The assembler directive "XPAGEON" will cause the assembler to insert
`XPAGE instructions automatically. As instructions can be either one or two bytes long, the assembler may occasionally need to
`insert a NOP followed by an XPAGE for correct execution.
`The program counter of the next instruction to be executed, carry flag, and zero flag are saved as two bytes on the program stack
`during an interrupt acknowledge or a CALL instruction. The program counter, carry flag, and zero flag are restored from the
`program stack only during a RETI instruction.
`Please note the program counter cannot be accessed directly by the firmware. The program stack can be examined by reading
`SRAM from location OxOO and up.
`
`8-bit Accumulator (A)
`6.2
`The accumulator is the general purpose, do everything register in the architecture where results are usually calculated.
`
`8-bit Index Register (X)
`6.3
`The index register "X" is available to the firmware as an auxiliary accumulator. The X register also allows the processor to perform
`indexed operations by loading an index value into X.
`
`8-bit Program Stack Pointer (PSP)
`6.4
`During a reset, the program stack pointer (PSP) is set to zero. This means the program "stack" starts at RAM address OxOO and
`"grows" upward from there. Note the program stack pointer is directly addressable under firmware control, using the MOV PSP,A
`instruction. The PSP supports interrupt service under hardware control and CALL, RET, and RETI instructions under firmware
`control.
`During an interrupt acknowledge, interrupts are disabled and the program counter, carry flag, and zero flag are written as two
`bytes of data memory. The first byte is stored in the memory addressed by the program stack pointer, then the PSP is incremented.
`The second byte is stored in memory addressed by the program stack pointer and the PSP is incremented again. The net effect
`is to store the program counter and flags on the program "stack" and increment the program stack pointer by two.
`The return from interrupt (RETI) instruction decrements the program stack pointer, then restores the second byte from memory
`addressed by the PSP. The program stack pointer is decremented again and the first byte is restored from memory addressed
`by the PSP. After the program counter and flags have been restored from stack, the interrupts are enabled. The effect is to restore
`the program counter and flags from the program stack, decrement the program stack pointer by two, and re-enable interrupts.
`The call subroutine (CALL) instruction stores the program counter and flags on the program stack and increments the PSP by two.
`The return from subroutine (RET) instruction restores the program counter, but not the flags, from program stack and decrements
`the PSP by two.
`Note that there are restrictions in using some jump, call, and index instructions across the 4KB boundary of the program memory.
`Refer to the CYASM Assembler User's Guide for a detailed description.
`
`8-bit Data Stack Pointer (DSP)
`6.5
`The data stack pointer (DSP) supports PUSH and POP instructions that use the data stack for temporary storage. A PUSH
`instruction will pre-decrement the DSP, then write data to the memory location addressed by the DSP. A POP instruction will read
`data from the memory location addressed by the DSP, then post-increment the DSP.
`During a reset, the Dat