Universal Serial Bus Specification Revision 2.0
`
`11.20.2 Interrupt Split Transaction State Machines
`
`~s.11.
`···-- .... -·-·-············ -·-····.
`! lssue_packet(HSD1 ' SSPLIT);
`! ....... ·----·········· ··········-··-······-····--.. -··-··---···- - .............. ___ .... ;
`
`. 1
`
`sd1
`......
`· ~~~~~~~~~~- i
`
`. ..... -............. .
`1_1~_5..~.=~-~-~~=~~~-~~.:.'. ... ~~~~>.; ...... J
`
`sh1
`
`RespondHC(Do_complete);
`~
`
`HC_Do_lntOSS
`
`Figure 11-72. Interrupt OUT Start-split Transaction Host State Machine
`
`386
`
`ZTE/SAMSUNG 1008-0414
`IPR2018-00111
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`Jct1
`
`.. ···-·······-·· ··~····---· ·· ·--···· ···--· ····-·· ···
`-·····-·-·-·
`lssue_packet(HSD1, CSPLIT);
`
`1 ct2
`!" .............................................. ........................... -............. -............ ..
`l issue_packet(HSD1 , tokenOUT);
`
`! .......... ,,_,, ............................................................ - ........................... .
`
`Packet_ ready(HSU2)
`
`"-··-Hs~2:;;·jr;·~-·~·;i< ........ l
`
`RespondHC(Do_start);
`
`i HSU2.PID =STALL
`~------: ! RespondHC(Do_halt);
`
`Respond HC(Do _next_ cmd);
`
`HSU2.PID = NYET .. !
`'-·---·--·- __;
`ce2 ~:--~Hc=-c~s;- -
`~ RespondHC(Do_next_complete);
`~.:·.:.--······----···········-·-···-.. ··-··-······---········· ····--·····- ..
`.
`' HC_cmd.last
`
`·············-····-······-··----.................... .
`HSU2.PID = ERR
`
`- i
`
`! (HSU2.PID /=STALL and
`! HSU2.PID I= NAK and
`i HSU2.PID I= ACK and
`i HSU2.PID /= ERR and
`J HSU2.PID /= NYET) or
`. . , L~~.~3._~t!.~-~~~~-.. -... y ............... : .. .
`
`.................... ..
`
`RespondHC(Do_halt);
`~.-y/
`
`i-•+>••·····--···· .. ·······-··-··-······ ...... .....
`! ErrorCount >= 3
`i
`L .......................... - .................... 1 & ..
`[~~~~c~~-~~ .. ~=-·~: .. :]
`
`ErrorCount < 3
`RespondHC(Do _comp _immed _now);
`
`HC_Do_JntOCS
`
`Figure 11-73. Interrupt OUT Complete-split Transaction Host State Machine
`
`387
`
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`IPR2018-00111
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`HSD2.PID /= DATAx or
`HSD2.timeout
`
`se1
`
`.... - .... --------------------·· ··--····
`' Packet_ready(HSD2)
`
`. HSD2. Pl D = DAT Ax
`
`............................................. "'"""""_ - :
`HSD2.CRC16 = ok
`Data_into_ ss _pipe;
`
`TT_lntOSS_wait
`Wait_for_packet(
`HS02, ITG);
`
`I HSD2.CRC16 = b~d -,
`
`•
`
`,!
`
`I TT_Do_lntOSS
`Figure 11-74. Interrupt OUT Start-split Transaction TT State Machine
`
`388
`
`ZTE/SAMSUNG 1008-0416
`IPR2018-00111
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`CS_Buff.match.down_result = r_trans_err
`lssue_packet(HSU1 , ERR);
`
`ch1
`
`CS_Buff.match.down_result = r_ack
`lssue_packet(HSU1, ACK);
`
`. CS_Buff.match.down_result = r_stall
`lssue_packet(HSU1, STALL);
`
`~ -
`
`-4-••-
`
`· .. ~~~;~~;;~~;~;,~~;:~~2.'..~;~~i.~~·~··········j
`i?..~::~.~.~~~:~.~-~.:~.~~!: .. ~ .. r.12~~~-~=~·~·=~--··...f
`
`f''""·--···············--·· ····················--············-····-·· .. ······---········-.. ··-·············-.
`
`TT _Do_lntOCS
`
`Figure 11-75. Interrupt OUT Complete-split Transaction TT State Machine
`
`lssue_packet(HSD1, SSPLIT);
`
`···-·······-······------··--····--- .... _ ........................................................ ,
`~~~~~~~~~~~ !
`lssue_packet(HSD1, tokenlN);
`
`RespondHC(Do_complete);
`
`HC_Do_lntlSS ... .. I . . .. ··\:~
`
`Figure 11-76. Interrupt IN Start-split Transaction Host State Machine
`
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`
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`

`Universal Serial Bus Specification Revision 2.0
`
`ce2
`
`HSU2.PID = ERR
`
`ce9
`
`1
`
`ErrorCount < 3
`i RespondHC(Do_start);
`<... ............................................................................ J
`.... . )
`
`]
`l
`
`l
`
`ErrorCount >= 3
`! RespondHC(Do_halt);
`
`,
`!. .••• ,_ ............................ - .................. - ........ ,_., .. J
`
`..... ,,,_ . ···········-···· ···-··---· .............. •<>••·-·· ········- ·· .......
`.
`not HC cmd.last
`J RespondHC(Do~next_complete);
`
`.... -·· ···1
`
`._ .......... ~.~~-····--··············-·-:
`
`lssue_packet(HSD1 , CSPLIT);
`
`i
`
`lssue_packet(HSD1 , tokenlN);
`
`HSU2.PID =STALL
`. RespondHC(Do_halt);
`
`(HSU2.PID /= NAK and
`HSU2.PID /=STALL and
`HSU2.PID /= NYET and
`HSU2.PID /= ERR) or
`HSU2.timeout
`
`HC_Do_lntlCS
`
`Figure 11-77. Interrupt fN Complete-split Transaction Host State Machine
`
`390
`
`ZTE/SAMSUNG 1008-0418
`IPR2018-00111
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`:' ·- ....... ...
`·•· .......... . ·····- . ..... ···---······ ····-········.
`HSU2.x = HC_cmd.toggle
`' RespondHC(Do_next_ cmd);
`
`HC_Reject_data;
`
`RespondHC(Do_next_complete);
`
`ErrorCount >= 3
`! RespondHC(Do_halt);
`............................. _., ........... ·······-·j
`
`HSU2.PID = DATAx and
`HSU2.CRC16 = ok
`HC_Accept_ data;
`
`ErrorCount < 3
`RespondHC(Do_comp_immed_now);
`
`: HSU2.PID = MDATA and
`i HSU2.CRC16 = ok
`HC_Accept_data;
`
`...
`
`ch5
`
`(HSU2.PID = MDATA or
`HSU2.PID = DATAx) and
`HSU2.CRC16 = bad
`
`(HSU2.PID /= MDATA and
`cei
`HSU2.PID /= DATAx) or
`Fili••f>-.L<::------=c:..c....-- - -- - - - HSU2.timeout
`
`HC_Data_or_error
`
`Figure 11-78. HC_Data_or_Er ror State Machine
`
`~ Data_into_SS_pipe; _._CB>
`
`TT_Do_lntlSS
`
`Figure 11-79. Interr upt IN Start-split T ransaction TT State Machine
`
`391
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`IPR2018-00111
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`. CS_Buff.match.down_result = r_moredata
`lssue_packet(HSU1 , MDATA);
`
`I CS Buff.match.down result= r lastdata
`!
`- lssue_packet(HsU1 , DATAx);
`
`ch3
`
`! CS. Buff.match.down result= r trans err
`! - lssue_packet{Hsu1 ,ERR);
`
`.
`t ............................. ..., .. ,_ •.. ,_ .•.•. _ .. , •. ..,. .•. ...,..._,, ____ ,.. ..................... .,,._ •••• ...._. ... ..,.,, •.•...• _,,,..,.,..., .. ___ ,..!
`
`CS_Buff.match.down_result = r_nak
`lssue_packet(HSU1, NAK);
`
`i CS_Buff.match.state =old
`
`ch2
`
`CS_Buff.match.down_result = r_stall
`lssue_packet(HSU1 , STALL);
`
`!'"' ............................................. ................................... .............. ......................... ,
`
`ch4
`
`I CS_Buff.match.state = no_match
`i
`·
`lssue_packet(HSU1, NYET);
`; ........................................................................................ ,,.,_ ... ,, ..................... J
`ce1
`;/._ ________ _J CS_Buff.match.state = match_busy
`
`.-·· ···· ·· ······ · ·--· ·-· ·······-···· -· ·· ·· ·····---··· ·····-···· ··-· ·····--· -~··· ·---··-·-·· ·········-···· ···· ·
`
`IT_Do_lntlCS
`
`Figure 11-80. Interrupt IN Complete-split Transaction TT State Machine
`
`11.20.3 Interrupt OUT Sequencing
`Interrupt OUT split transactions are scheduled by the host controller as nonnal high-speed transactions with
`the start- and complete-splits scheduled as described previously.
`
`When there are several full-flow-speed transactions allocated for a given microframe, they are saved by the
`high-speed handler in the TI in the start-split pipeline stage. The start-splits are saved in the order they are
`received until the end of the microframe. At the end of the microframe, these transactions are available to
`be issued by the full-flow-speed handler on the full-flow-speed bus in the order they were received.
`
`Jn a following microframe (as described previously), the full-flow-speed handler issues the transactions that
`had been saved in the start-split pipeline stage on the downstream facing full-flow-speed bus. Some
`transactions could be leftover from a previous microframe since the high-speed schedule was built assuming
`best case bit stuffing and the full-flow-speed transactions could be taking longer on the full-/low-speed bus.
`As the full-flow-speed handler issues transactions on the downstream facing full-flow-speed bus, it saves the
`results in the periodic complete-split pipeline stage and then advances to the next transaction in the start(cid:173)
`split pipeline.
`
`In a following microframe (as described previously), the host controller issues a high-speed complete-split
`transaction and the TI responds appropriately.
`
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`
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`IPR2018-00111
`
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`

`Universal Serial Bus Specification Revision 2.0
`
`High
`Speed
`Bus
`:
`j 64 bytes w/
`! HS CRCI6
`:
`il25us microframe ~
`
`Full/Low(cid:173)
`Speed
`Bus
`
`64 bytes
`Figure 11-81. Example ofCRC16 Handling for Jnterrupt OUT
`
`The start-split transaction for an interrupt OUT transaction includes a normal CRCI6 field for the high(cid:173)
`speed data packet of the data phase of the start-split transaction. However, the data payload of the data
`packet contains only the data payload of the corresponding full-/low-speed data packet; i.e., there is only a
`single CRCI6 in the data packet of the start-split transaction. The TT high-speed handler must check the
`CRC on the start-split and ignore the start-split if there is a failure in the CRC check of the data packet. If
`the start-split has a CRC check failure, the full-speed transaction must not be started on the downstream bus.
`Figure I 1-81 shows an example of the CRC I 6 handling for an interrupt OUT transaction and its start-split.
`
`11.20.4 Interrupt IN Sequencing
`When the high-speed handler receives an interrupt start-split transaction, it saves the packet in the start-split
`pipeline stage. In this fashion, it accumulates some number of start-split transactions for a following
`microframe.
`
`At the beginning of the next microframe (as described previously), these transactions are available to be
`issued by the full-flow-speed handler on the downstream full-/low-speed bus in the order they were saved in
`the start-split pipeline stage. The full-/low-speed handler issues each transaction on the downstream facing
`bus. The full-/low-speed handler responds to the full-/low-speed transaction with an appropriate handshake
`as described in Chapter 8. The full-/low-speed handler saves the results of the transaction (data, NAK,
`STALL, trans_ err) in the complete-split pipeline stage.
`
`During following microframes, the host controller issues high-speed complete-split transactions to retrieve
`the data/handshake from the high-speed handler. When the high-speed handler receives s complete-split
`transaction, the TT returns whatever data it has received during a microframe. If the full-flow-speed
`transaction was started and completed in a single microframe, the TT returns all the data for the transaction
`in the complete-split response occurring in the following microframe. If the full-flow-speed CRC check
`passes, the appropriate DAT AO/ I PID for the data packet is used. If the full-/low-speed CRC check fails, an
`ERR handshake is used and there is no data packet as part of the complete-split transaction.
`
`If the full-/low-speed transaction spanned a microframe, the TT requires two complete-splits (in two
`subsequent microframes) to return all the data for the full-flow-speed transaction. The data packet PID for
`the first complete-split must be an MDA TA to tell the host controller that another complete-split is required
`for this endpoint. This MDATA response is made without performing a CRC check (since the CRC16 field
`has not yet been received on the full-/low-speed bus). The complete-split in the next microframe must use a
`DAT AO/I PID if the CRC check passes. If the CRC check fails, an ERR handshake response is made
`instead and there is no data packet as part of the complete-split transaction. Since full-speed interrupt
`transactions are limited to 64 data bytes or less (and low-speed interrupt transactions are limited to 8 data
`
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`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`bytes or less), no full-/low-speed interrupt transaction can span more than a single microframe boundary;
`i.e., no more than two microframes are ever required to complete the transaction.
`
`The complete-split transaction for an interrupt IN transaction must not include the CRC16 field received
`from the full-/low-speed data packet (i.e., only a high-speed CRC16 field is used in split transactions). Tbe
`TT must use a high-speed CRC 16 on each complete-split data packet. If the full-speed handler detects a
`failed CRC check, it must use an ERR handshake response in the complete-split transaction to reflect that
`error to the high-speed host controller. The host controller must check the CRCl 6 on each returned
`complete-split data packet. A CRC failure (or ERR handshake) on any (partial) complete-split is reflected
`as a CRC failure on the total full-/low-speed transaction. This means that for a case where a full-/low-speed
`interrupt spans a microframe boundary, the host controller can accept the first complete-split without
`errors, then the second complete-split can indicate that the data from the first complete-split must be
`rejected as if it were never received by the host controller. Figure 11-82 shows an example of an interrupt
`IN and its CRC16 handling with corresponding complete-split responses.
`
`High
`Speed
`Bus
`
`il25us microframe
`:
`!
`Full/Low(cid:173)
`Speed
`Bus
`
`64 bytes w/
`HS CRCI6
`
`Figure 11-82. Example of CRC16 Handling for Interrupt IN
`
`Isochronous Transaction Translation Overview
`11 .21
`Isochronous split transactions are handled by the host by scheduling start- and complete-split transactions as
`described previously. Isochronous IN split transactions have more than two schedule entries:
`
`• One entry for the start-split transaction in the microframe before the earliest the full-speed transaction
`can occur
`
`• Other entries for the complete-splits in microframes after the data can occur on the full-speed bus
`(similar to interrupt IN scheduling)
`
`Furthermore, isochronous transactions are split into microframe sized pieces; e.g., a 300 byte full-speed
`transaction is budgeted multiple high-speed split transactions to move data to/from the TT. This allows any
`alignment of the data for each microframe.
`
`Full-speed isochronous OUT transactions issued by a TT do not have corresponding complete-split
`transactions. They must only have start-split transaction(s).
`
`The host controller must preserve the same order for the complete-split transactions (as for the start-split
`transactions) for IN handling.
`
`394
`
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`
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`

`Universal Serial Bus Specification Revision 2.0
`
`Isochronous INs have start- and complete- split transactions. The "first" high-speed split transaction for a
`full-speed endpoint is always a start-split transaction and the second (and others as required) is always a
`complete-split no matter what the high-speed handler of the TT responds.
`
`The full-/low-speed handler recombines OUT data in its local buffers to recreate the single full-speed data
`transaction and handle the microframe error cases. The full-/low-speed handler splits IN response data on
`microframe boundaries.
`
`Microframe buffers always advance no matter what the interactions with the host controller or the full-speed
`handler.
`
`11.21.1 Isochronous Split Transaction Sequences
`The flow sequence and state machine figures show the transitions required for high-speed split transactions
`for a full-speed isochronous transfer type for a single endpoint. These figures must not be interpreted as
`showing any particular specific timing. In particular, high-speed or full-speed transactions for other
`endpoints may occur before or after these split transactions. Specific details are described as appropriate.
`
`In contrast to bulk/control processing, the full-speed handler must not do local retry processing on the full (cid:173)
`speed bus in response to transaction errors (including timeout) of an isochronous transaction.
`
`Start split
`
`r ·-·- -- -- ---- ----,----------i-·- ·- ·-r-·--------- --·-·1
`i
`i
`i
`I
`If mi<Jdle
`If litst
`If ~II of
`If be~inning
`of ~ayload
`paj,Joad
`of payload
`of pajrload
`I
`I
`I
`I
`I
`I
`I
`I
`i
`I
`I
`I
`st3.
`st2 ·
`st4 ·
`stl ·
`
`SSPLIT-all SSPLIT -begin SSPLIT-mid
`
`SSPLIT-enq
`
`.......... -......................................................... :
`
`st5
`
`sd ?~!. ________ J
`
`T~ans err
`seq
`
`DATAO ,
`; ............................................................... ;
`not tran4_err,
`TransLerr
`Dowrt~error
`Data _info_ SS _pipe
`shli
`se21
`T
`T
`Go to next
`cmd
`
`Figure 11-83. Isochronous OUT Start-split Transaction Sequence
`
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`
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`
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`

`Universal Serial Bus Specification Revision 2.0
`
`Start split
`
`SS PL IT
`
`Data into SS_pipe
`-
`I -
`
`~
`
`Goto
`complete split
`
`jHostj CE]
`
`Figure 11-84. Isochronous IN Start-split Transaction Sequence
`
`In Figure 11-85, the high-speed handler returns an ERR handshake for a "transaction error" of the full-speed
`transaction.
`
`The high-speed handler returns an NYET handshake when it cannot find a matching entry in the complete(cid:173)
`split pipeline stage. This handles the case where the host controller issued the first high-speed complete(cid:173)
`split transaction, but the full-/low-speed handler has not started the transaction yet or has not yet received
`data back from the full-speed device. This can be due to a delay from starting previous full-speed
`transactions.
`
`The transition labeled "T Advance" indicates that the host advances to the next transaction for this full -speed
`endpoint.
`
`The transition labeled "DAdvance" indicates that the host advances to the next data area of the current
`transaction for the current full-speed endpoint.
`
`396
`
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`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`Complete split
`
`cell
`
`;
`
`ce 7j
`
`ce2i
`
`cd 1:
`
`cd2
`
`ctl
`CSP LIT
`Trans err
`,. ................................. - .............. -.................... ct2
`l
`IN
`Fast~match
`!····~~a.;~~-r.!Pt. .. q_.<l..'!!P.!.<!.!!f. ......... , ........ !!..C?...§P.l.!!..!..~~P.Q.rl.~<!.[C?..1:'.!1.4.. .............................. ,
`~ Tra•s err
`i
`~---·-·--t - old!T1F~~=~;;······ .. ··;11i~~;d~;~ ............. ~.ldfmoredata
`I
`;
`r----~~r [ Ef ] [ D::~,O ] [ j~TA] [ NT.~}
`ch4.
`
`eel
`if err _count< 3
`retry immed.
`I.
`comp. sp 1t
`
`l
`j ~--·-·-T Not ~rans_err i
`!
`ce4j
`I not
`i Tra~s_err DA~vance
`trans_frr © c~~-·
`!
`!
`if err c~unt >= 3
`!
`- !
`L'st Not ~ast
`·1
`·
`·
`I
`I
`·
`·
`1
`.~
`i ,~-~~~--~:~ ! r·--:~:t
`l ·-·-·-·T·-·-·-·-·-,
`j
`!
`.
`'·-... L./
`·1.., I . ./
`ch ii
`T
`!
`ch3 l
`Record error
`l _________ T_y
`Not last
`ch4 t_ ________ ! _______ y
`T Ad~ance
`T
`Go to next
`comp. split
`
`I
`·
`
`last
`
`•
`Go to next
`cmd
`
`Figure 11-85. Isochronous IN Complete-split Transaction Sequence
`
`397
`
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`IPR2018-00111
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`11.21.2 Isochronous Split Transaction State Machines
`
`HC_cmd.datapart = alldata
`! lssue_packet(HSD1, SSPLIT); - all
`i ............. ~ ......................................... ft . . . . . . . . . . .
`
`. . . .. . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`HC_cmd.datapart = enddata
`L'~s.~_:.::?.~ .. c~e~~-~~-~!'.. ~~-~~'!.?; == =·nd
`HC_cmd.datapart = begindata
`lssue_packet(HSD1 , SSPLIT); -- begin
`
`st3
`
`!
`
`HC_cmd.datapart = middata
`lssue_packet(HSD1 , SSPLIT); -- middata
`
`lssue_packet(HSD1, tokenOUT);
`
`lssue_packet(HSD1, DATAx);
`
`· RespondHC(Do_next_cmd);
`................................................................................... ~
`__ H_C ___ D_o_- ,s-o-ch_O_s_s __ I
`
`Figure 11-86. Isochronous OUT Start-split Transaction Host State Machine
`
`398
`
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`IPR2018-00111
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`HSD2.PID = DATAx and HSD2.CRC16 = ok and
`split.datapart = enddata and SS_Buff.isochO and
`(SS_Buff.lastdata = middata or
`SS_Buff.lastdata = begindata)
`
`r, f .............. ,.,_ .......................... _ ....... - ............ - ... ~····--··-·"t
`i SS_Buff.isochO <=false;
`: SS_Buff.saw_split <=false;
`1 ... ?..~.t·~=i~·t·~=~-~=-~·i·~:: .................................. :
`
`HSD2.PID = DATAx and HSD2.CRC16 = ok and
`split.datapart = middata and SS_Buff.isochO and
`(SS_Buff.lastdata = begindata or
`SS_Buff.lastdata = middata)
`
`SS_Buff.lastdata <= middata;
`: SS_Buff.saw_split <=true;
`Data_into _SS __pipe;
`
`.............. - ............................................................... - .............................. !
`HSD2.PID = DATAx and
`HSD2.CRC16 = ok and
`split.datapart = begindata and
`(not SS_Buff.isochO)
`
`!
`I
`
`st4
`
`st2
`
`SS_Buff.isochO <=true;
`SS_Buff.lastdata <= begindata;
`SS_Buff.saw_split <=true;
`Data_into_ SS __pipe;
`
`! Packet_ready(HSD2)
`
`!
`
`SS_Buff.isochO
`SS_Buff.isochO <=false;
`Down_error;
`
`I TT _Do_lsochOSS
`Figure 11-87. Isochronous OUT Start-split Transaction TT State Machine
`
`There is a condition in Figure 11-87 on transition sel/se2 labeled "Bad_IsochOut". This condition is true
`when none of the conditions on transitions stl through st4 are true. The action labeled "Down_er~or"
`records an error to be indicated on the downstream facing full-speed bus for the transaction corresponding
`to this start-split.
`
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`
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`

`Universal Serial Bus Specification Revision 2.0
`
`~sl1
`f ·----"' .. -~· - ,._ ...
`! ... '~~.~'.::?.~:~=~~.~~-o.:.:.~~.~~~.~!.'. ... _.J
`
`· ···· · ·· ········ ······ ·· ···~
`
`r··········-··-··-····· .. ................. ......................... .............................. ""!
`~~~~~~~~~~~;
`
`! RespondHC(Do_complete);
`,
`• ...................................................... ~ ....................... ;
`
`HC_Do_lsochlSS
`
`Figure 11-88. Isochronous IN Start-split Transaction Host State Machine
`
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`Universal Serial Bus Specification Revision 2.0
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`HSU2.PID = DATAx and
`HSU2.CRC16 = ok
`HC _Accept_data;
`
`i HSU2.PID = MDATA and
`i HSU2.CRC16 = ok
`
`HSU2.PID = NYET
`
`· HC_cmd.last
`
`;.,.~·········--·-···--······· ............................... -...• -................ -~·······;
`
`................................................................ _____
`
`HSU2.PID = ERR
`
`(HSU2.PID = MDATA or
`, HSU2.PID = DATAx) and
`. HSU2.CRC16 =bad
`
`ErrorCount < 3
`RespondHC(Do_comp_immed_now);
`l
`t ... 3 ..
`1 E C
`i ....... r..r.o·~-.. ~~.~--~~ ........... i
`
`ce3
`
`lssue__packet(HSD1, token IN);
`
`. (HSU2.PID /= NYET and
`: HSU2.PID /= DATAx and
`- HSU2.PID /= MDATA and
`HSU2.PID /=ERR) or
`HSU2.timeout
`
`lssue__packet(HSD1 , CSPLIT);
`ct1
`~ -- - - - - · ... -·-·-- _____ ..
`
`HC_Do_lsochlCS
`
`Figure 11-89. Isochr onous IN Complete-split Transaction Host State Machine
`
`In Figure 11-89, the transition "ce8" occurs when the high-speed handler responds with an MDA TA to
`indicate there is more data for the full-speed transaction, but the host controller knows that this is the last
`scheduled complete-split for this endpoint for this frame. If a DAT AO response from the high-speed
`handler is not received before the last scheduled complete-split, the host controller records an error and
`proceeds to the next transaction for this endpoint (in the next frame).
`
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`Universal Serial Bus Specification Revision 2.0
`
`: ...............•....... --···-···· .. ··---.. -···--·· .................... J
`
`TT_Do_lsochlSS
`
`Figure 11-90. Isochronous IN Start-split Transaction TI State Machine
`
`token.PIO/= tokenlN or
`~-~ token. timeout
`
`cd2
`
`1 CS Buff.match.down result= r moredata
`l
`-
`-
`-
`.
`lssue_packet(HSU1 , MDATA);
`
`CS_Buff.match.down_result = r_lastdata
`lssue_packet(HSU1, DATAx); -- DataO
`;. ........................ -............................................................ "" ........................................... ..
`
`... -. .. --····-· ··· ··--···· ····· ·~ .............................................. -................................................ .,
`CS_Buff.match.down_result = r_trans_err
`lssue_packet(HSU1, ERR);
`
`CS_Buff.match.state = no_match
`lssue_packet(HSU1, NYET);
`
`-D
`
`I CS_Buff.match.state = match_busy
`
`l,,,,,,, .. -
`
`...... ,H_•••·•- • .. o o . . OOM•••••''"°' ................. ,, ...................... , ... , ......... ,.,,__,.,,.,.,,. .. .
`
`Figure 11-91. Isochronous IN Complete-split Transaction TI State Machine
`
`TT _lsochlCS
`
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`
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`

`Universal Serial Bus Specification Revision 2.0
`
`11.21.3 Isochronous OUT Sequencing
`The host controller and IT must ensure that errors that can occur in split transactions of an isochronous full(cid:173)
`speed transaction translate into a detectable error. For isochronous OUT split transactions, once the high(cid:173)
`speed handler has received an "SSPLlT-begin" start-split transaction token packet, the high-speed handler
`must track start-split transactions that are received for this endpoint. The high-speed handler must track that
`a start-split transaction is received each and every microframe until an "SSPLIT-end" split transaction token
`packet is received for this endpoint. If a microframe passes without the high-speed handler receiving a
`start-split for this full-speed endpoint, it must ensure that the full-speed handler forces a bitstuff error on the
`full-speed transaction. Any subsequent "SPLIT-middle" or "SPLIT-end" start-splits for the same endpoint
`must be ignored until the next non "SPLIT-middle" and non "SPLIT-end" is received (for any endpoint
`supported by this IT).
`
`The start-split transaction for an isochronous OUT transaction must not include the CRC16 field for the full(cid:173)
`speed data packet. For a full-speed transaction, the host would compute the CRC16 of the data packet for
`the full data packet (e.g., a 1023 byte data packet uses a single CRC16 field that is computed once by the
`host controller). For a split transaction, any isochronous OUT full-speed transaction is subdivided into
`multiple start-splits, each with a data payload of 188 bytes or less. For each of these start-splits, the host
`computes a high-speed CRC16 field for each start-split data packet. The IT high-speed handler must check
`each high-speed CRC16 value on each start-split. The IT full-speed handler must locally generate the
`CR Cl 6 value for the complete full-speed data packet. Figure 11-92 shows an example of a full-speed
`isochronous OUT packet and the high-speed start-splits with their CRC16 fields.
`
`lf there is a CRC check failure on the high-speed start-split, the high-speed handler must indicate to the full(cid:173)
`speed handler that there was an error in the start-split for the full-speed transaction. If the transaction has
`been indicated as having a CRC failure (or ifthere is a missed start-split), the full-speed handler uses the
`defined mechanism for forcing a downstream corrupted packet. If the first start-split has a CRC check
`failure, the full-speed transaction must not be started on the downstream bus.
`
`Additional high-speed start-split transactions for the same endpoint must be ignored after a CRC check fails,
`until the high-speed handler receives either an "SSPLlT-end" start-split transaction token packet for that
`endpoint or a start-split for a different endpoint.
`
`High
`Speed
`Bus
`I ! 188 byte w
`I l : I
`j HS CRC16
`jl 25us microframe ~
`
`I
`
`I
`I
`
`I
`
`Full
`Speed
`Bus
`
`188 bytes 2 bytes
`Figure 11-92. Example ofCRC16 Isochronous OUT Data Packet Handling
`
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`Universal Serial Bus Specification Revision 2.0
`
`11.21.4 Isochronous IN Sequencing
`The complete-split transaction for an isochronous IN transaction must not include the CRCJ 6 field for the
`full-speed data packet (e.g., only a high-speed CRCI 6 field is used in split transactions). The TT must not
`pass the full-speed value received from the device and instead only use high-speed CRC 16 values for
`complete-split transactions. If the full-speed handler detects a failed CRC check at the end of the data
`packet (e.g., after potentially several complete-split transactions on high-speed), the handler must use an
`ERR handshake response to reflect that error to the high-speed host controller. The host controller must
`check the CRC J 6 on each returned high-speed complete-split. A CRC failure (or ERR handshake) on any
`(partial) complete-split is reflected by the host controller as a CRC failure on the total full-speed transaction.
`Figure 1 I -93 shows an example of the relationships of the full-speed data packet and the high-speed
`complete-splits and their CRCJ 6 fields.
`
`High
`Speed
`Bus
`
`p 2sus microframe
`!
`Full
`Speed
`Bus
`
`1 byte w/
`HS CRCl6
`
`188 bytes
`Figure 11-93. Example of CRC16 Isochronous IN Data Packet Handling
`
`11.22 TT Error Handling
`The TT has the same requirements for handling errors as a host controller or hub. In particular:
`
`•
`
`•
`
`•
`
`If the IT is receiving a packet at EOF2 of the downstream facing bus, it must disable the downstream
`facing port that is currently transmitting.
`
`If the TT is transmitting a packet near EOFl of the downstream facing bus, it must force an abnormal
`termination sequence as defined in Section 1 1.3.3 and stop transmitting.
`
`If the IT is going to transmit a non-periodic full-flow-speed transaction, it must determine that there is
`sufficient time remaining before EOFJ to complete the transaction. This determination is based on
`nonnal sequencing of the packets in the transaction. Since the IT has no information about data
`payload size for INs, it must use the maximum allowed size allowed for the transfer type in its
`determination. Periodic transactions do not need to be included in this test since the microframe
`pipeline is maintained separately.
`
`11.22.1 Loss of TT Synchronization With HS SOFs
`The hub has a timer it uses for (micro)frame maintenance. It has a 1 ms frame timer when operating at full(cid:173)
`/ low-speed for enforcing EOF with downstream connected devices. It has a 125 µs microframe timer when
`operating at high-speed for enforcing EOF with high-speed devices. It also uses the 125 µs microframe
`timer to create a 1 ms frame timer for enforcing EOF with downstream full-flow-speed devices when
`operating at high-speed. The hub (micro)frame timer must always stay synchronized with host generated
`SOFs to keep the bus operating correctly
`
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`

`Universal Serial Bus Specification Revision 2.0
`
`In normal hub repeater (full- or high-speed) operation (e.g., not involving a TT), the (micro)frame timer
`loses synchronization whenever it has missed SOFs for three consecutive microframes. While timer
`synchronization is lost, the hub does not establish upstream connectivity. Downstream connectivity is
`established normally, even when timer synchronization is lost. When the timer is synchronized, the hub
`allows upstream connectivity to be established when required. The hub is responsible for ensuring that
`there is no signaling being repeated/transmitted upstream from a device after the EOF2 point in any
`(micro)frame. The hub must not establish upstream connectivity ifit has lost (micro)frame timer
`synchronization since it no longer knows accurately where the EOF2 point is.
`
`11 .22.2 TT Frame and Microframe Timer Synchronization Requirements
`When the hub is operating at high-speed and has full-flow-speed devices connected on its downstream
`facing ports (e.g., a TT is active), the hub has additional responsibilities beyond enforcement of the (high(cid:173)
`speed) EOF2 point on its upstream facing port in every microframe. The TT must also generate full-speed
`SOFs downstream and ensure that the TT operates correctly (in bridging high-speed and full-flow-speed
`operation).
`
`A high-speed operating hub synchronizes its microframe timer to 125 µs SOFs. However, in order to
`generate full-speed downstream SOFs, it must also have a l ms frame timer. lt generates this l ms frame
`timer by recognizing zeroth microframe SOFs, e.g., a high-speed SOF when the frame number value
`changes compared to SOF of the immediately previous microframe.
`
`In order to create the l ms frame timer, the hub must successfully receive a zeroth microframe SOF after its
`microframe timer is synchronized. In order to recognize a zeroth microframe SOF, the hub must
`successfully receive SOFs for two consecutive microframes where the frame number increments by 1 (mod
`2" I l ). When the hub has done this, it knows that the second SOF is a zeroth microframe SOF and thereby
`establishes a l ms frame timer starting time. Note that a hub can synchronize both timers with as few as
`two SOFs if the SOFs are for microframe 7 and microframe 0, i.e., if the second SOF is a zeroth
`microframe SOF.
`
`Once the hub has synchronized its l ms frame timer, it can keep that timer synchronized as long as it keeps
`its 125 µs microframe timer synchronize