`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`LG Electronics, Inc., LG Electronics U.S.A. Inc., LG Electronics
`Mobilecomm U.S.A. Inc., LG Electronics Mobile Research U.S.A.
`LLC, and LG Electronics Alabama, Inc.,
`
`Petitioner
`
`v.
`
`Fundamental Innovation Systems International LLC,
`
`Patent Owner.
`
`
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 8,624,550 B2
`
`Case No. IPR2018-00460
`
`
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`
`
`
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`
`

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`
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`TABLE OF CONTENTS
`
`I.
`
`Mandatory Notices (37 C.F.R. § 42.8) ............................................................ 1
`
`A.
`
`B.
`
`C.
`
`Real Parties-in-Interest (§ 42.8(B)(1)) .................................................. 1
`
`Related Matters (§ 42.8(B)(2)) .............................................................. 1
`
`Counsel Information (§ 42.8(b)(3)) ....................................................... 2
`
`II.
`
`Payment of Fees (§ 42.15(A)) ......................................................................... 3
`
`III. Grounds for Standing (§ 42.104(A)) ............................................................... 3
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`IV.
`
`’550 Patent Background .................................................................................. 3
`
`A.
`
`B.
`
`C.
`
`Summary ............................................................................................... 3
`
`Prosecution History ............................................................................... 4
`
`Priority Date .......................................................................................... 4
`
`V.
`
`Technology Background .................................................................................. 6
`
`A.
`
`B.
`
`Person of Ordinary Skill in the Art ....................................................... 6
`
`State of the Art ...................................................................................... 6
`
`VI. Claim Construction (§ 42.104(B)(3)) ............................................................15
`
`VII. Grounds of Rejection (§ 42.104(B)(1)-(2), (4)) ............................................17
`
`A. Ground 1: Dougherty anticipates claims 1-3, 9-12, and 18. ...............17
`
`1.
`
`2.
`
`Dougherty ..................................................................................17
`
`Application of Dougherty to claims 1-3, 9-12, and
`18 ...............................................................................................25
`
`B.
`
`Ground 2: Dougherty and Shiga render obvious claims 4-8 and 13-
`17. ........................................................................................................41
`
`1.
`
`Shiga ..........................................................................................41
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`Patent 8,624,550 B2
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`2.
`
`3.
`
`The Dougherty/Shiga combinations .........................................46
`
`Application of the Dougherty/Shiga combinations
`to claims 4-8 and 13-17 .............................................................56
`
`C.
`
`Neither ground is redundant. ...............................................................63
`
`VIII. Conclusion .....................................................................................................64
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`
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`Exhibit Description
`
`U.S. Patent 8,624,550
`
`EXHIBIT LIST
`
`
`Short Name
`
`’550 patent
`
`1001
`
`1002
`
`1003
`
`1004
`
`1005
`
`1006
`
`1007
`
`1008
`
`1009
`
`1010
`
`1011
`
`1012
`
`1013
`
`
`
`
`
`File History of U.S. Patent 8,624,550
`
`’550 file history
`
`U.S. Provisional Application 60/273,021
`
`’021 provisional
`
`U.S. Provisional Application 60/330,486
`
`’486 provisional
`
`U.S. Patent 7,360,004
`
`U.S. Patent 6,625,738
`
`Universal Serial Bus Specification,
`Revision 1.1, September 23, 1998
`
`Universal Serial Bus Specification,
`Revision 2.0, April 27, 2000
`
`Declaration of Mr. James Geier in
`Support of the Petition for Inter Partes
`Review of U.S. Patent 8,624,550
`
`U.S. Patent 6,625,790
`
`Cypress CY7C63722/23 CY7C63742/43
`enCoRe™ USB Combination Low-Speed
`USB & PS/2 Peripheral Controller
`(Cypress enCoRe or Cypress Datasheet),
`by Cypress Semiconductor Corporation,
`published May 25, 2000
`
`Dougherty
`
`Shiga
`
`USB 1.1
`
`USB 2.0
`
`Geier
`
`Casebolt
`
`Cypress datasheet
`
`U.S. Patent 6,531,845
`
`Kerai
`
`File History of U.S. Patent No. 7,360,004
`
`Dougherty file history
`
`
`
`
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`Patent 8,624,550 B2
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`Petitioner, LG Electronics, Inc., LG Electronics U.S.A. Inc., LG Electronics
`
`Mobilecomm U.S.A. Inc., LG Electronics Mobile Research U.S.A. LLC, and LG
`
`Electronics Alabama, Inc., requests inter partes review (“IPR”) of claims 1-18 of
`
`U.S. Patent No. 8,624,550 B2 (“the ’550 patent”). As explained below, there is a
`
`reasonable likelihood that Petitioner will prevail on at least one claim challenged in
`
`this petition.
`
`I. Mandatory Notices (37 C.F.R. § 42.8)
`
`A. Real Parties-in-Interest (§ 42.8(B)(1))
`
`LG Electronics, Inc., LG Electronics U.S.A. Inc., LG Electronics
`
`Mobilecomm U.S.A. Inc., LG Electronics Mobile Research U.S.A. LLC, and LG
`
`Electronics Alabama, Inc., are the real parties-in-interest.
`
`B. Related Matters (§ 42.8(B)(2))
`
`The ’550 patent is the subject of Civil Action Nos. 2:17-cv-00145-JRG,
`
`2:16-cv-01424-JRG-RSP, and 2:16-cv-01425-JRG-RSP, which are pending in the
`
`U.S. District Court for the Eastern District of Texas, and Civil Action No. 3:17-cv-
`
`01827-N, which is pending in the U.S. District Court for the Northern District of
`
`Texas.1
`
`The ’550 patent is subject to ZTE (USA) Inc. et al., v. Fundamental
`
`
`1 The unpatentability positions herein take into account Patent Owner’s
`infringement positions in the co-pending litigation and in some instances are based
`in-part on these positions.
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`Patent 8,624,550 B2
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`Innovation Systems International LLC, IPR2018-00110, and pending institution.
`
`The ’550 patent is also subject to IPR2018-00111, also filed by ZTE (USA) Inc. et
`
`al. and pending institution. Petitioner is also challenging the ’550 patent in
`
`IPR2018-00461, which is pending institution and substantially identical as
`
`IPR2018-00111.
`
`This petition is substantially identical to IPR2018-00110, and Petitioner will
`
`seek joinder with IPR2018-00110 under 35 U.S.C. § 315(c), 37 C.F.R. §§ 42.22
`
`and 42.122(b).
`
`Petitioner is unaware of any other pending matter that would affect, or by
`
`affected by, a decision in this proceeding.
`
`C. Counsel Information (§ 42.8(b)(3))
`
`
`
`Lead Counsel
`David L. McCombs
`HAYNES AND BOONE, LLP
`2323 Victory Ave. Suite 700
`Dallas, TX 75219
`Back–up Counsel
`Gregory P. Huh
`HAYNES AND BOONE, LLP
`2323 Victory Ave. Suite 700
`Dallas, TX 75219
`
`David M. O’Dell
`HAYNES AND BOONE, LLP
`2323 Victory Ave. Suite 700
`Dallas, TX 75219
`
`
`214-651-5533
`Phone:
`214-200-0853
`Fax:
`
`david.mccombs.ipr@haynesboone.com
`USPTO Reg. No. 32,271
`
`972-739-6939
`Phone:
`214-200-0853
`Fax:
`
`gregory.huh.ipr@haynesboone.com
`USPTO Reg. No. 70,480
`
`972-739-8635
`Phone:
`214-200-0853
`Fax:
`
`david.odell.ipr@haynesboone.com
`USPTO Reg. No. 42,044
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`Please address all correspondence to lead and back-up counsel. Petitioner
`
`consents to electronic service.
`
`II.
`
`Payment of Fees (§ 42.15(A))
`
`Petitioner authorizes the Office to charge the filing fee and any other
`
`necessary fee to Deposit Account 08-1394.
`
`III. Grounds for Standing (§ 42.104(A))
`
`Petitioner certifies that: (i) the ’550 patent is available for IPR and
`
`(ii) Petitioner is not barred or estopped from requesting an IPR challenging the
`
`’550 patent’s claims.
`
`IV.
`
`’550 Patent Background
`
`A.
`
`Summary
`
`The ’550 patent relates to “[a]n adapter for providing a source of power to a
`
`mobile device through an industry standard port.”2 The ’550 patent has 18 claims.
`
`Independent claims 1 and 10 are provided below.
`
`1. An adapter comprising:
`a USB VBUS line and a USB communication path,
`said adapter configured to supply current on the VBUS line
`
`without regard to at least one associated condition speci-
`
`fied in a USB specification.
`
`
`10. An adapter comprising:
`a USB VBUS line and a USB communication path,
`said adapter configured to supply current on the VBUS line
`
`2 Ex. 1001 (“’550 patent”) at 2:19-20.
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`B.
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`without regard to at least one USB Specification
`imposed limit.
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`Prosecution History
`
`The ’550 patent issued from U.S. Patent Application No. 13/536,767, which
`
`was filed on June 28, 2012. That same day, the applicant cancelled all pending
`
`claims and added 18 new claims.3
`
`On May 28, 2013, the examiner rejected all pending claims based upon
`
`obviousness-type double patenting over claims 1-12 of U.S. Patent No. 7,986,127.4
`
`In response, on August 7, 2013, the applicant filed a terminal disclaimer.5
`
`On September 5, 2013, the examiner issued a notice of allowance.6 Before
`
`the patent issued, the applicant requested an amendment after allowance on
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`November 19, 2013, to “correct minor clerical errors” and to “correct a
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`typographical error” made to claim 27.7 The examiner approved the amendments,
`
`and the ’550 patent issued on January 7, 2014.8
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`C.
`
`Priority Date
`
`The ’550 patent claims priority through a series of continuations to two
`
`provisional applications: (1) U.S. Provisional Application No. 60/273,021 (“the
`
`
`3 Ex. 1002 (“’550 file history”) at 216.
`4 ’550 file history at 103-107.
`5 ’550 file history at 95-98.
`6 ’550 file history at 81-84.
`7 ’550 file history at 50-60.
`8 ’550 file history at 41.
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`’021 provisional”) (Ex. 1003), filed March 1, 2001; and (2) U.S. Provisional
`
`Application No. 60/330,486 (“the ’486 provisional”) (Ex. 1004), filed October 23,
`
`2001. However, at least claims 4-8 and 13-17 of the ’550 patent are not entitled to
`
`the ’021 provisional’s filing date because the ’021 provisional does not provide
`
`written description support for the following claim elements:
`
`(i)
`
`said current is supplied in response to an abnormal data condition on
`
`said USB communication path (claims 4 and 13);
`
`(ii)
`
`said abnormal data condition is an abnormal data line condition on
`
`said D+ line and said D- line (claims 6 and 15);
`
`(iii)
`
`said abnormal data line condition is a logic high signal on each of said
`
`D+ and D- lines (claims 7 and 16); and
`
`(iv) each said logic high signal is greater than 2V (claims 8 and 17).9
`
`The later-filed ’486 provisional is the first application in the priority chain that
`
`potentially provides written description for these claim elements.10 Thus, the
`
`earliest potential priority date for claims 4-8 and 13-17 is October 23, 2001.11
`
`
`9 Ex. 1009 (“Geier”) at ¶¶ 28-30.
`10 ’486 provisional, at 14:9-15:17.
`11 The analysis in this petition remains the same regardless of whether the ’550
`patent’s claims are entitled to a priority date of March 1, 2001 or October 23, 2001.
`Both grounds in this petition apply even if the claims are entitled to the March 1,
`2001 filing date.
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`V. Technology Background
`
`A.
`
`Person of Ordinary Skill in the Art
`
`The person of ordinary skill in the art (POSITA) of the subject matter of the
`
`’550 patent would have had a master’s degree in electrical engineering, computer
`
`science, or a related field, plus 2-3 years of experience with Universal Serial Bus
`
`(“USB”). Along with this petition, Petitioner submits the declaration of James T.
`
`Geier, who has been a POSITA since at least the ’550 patent’s claim priority
`
`date.12
`
`B.
`
`State of the Art
`
`As of March 2001, POSITAs would have been familiar with the USB
`
`Implementers Forum, Inc. (“USB-IF”), which has been responsible for the
`
`advancement and adoption of USB technology since its inception in 1995.13 As of
`
`December 2000, USB-IF had more than 900 member companies that helped
`
`facilitate the development of USB.14
`
`POSITAs would have also been familiar with the USB specification and its
`
`various revisions.15 On September 23, 1998, USB-IF released Universal Serial Bus
`
`Specification, Revision 1.1 (“USB 1.1”), which was widely adopted by industry
`
`
`12 Geier at ¶¶ 3-6, 23.
`13 Geier at ¶ 31.
`14 Geier at ¶ 31.
`15 Geier at ¶ 32.
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`leaders and consumers.16 On April 27, 2000, USB-IF released USB Revision 2.0
`
`(“USB 2.0”).17 Among USB 2.0’s improvements were faster speeds and additional
`
`functionality.18
`
`POSITAs would have also understood the architecture for a USB system.19
`
`Generally, a USB system includes a USB host, one or more USB devices, and a
`
`USB interconnect.20 A USB host (e.g., a laptop computer system) interacts with
`
`USB devices and is responsible for tasks such as (i) detecting the attachment and
`
`removal of USB devices; (ii) managing control and data flow between the host and
`
`USB devices; (iii) collecting status and activity statistics; and (iv) providing power
`
`to attached USB devices.21 A USB device connects to the USB host, and falls into
`
`one of two categories: (i) a hub, which has the ability to provide additional USB
`
`attachment points, or (ii) a function, which is a device that is able to transmit or
`
`receive data or control information over the USB bus (e.g., a peripheral device,
`
`such as a keyboard, mouse, or mobile phone).22 A USB interconnect is the manner
`
`in which USB devices are connected and communicate with the host.23 The
`
`
`16 Geier at ¶ 32 (citing Ex. 1007 (“USB 1.1”) at 1).
`17 Geier at ¶ 32 (citing Ex. 1008 (“USB 2.0”) at 1).
`18 Geier at ¶ 32.
`19 Geier at ¶¶ 33-35.
`20 Geier at ¶¶ 33 (citing USB 2.0 at 15; USB 1.1 at 15).
`21 Geier at ¶ 33 (citing USB 2.0 at 24; USB 1.1 at 24).
`22 Geier at ¶ 33 (citing USB 2.0 at 22-24; USB 1.1 at 21-24).
`23 Geier at ¶ 33 (citing USB 2.0 at 15; USB 1.1 at 15).
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`following figure from USB 2.0 depicts a typical configuration of a USB host,
`
`interconnect, and device(s):24
`
`
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`
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`From the USB specifications, POSITAs would have also understood the
`
`USB cable structure.25 As of the claimed priority date, the USB cable “consist[ed]
`
`of four conductors, two power conductors, and two signal conductors.”26 The
`
`following figure from USB 2.0 depicts the four wires within a USB cable.27
`
`
`24 Geier at ¶ 33 (citing USB 2.0 at Figure 4-4).
`25 Geier at ¶ 34 (citing USB 2.0 at 86; USB 1.1 at 74).
`26 Geier at ¶ 34 (citing USB 2.0 at 86; USB 1.1 at 74).
`27 Geier at ¶ 34 (citing USB 2.0 at Figure 4-2).
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`VBUS and GND deliver power, and D+ and D- carry signals for communication
`
`between a USB host and the connected device.28
`
`POSITAs would have also understood the USB connector structure.29 USB
`
`1.1 and USB 2.0 specified Series “A” and Series “B” connectors.30 “Table 6-1
`
`provides the standardized contact terminating assignments by numbers and
`
`electrical value for Series ‘A’ and Series ‘B’ connectors.”31
`
`According to USB 1.1 and USB 2.0, “[a]ll USB devices must have the standard
`
`28 Geier at ¶ 34 (citing USB 2.0 at 17-18; USB 1.1 at 17).
`29 Geier at ¶ 35 (citing USB 2.0 at 85, 94; USB 1.1 at 73, 82).
`30 Id.
`31 Geier at ¶ 35 (USB 2.0 at 94; USB 1.1 at 82).
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`Series ‘A’ connector.”32 “The ‘B’ connector allows device vendors to provide a
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`standard detachable cable.”33
`
`
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`POSITAs would have also understood how the USB host configured a USB
`
`device. For example, USB 2.0 stated that “[w]hen a USB device is attached to or
`
`removed from the USB, the host uses a process known as bus enumeration to
`
`identify and manage the device state changes necessary.”34 In its “Bus
`
`Enumeration” section, USB 2.0 specified the bus-enumeration requirements,
`
`
`32 USB 2.0 at 85; see also USB 1.1 at 73.
`33 Id.
`34 Geier at ¶ 36 (citing USB 2.0 at 243).
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`including eight actions taken “[w]hen a USB device is attached to a powered
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`port.”35
`
`POSITAs would have also understood that USB 2.0 imposed current limits
`
`on VBUS. For example, USB 2.0 limited a USB device’s current draw on VBUS
`
`to “one unit load [i.e., 100 mA] or less until configured.”36 USB 2.0 also stated that
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`“[d]epending on the power capabilities of the port to which the device is attached,
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`a USB device may be able to draw up to five unit loads [i.e., 500 mA] from VBUS
`
`after configuration.”37
`
`POSITAs would have also understood that USB 2.0 imposed voltage limits
`
`on VBUS.38 For example, USB 2.0 imposed a 5.25 V limit on the VBUS line.39
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`
`
`POSITAs would have also known about the different signaling states on the
`
`D+ and D- lines.40 Some of these states (e.g., Differential 0, Differential 1, Data J
`
`State, and Data K State) transmit data while others (e.g., Single-ended 0, Single-
`
`35 Id.
`36 Geier at ¶ 37 (citing USB 2.0 at 245).
`37 Id.
`38 Geier at ¶ 38.
`39 Geier at ¶ 38 (quoting USB 2.0 at 175, 178).
`40 Geier at ¶ 39-40 (citing USB 2.0 at 123).
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`Ended 1) are used as specific signaling conditions.41 Relevant to this petition is the
`
`SE1 condition.42 USB 2.0 defined “SE1” as “a state in which both the D+ and D-
`
`lines are at a voltage above VOSE1 (min), which is 0.8 V.”43 USB 2.0 also taught
`
`that the low- and full-speed USB drivers “must never ‘intentionally’ generate an
`
`SE1 on the bus.”44 In other words, according to USB 2.0, an abnormal data
`
`condition would occur if D+ and D- were intentionally set in a high state above 0.8
`
`V.45
`
`
`41 Geier at ¶ 39 (citing USB 2.0 at 144-146, Table 7-2).
`42 Id.
`43 Geier at ¶ 39 (citing USB 2.0 at 123).
`44 Id.
`45 Geier at ¶ 39.
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`Finally, POSITAs would have also known that the SE1 condition would be a
`
`logical choice for signaling information about a device without interfering with
`
`USB signaling.46 For example, Casebolt taught that SE1 could be used as a special
`
`signaling mode.47 Specifically, as shown below, the D+ and D- data lines would be
`
`connected to Vcc (+5V) to signal a PS/2 adapter.48
`
`
`
`
`46 Geier at ¶ 40.
`47 Under pre-AIA § 102(e), Ex. 1010, U.S. Patent No. 6,625,790 (“Casebolt”) is
`prior art to every claim of the ’550 patent. Casebolt’s filing date, October 1, 1999,
`predates the ’550 patent’s earliest claimed priority date, March 1, 2001.
`48 Ex. 1010 (“Casebolt”) at FIG. 2C (annotated), 7:41-54, Table 1.
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`Indeed, knowledge of SE1 was so common that Cypress Semiconductor integrated
`
`it into their enCoRe product, stating “USB D+ and D- lines can also be used for
`
`PS/2 SCLK and SDATA pins, respectively. With USB disabled, these lines can be
`
`placed in a high impedance state that will pull up to VCC.”49 As yet another
`
`example, Kerai used a high state on USB D+ and D- for charging.50 As shown
`
`below, both USB D+ and D- (yellow) are brought to a high state in cooperation
`
`with the charging system (green) for a special charging mode.51
`
`
`49 Ex. 1011 (Cypress datasheet) at 21, 22, 24, 25, 41. Under pre-AIA § 102(b), Ex.
`1011, the Cypress datasheet is prior art to every claim of the ’550 patent. The
`Cypress datasheet’s publication date, May 25, 2000, predates the ’550 patent’s
`earliest claimed priority date, March 1, 2001.
`50 Ex. 1012 (“Kerai”) at FIG. 3 (annotated). Under pre-AIA § 102(e), Kerai is prior
`art to every claim of the ’550 patent. Kerai’s filing date, November 23, 1999,
`predates the ’550 patent’s earliest claimed priority date, March 1, 2001.
`51 Geier at ¶ 40 (citing Kerai at FIG. 3).
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`Therefore, a POSITA would have understood that a high state on USB D+ and D-
`
`lines could be used in a variety of contexts, including PS/2 (e.g., Casebolt’s PS/2
`
`adapter), standard USB (e.g., the keyboard in Shiga52), and others (e.g., Kerai’s
`
`charging scheme) and was not restricted to a single application.53
`
`VI. Claim Construction (§ 42.104(B)(3))
`
`The challenged claims receive the broadest reasonable interpretation (BRI)
`
`in light of the specification of the ’550 patent. 37 C.F.R. § 42.100(b). Under the
`
`BRI standard, the Board should construe USB enumeration54 (which appears in
`
`claims 3 and 12) as “the bus-enumeration procedure specified in the USB 2.0
`
`specification or an earlier USB specification” at the time of the alleged invention.
`
`52 See Section VII.B.1.b (pp. 40-43).
`53 Geier at ¶ 40.
`54 This petition uses italics to refer to claim language in the ’550 patent.
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`The “USB” modifier in USB enumeration indicates that USB enumeration
`
`refers to an enumeration procedure specified in a USB specification.
`
`The ’550 patent repeatedly refers to enumeration as a procedure specified in
`
`a then-existing USB specification (i.e., USB 2.0 or earlier). For example, the ’550
`
`patent states that “[i]n accordance with the USB specification, typical USB power
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`source devices, such as hubs and hosts, require that a USB device participate in a
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`host-initiated process called enumeration in order to be compliant with the current
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`USB specification in drawing power from the USB interface.”55 As another
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`example, the ’550 patent states that “[t]he USB specifies a process for transferring
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`energy across the USB called enumeration and limits the electrical current that can
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`flow across the USB.”56
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`From this disclosure, POSITAs would have understood that when the ’550
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`patent’s specification refers to “enumeration,” it is referring to a specific bus-
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`enumeration procedure in the USB 2.0 specification or an earlier USB
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`specification.57 For example, the ’550 patent describes enumeration as a “host-
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`initiated process” needed “to be compliant with the current USB specification in
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`drawing power from the USB interface.”58 Consistent with the ’550 patent’s
`
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`55 ’550 patent at 2:3-7.
`56 ’550 patent at 8:17-20.
`57 Geier at ¶ 41.
`58 ’550 patent at 2:3-7.
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`description at column 2, lines 3-7, the USB 2.0 specification describes bus
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`enumeration as a host-initiated process that a USB device must undergo before it
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`can communicate data over the USB interface.59 See Section V.B (pp. 6-15). Thus,
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`in the context of the ’550 patent, POSITAs would have immediately recognized
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`that “enumeration” refers to the bus-enumeration procedure in the USB 2.0
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`specification or an earlier USB specification.60
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`VII. Grounds of Rejection (§ 42.104(B)(1)-(2), (4))
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`Petitioner requests that the Board review and cancel claims 1-18 of the ’550
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`patent on the following grounds.
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`Ground Claims
`1
`1-3, 9-12, 18
`2
`4-8, 13-17
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`Reference(s)
`Basis
`pre-AIA 35 U.S.C. § 102(e) Dougherty
`pre-AIA 35 U.S.C. § 103(a) Dougherty and Shiga
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`A. Ground 1: Dougherty anticipates claims 1-3, 9-12, and 18.
`
`1.
`
`Dougherty
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`In this petition, “Dougherty” refers to Exhibit 1005, which is U.S. Patent No.
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`7,360,004, naming Michael J. Dougherty as its first-named inventor. Dougherty
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`was not cited to the Patent Office or considered by the examiner during the
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`prosecution of the application that issued as the ’550 patent.61
`
`
`59 Geier at ¶ 36 (citing USB 2.0 at 243).
`60 Geier at ¶¶ 36, 41.
`61 During prosecution, the applicant cited Dougherty’s parent patent, U.S. Patent
`No. 6,668,296 (“the ’296 patent”), along with 71 other documents, in an
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`a.
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`Prior art status
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`Under pre-AIA 35 U.S.C. § 102(e), Dougherty is prior art to every claim of
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`the ’550 patent. Dougherty’s effective filing date, June 30, 2000, predates the ’550
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`patent’s earliest claimed priority date, March 1, 2001.
`
`b.
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`Dougherty overview
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`Dougherty taught a docking station that powers a laptop over the power rails
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`of a USB interface.62 Dougherty’s Figure 1, annotated below, depicts a system in
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`which a docking station (blue) 200 powers a laptop computer (red) 100 via a USB
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`cable (yellow):
`
`
`Information Disclosure Statement. See ’550 file history at 195-200. The Examiner
`did not apply the ’296 patent in any claim rejection. Instead, the Examiner rejected
`the claims on double patenting grounds and then allowed the claims in response to
`a terminal disclaimer. See Section IV.B (pp. 3-4).
`62 Geier at ¶ 44 (citing Dougherty at Abstract, 2:55-58).
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`In Figure 1, the docking station 200 connects to the laptop computer 100 via a
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`standard USB communication cable 126, 138 with four conductors.63 Serial
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`communication conductors 126 “allow communication between devices using
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`USB protocol.”64 The other two conductors carry power between the laptop
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`computer 100 and the docking station 200.65
`
`
`63 Dougherty at 4:61-63.
`64 Dougherty at 4:64-65.
`65 Dougherty at 4:65-66.
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`Dougherty’s docking station 200 can power the laptop computer 100 in two
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`scenarios. In the first scenario, the laptop computer 100 has a charged battery and
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`is in an operational state (“charged battery scenario”).66 In the second scenario, the
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`laptop computer 100 either does not have a battery (non-operational) or the battery
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`is completely discharged (“dead battery scenario”).67
`
`i.
`
`Dougherty’s “charged battery” scenario
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`Dougherty taught a four-step process by which the docking station 200
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`powers the laptop 100 when the laptop 100 has a charged battery.
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`First, the laptop 100 and docking station 200 perform a “handshaking
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`protocol” over the serial communication lines. Specifically, once a user connects
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`the laptop computer 100 and docking station 200, “th[e] handshaking protocol
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`between the laptop computer 100 and the docking station 200 reveals to software
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`running in the laptop computer 100 that the docking station 200 is capable of
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`providing power across the power rails 138 of the USB interface.”68
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`Second, “[b]ased on the handshaking between the two devices, operating
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`system software loads a driver specifically used with the docking station 200.”69
`
`The driver “turns off the laptop computer’s ability to provide five volts to the
`
`
`66 Geier at ¶ 46 (citing Dougherty at 5:26-27).
`67 Geier at ¶ 46 (citing Dougherty at 6:5-10).
`68 Dougherty at 5:44-48.
`69 Dougherty at 5:53-55.
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`power rails 138.”70 Specifically, the driver “commands the Super I/O controller
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`130 to issue a five volt shut-off command signal 148,” which “de-couples the five
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`volt input line 142 from the positive power rail 144.”71 By turning off the laptop’s
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`ability to provide power to downstream devices, “the laptop computer 100 breaks
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`with the standard USB protocol.”72
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`Third, “docking station dock logic 234 must establish that the laptop
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`computer to which it is docked is capable of receiving power.”73 Specifically,
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`“communication and control circuit 250 [within the docking station 200]
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`preferably communicates with reactive signaling circuit 150 [within the laptop
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`100] by serially communicating across the positive power rail 144.”74
`
`
`70 Dougherty at 5:55-58.
`71 Dougherty at 5:60-67.
`72 Dougherty at 5:67-6:3.
`73 Dougherty at 6:13-15.
`74 Dougherty at 6:38-41.
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`“If communication and control circuit 250 establishes positive communication with
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`reactive signaling circuit 150, the docking station 200 has made a positive
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`identification that the laptop to which it is docked is capable of receiving power
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`across the USB connection.”75 “The communication and control logic 250, after
`
`positively identifying the laptop as capable of receiving power, informs the voltage
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`ramp logic 210 [in docking station 200] across the ramp signal line 213 to ramp the
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`voltage on the positive USB power rail 244, 144 up to approximately 18 volts.”76
`
`Finally, “[v]oltage ramp logic 210 [in the docking station 200], upon
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`receiving the ramp indication from the communication and control logic 250,
`
`
`75 Dougherty at 6:32-37, 6:38-7:2.
`76 Dougherty at 7:3-7.
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`preferably ramps the voltage to 18 volts over a period of 20-50 milli-seconds.”77
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`“When the dock station 200 provides for full operation of the laptop computer 100,
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`as many as 2.5 amps of current may flow from the dock station 200 to the laptop
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`computer 100 across the USB connectors 136, 236.”78
`
`ii.
`
`Dougherty’s “dead battery” scenario
`
`In the “dead battery” scenario, the laptop 100 and docking station 200 do not
`
`perform the first two steps described above.79 They perform only the third and
`
`fourth steps.80 The laptop 100 and docking station 200 complete the third and
`
`fourth steps in the same manner as the “charged battery” scenario.81
`
`c.
`
`Analogous art
`
`For obviousness purposes, “[t]wo separate tests define the scope of
`
`analogous prior art: (1) whether the art is from the same field of endeavor,
`
`regardless of the problem addresses, and (2) if the reference is not within the field
`
`of the inventor’s endeavor, whether the reference still is reasonably pertinent to the
`
`particular problem with which the inventor is involved.” In re Bigio, 381 F.3d
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`1320, 1325 (Fed. Cir. 2004). A reference is analogous art if it meets either of these
`
`tests. See id. Dougherty is analogous art to the ’550 patent under either test.
`
`
`77 Dougherty at 7:10-13.
`78 Dougherty at 7:47-51.
`79 Geier at ¶ 53 (citing Dougherty at 6:4-7:19)
`80 Geier at ¶ 53 (citing Dougherty at 6:4-7:19).
`81 Geier at ¶ 53 (citing Dougherty at 6:4-7:19, 9:12-15).
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`First, Dougherty is from the same field of endeavor as the ’550 patent. For
`
`example, the ’550 patent states its “invention relates generally to power
`
`adapters.”82 Dougherty also relates to power adapters. For example, Dougherty
`
`taught “a laptop computer and related docking station adapted to supply power
`
`from the docking station to the laptop computer across the USB connection.”83
`
`Second, Dougherty is at least reasonably pertinent to the particular problem
`
`with which the named inventors of the ’550 patent were involved. For example, the
`
`’550 patent asserts that “the USB specification specifies a process for transferring
`
`energy across the USB called enumeration and limits the electrical current that can
`
`flow across the USB.”84 In light of this alleged problem, the ’550 patent proposes
`
`that “the mobile device can forego the enumeration process and charge negotiation
`
`process and immediately draw energy from the USB power adapter at a desired
`
`rate, for instance at 5 unit loads, i.e. 500 mA.”85 Similarly, Dougherty sought a
`
`way to power a laptop through a docking station via USB while “reducing the time
`
`and complexity to couple the laptop to the docking station.” As discussed above,
`
`Dougherty proposed a solution whereby a docking station and discharged laptop
`
`
`82 ’550 patent at 1:46.
`83 Dougherty at 2:55-58 (emphasis added).
`84 ’550 patent at 8:17-20.
`85 ’550 patent at 9:65-10:3 (reference numerals omitted).
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`Patent 8