`US 6,625,790 Bl
`{10) Patent N0.:
`
`Casebolt et a].
`(45} Date of Patent:
`*Sep. 23, 2003
`
`USIJO66 25? 90B 1
`
`(54) METHOD AND APPARATUS FOR
`DETECTING THE TYPE 011‘ INTERFACE “1‘0
`WHICHA PERIPHERAL DEVICE IS
`CONNECTED
`Inventors: Mark W. Casebolt, Seattle, WA (US);
`,
`,
`.
`_
`‘
`Lord “38‘" "M‘h‘l'bwns Rc‘lmmd’
`WAtUSI
`
`(75)
`
`(73) Assignee: Microsoft: Corporation, Redmond, WA
`(US)
`
`395.883
`Ii el al
`77‘1997
`5,644,?90 A
`.. 395.3886
`571998 [-Iulmdahl el aI.II
`5,754,890 A
`13:33;
`1:55:33: E107
`13333: R
`..
`..
`ao
`._.
`,.
`.
`
`395.3309
`[”1998 Jolley el al
`5,832,244 A
`3952828
`5:33:
`Ilashcmi CI 8' "
`gfggifi R
`7107129
`.
`.
`ones
`. _..
`,.
`E71999 Svancarek et aII. ............ 710763
`5,035,224 A
`.. 710762
`1271099 Jones et al.
`rs,0m,295 A
`
`6,460,094 Bl " 1072002 Ilanson ct al.
`TIUIS
`
`FOREIGN PATENT DOCUMENTS
`
`( *) Notice:
`
`Subject to any disclaimer, the term ofthis
`patent is extended or adjusted under 35
`U.S.C. 154th) by 0 days.
`
`LIP
`$0
`0
`
`U 3‘50 781 A2
`$0 32231386
`0 . 7717214
`
`AIM-993
`82132
`471.
`. 9
`
`This patent is subject to a terminal dis-
`claimer.
`
`(21) Appl. No; [DEW-09,683
`
`(22)
`
`Filed:
`
`0m. 1, 1999
`
`Related U'S' Application Data
`C I'
`'l'
`—‘
`—
`1
`ft
`I'vt' N .09112,I7I,1‘Id
`JIIIIIEIIIIi‘IJ‘EIfItII 1:231:51? b}? £13359:
`2
`I e 0"
`
`63
`
`)
`
`(
`
`Int. Cl.
`(51)
`(52) U.5. c1.
`
`.Gfl6F 97’45
`.................................71579,71679; 716tt;0
`716211
`7164 8 212“
`Fleld "2 Search
`2122226III7I1222I’II22’II23 108’ 262’ 269
`305’ 3063 379214215
`
`..
`References ("ted
`U.S. PA'I‘EN'I‘ DOCUMENTS
`
`4,500,933
`4,795 .469
`5,043,938
`5,473,264
`5,481,696
`5,548,782
`5,5 77,2 t 3
`5,612,634
`
`>>b>>b3¢>
`
`27"1985 Chan
`IIKI‘JSS .Ioshi el al.
`
`.
`
`3607’69
`.. 375tllfl
`
`
`
`8"391 BMW“ ----
`12:19:;
`flaigétafil'
`871996 Michael et al.
`llflggfi Avery et al.
`3t199? MacKcuna
`
`.
`
`3647000
`“33%?423
`3957835
`3957980
`326t62
`
`1421
`
`(58)
`
`(56)
`
`()IIIIILI'R PUBLICAIIIONS
`.
`. .
`.
`.
`.
`Universal Serial Bus Specification, Rev. Ll, Section 7.1.5:
`Device speed identification, pp. 1 l3 and 1 [4, Sep. 23, 1998.
`
`* cited by examiner
`
`Prinmry Examiner Vuthe Siek
`Assistant Emttttrter—Naum Levin
`.
`.
`{74) Attorney, Agent, or Ftrot—Joseph R. Kelly, Westman,
`Champlin & Kelly, PA.
`
`.. 1
`.. 1
`ABSIRAU
`{57)
`A peripheral device is connectable to a computer having one
`ofa first interface and a second interface. The first interface
`communicates with the peripheral device over a differential
`data connection having a first data conductor and a second
`data conductor. The second interface communicates with the
`peripheral device over a clock conductor and a single ended
`data connection which includes a data conductor. The
`
`peripheral device includes an interface detection component
`coupled to at least one of first and second communication
`conductors used to communicate between the peripheral
`device and the computer. The interface detection component
`is configured to detect which of the first and second inter—
`laces the peripheral dev1ce Is connected to.
`
`33 Claims, 7 Drawing Sheets
`
`WC
`
`
`INTERFACECONTROL
`SHOWN IN LOW SPEED CONFIGURATION
`
`
`
`P52 DATMJSB D-
`
`
`
`
`
`U53 SIE
`INTERFACE ENGINE
`
`P512
`COMMUNICATIONS
`
`PS2 CLOCIUUSB DI-
`
`
`
`ZTE/SAMSUNG 1010-0001
`ZTE/SAMSUNG 1010-0001
`IPR2018-00110
`|PR2018—001 10
`
`
`
`US. Patent
`
`Sep. 23, 2003
`
`Sheet 1 of 7
`
`US 6,625,790 Bl
`
`FIG. 1
`
`1
`
`REMOVABLE
`STORAGE
`29
`
`DISK
`31
`
`El
`
`—“—
`MONITOR
`47
`
`COMPUTER 20
`
`ROM 24
`BIOS 26
`
`OPERA‘I’ING
`
`SYSTEM 35
`
`APPLICATION
`PR
`RAM
`06
`S 36
`_
`
`PROGRAM
`MODULE 37
`
`PROGRAM DATA 3B
`
`46
`
`SERIAL
`PORT
`INTERFACE
`
`NETWORK
`ADAPTER 53
`
`'
`, :I
`.
`KEYBOARD MOUSE
`
`40
`
`42
`
`MEMORY 50
`
`ZTE/SAMSUNG 1010-0002
`ZTE/SAMSUNG 1010-0002
`IPR2018-00110
`|PR201 8-001 10
`
`
`
`US. Patent
`
`Sep. 23, 2003
`
`Sheet 2 of 7
`
`US 6,625,790 Bl
`
`
`
`
`COMPUTER 20
` USB
`INTERFACE 102
`
`
`
`
`
`HIGH SPEED USB
`
`
` PROCESSOR
`
`PERIPHERAL DEVICE
`
`
`
`LOW SPEED USB
`
`PERIPHERAL DEVICE
`
`PROCESSOR
`
`ZTE/SAMSUNG 1010-0003
`ZTE/SAMSUNG 1010-0003
`IPR2018-00110
`|PR201 8-001 10
`
`
`
`US. Patent
`
`Sep. 23, 2003
`
`Sheet 3 of 7
`
`US 6,625,790 Bl
`
`20
`
`\
`
`21
`
`HOST
`
`
`
` PS2INTERFACE
`
`
`OCESSOR
`
`_PR
`
`
`VCC
`
`124
`
`128
`
`FIG.2C
`
`
`PERIPERAL
`DEVICE
`
`
`
`ZTE/SAMSUNG 1010-0004
`ZTE/SAMSUNG 1010-0004
`IPR2018-00110
`|PR201 8-001 10
`
`
`
`US. Patent
`
`Sep. 23, 2003
`
`Sheet 4 of 7
`
`US 6,625,?90 B1
`
`akan—EOO
`
`ON
`
`we
`
`Nan.
`
`Kuhn—(Dd.
`
`00>
`
`
`
`.._0th00wo<ummhz_
`
`NE.
`
`ZOF<KDOEZOOQmmmw2,042—2.3075
`
`
`
`mzazmm0<mmm._.2_
`
`m_wmm:
`
`an—
`
`wZO_._.<U_ZD§EOO
`
`ZTE/SAMSUNG 1010-0005
`ZTE/SAMSUNG 1010-0005
`IPR2018-00110
`|PR2018—001 1O
`
`
`
`
`
`
`
`US. Patent
`
`Sep. 23, 2003
`
`Sheet 5 of 7
`
`US 6,625,790 Bl
`
`170
`
`COUNTING
`
`F I G . 4
`
`172
`
`TERMINAL
`COUNT
`
`CONTACT
`
`
`
`BOUNCE
`DELAY
`
`178
`
`174
`
`STATE 3 (SE1)
`DETECTED
`
`
`
`
`SE1
`
`COUNTING
`
`TERMINAL
`COUNT
`
`ANY VALID use
`COMMUNICATION
`
`180
`
`17
`
`siPSL’fiDETECTED
`
`
`
`siUSB_DETECTED
`
`DONE
`
`DONE
`
`ZTE/SAMSUNG 1010-0006
`ZTE/SAMSUNG 1010-0006
`IPR2018-00110
`|PR201 8-001 10
`
`
`
`US. Patent
`
`Sep. 23, 2003
`
`Sheet 6 of 7
`
`US 6,625,?90 B1
`
`v.9.
`
`__mmha<o<*Nan—____
`
`00>N2_IIIIIIIIIIy«2
`
`
`
`JON—.5400wo<mmmkz_
`
`
`
`
`
`zOF<mnOEZOODmmmw.30..z_Zgoxw
`
`mmhbmfioo
`
`on
`
`cor
`
`
`
`JOmkzOO13-443."—
`
`
`
`m2_02mmudeMPE
`
`mamm:
`
`wZO_._.<U_Z:_25_OU
`
`Nan—
`
`ZTE/SAMSUNG 1010-0007
`ZTE/SAMSUNG 1010-0007
`IPR2018-00110
`|PR2018—001 1O
`
`
`
`
`
`
`
`
`
`
`US. Patent
`
`Sep. 23, 2003
`
`Sheet 7 of 7
`
`US 6,625,790 Bl
`
`1 mSec
`
`FIG. 6
`
`170
`
`72
`
`
`200
`
`202
`
`TERMINAL
`COUNT
`COUNTING
`J STATE
`
`
`
`
`
`siU NCERTIAN
`USB ATTACH(D-)
`
`
`
`SE1
`DETECTED
`
`
`
`
`COUNTING
`
`TERMINAL
`COUNT
`
`
`350 OR 3
`
`
`
`
`K STATE
`
`COUNTING
`
`TOGGLE
`TEST
`FAIL
`
`204
`
`178
`
`
`
`siTOGGLE __DM
`
`ATTACHDETACH
`
`
`
`USB
`TOGGLE
`PATERERN
`1 01 01
`
`
`
`
`176
`
`DONE
`
`
`
`COUNT
`5,3,2
`
`TOGGLE
`PATTERN
`
`
`
`50332
`siUSB
`11111
`_DETECTED
`_DETECTED
`
`
`180
`
`TERMINAL
`
`ZTE/SAMSUNG 1010-0008
`ZTE/SAMSUNG 1010-0008
`IPR2018-00110
`|PR201 8-001 10
`
`
`
`US 6,625,790 Bl
`
`1
`METHOD AND APPARATUS FOR
`DETECTING THE TYPE OF INTERFACE TO
`WHICH A PERIPHERAL DEVICE IS
`CONNECTED
`
`REFERENCE. TO (IO-PENDING APPLICATION
`
`The present application is a continuation-in-part of pend-
`ing U.S. patent application Ser. No. 09"] 12,121, liled Jul. 8,
`1998 now U.S. Pat. No. 6,460,094 entitled “METHOD AND
`APPARATUS FOR DETECTING THE TYPE OF INTER—
`FACE TO WHICH A PERIPHERAL DEVICE [S CON—
`
`NECTED” and assigned to the same assignee as the present
`application, and which is hereby incorporated by reference.
`
`BACKGROUND OF THE INVENTION
`
`The present invention relates to a peripheral device con—
`nectable to a computer. More particularly, the present inven—
`tion mlates to a peripheral device configured to detect the
`type of interface to which it is connected.
`A wide variety of peripheral devices. are currently con-
`figured to be connectable to computers. Such peripheral
`devices commonly include user input devices, such as
`keyboards, point and click devices (traditionally referred to
`as a computer mouse) and other similar types of devices.
`The computer to which such devices are connected com-
`municates with the devices through one of a number of
`interfaces. Interfaces commonly used to connect
`to such
`peripheral devices include a serial
`interface (such as an
`R5232 interface) and a P52 interface. Indeed,
`the P52
`interface has long been a standard for connecting keyboards
`and mice to computers.
`However, recently, another serial interface referred to as
`a universal serial bus (USB) interface has been introduced.
`The USB interface accommodates a wide variety of com-
`puter peripherals, including, for example, keyboards and
`mice. However, a conventional computer is. typically pro-
`vided with only one interface (such as a P82 or USB
`interface)
`for communication with peripheral devices.
`Therefore, if the computer is provided with a [’52 interface,
`the keyboard or mouse must be configured to support
`communication with the computer according to a protocol
`defined by the PS2 interface. Similarly, if the computer is
`provided with the USB interface, the keyboard or mouse
`must be configured to communicate according to a protocol
`defined by the USB interface.
`In order to do this, a conventional computer peripheral
`device contains a microprocessor which runs a software
`program to carry out the functions of that particular periph—
`eral device. In the device such as a keyboard or mouse, the
`software program includes an interface between the periph-
`eral device and the host computer, through which the periph—
`eral device communicates with the host computer. Such
`communication often includes receiving commands from
`the host computer and transmitting data and status informa-
`tion to the host computer.
`As discussed above, the P52 and USB interfaces have
`different hardware and software requirements, which must
`be met by the microprocessor in the peripheral device so that
`the peripheral device can communicate with the host com-
`puter. The PS2 interface uses two conductors which include
`a separate clock conductor and a separate data conductor.
`These conductors are driven by the computer through an
`open—collector or open—drain circuit, and have a pull—up
`resistor (typically in the range of 2 k ohms to 10 k ohms)
`pulling the conductor to a rail voltage (such as VCC) inside
`
`1!]
`
`15
`
`1t]
`
`40
`
`60
`
`2
`
`the host computer. The open-collector or open-drain circuit
`(commonly a transistor) is typically implemented inside the
`microprocessor. Another pull—up resistor is required inside
`the peripheral device as well. The peripheral device com—
`municating over a PS2 interface is responsible for providing
`a clock signal on the clock conductor, regardless of the
`direction of data flow on the data conductor. The host
`
`computer pulls the clock conductor to a logic low level to
`inhibit communication from the peripheral device, and it can
`also pull the data conductor low to signal to the peripheral
`device that the host computer intends to transmit data to the
`peripheral device.
`The USB interface also uses two conductors which
`include differential data signal conductors D+ and I)—.
`In the USB interface at
`the USB port (i.e., at the host
`computer or U513 hub), the two conductors are pulled to a
`logic low level via 15 k ohm resistors. in the peripheral
`device,
`the D+ conductor is pulled to approximately 3.3
`volts via a 1.5 k ohm resistor if the peripheral device is a
`high-speed USB peripheral device. The D— conductor is
`pulled to 3.3 volts via a 1.5 k ohm resistor if the peripheral
`device is a low—speed USB peripheral device. When a
`peripheral device is attached to the USB port, the USB host
`determines whether it is a low-speed or high-speed device
`by determining which of the 0+ or D— conductors is pulled
`to the logical high level.
`Thus, it can be seen that the two interfaces have different
`hardware structures, and communicate using diflerent soft—
`ware protocols. Traditionally, separate peripheral devices
`have been provided, one being configured to communicate
`with a USB interface, and the other being configured to
`communicate with a P82 interface. This requires the manu—
`facturer of such peripheral devices to offer two different
`types of peripheral devices in order to support these two
`different interfaces.
`
`SUMMARY ()1: THE INVENTION
`
`The present invention defines a method and apparatus in
`the peripheral device such that the peripheral device can
`determine which type of interface it is connected to, and
`configure itself accordingly.
`The peripheral device is connectable to a computer having
`one of a first
`interface and a second interface. The first
`interface communicates with a peripheral device over a
`dilferential data connection having a first data conductor and
`a second data conductor. The second interface communi—
`cates with the peripheral device over a clock conductor and
`a single-ended data connection, which includes a data con-
`ductor. The peripheral device has first and second commu-
`nication conductors configured for connection to the first
`and second data conductors in the differential data connec—
`tion and to the first data conductor in the single ended data
`connection and the clock conductor. The peripheral device
`includes an interface detection component configured to
`detect which of the first and second interfaces the peripheral
`device is connected to. The peripheral device also includes
`a controller component configured to communicate between
`the peripheral device and the computer according to a
`protocol corresponding to the detected interface.
`BRIEF DESCRIPTION ()l“ THE DRAWINGS
`
`FIG. I is a block diagram of an exemplary environment
`in which an input device in accordance with the present
`invention can be used.
`
`FIGS. 2A—2C illustrate conventional high—speed and low—
`speed U513 peripheral devices and a PS2 peripheral device
`coupled to a USB interface and a PS2 interface, respectively.
`
`ZTE/SAMSUNG 1010-0009
`ZTE/SAMSUNG 1010-0009
`IPR2018-00110
`|PR201 8-001 10
`
`
`
`US 6,625,790 Bi
`
`3
`FIG. 3 illustrates a peripheral device in accordance with
`one embodiment of the present invention.
`FIG. 4 is a state diagram illustrating the operation of the
`peripheral device shown in FIG. 3.
`FIG. 5 is a block diagram of a peripheral device in
`accordance with another embodiment of the present inven-
`tion.
`
`FIG. 6 is a state diagram illustrating the operation of the
`peripheral device shown in FIG. 5.
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`The present invention includes a method and apparatus,
`implemented in a peripheral device, by which the peripheral
`device detects whether it is coupled to a P52 interface or a
`USB interface. A peripheral device, in accordance with one
`aspect of the present
`invention,
`is configured initially to
`expect a first interface and senses the state of the interface
`to configure itself appropriately.
`FIG. I and the related discussion are intended to provide
`a brief, general description of a suitable computing envi—
`ronment
`in which the invention may be implemented.
`Although not required, the invention will be described, at
`least in part, in the general context of computer-executable
`instructions, such as program modules, being executed by a
`personal computer or other computing device. Generally,
`program modules include routine programs, objects,
`com ponents, data structures, etc.
`that perform particular
`tasks or implement particular abstract data types. Moreover,
`those skilled in the art will appreciate that the invention may
`be practiced with other computer system oonfigu rations,
`including hand-held devices, multiprocessor systems,
`microprocessor-based or programmable consumer
`electronics, network PCs, minicomputers, mainframe
`computers, and the like. The invention is also applicable in
`distributed computing environments where tasks are per—
`formed by remote processing devices that are linked through
`a communications network.
`In a distributed cOmputing
`environment, program modules may be located in both local
`and remote memory storage devices.
`With reference to FIG. 1, an exemplary environment for
`the invention includes a general purpose computing device
`in the form of a conventional personal computer 20, includ-
`ing processing unit 21, a system memory 22, and a system
`bus 23 that couples various system components including
`the system memory to the processing unit 21. The system
`bus 23 may be any of several
`types of bus structures
`including a memory bus or memory controller, a peripheral
`bus, and a local bus using any of a variety of bus architec—
`tures. The system memory includes read only memory
`(ROM) 24 a random access memory (RAM) 25. A basic
`inputfoutput 26 (BIOS), containing the basic routine that
`helps to transfer information between elements within the
`personal computer 20, such as during start—up, is stored in
`ROM 24. The personal computer 20 further includes a hard
`disk drive 27 for reading from and writing to a hard disk (not
`shown), a magnetic disk drive 28 for reading from or writing
`to removable magnetic disk 29, and an optical disk drive 30
`for reading from or writing to a removable optical disk 31
`such as a CD ROM or other optical media. The hard disk
`drive 27, magnetic disk drive 28, and optical disk drive 30
`are connected to the system bus 23 by a hard disk drive
`interface 32, magnetic disk drive interface 33, and an optical
`drive interface 34, respectively. The drives and the associ—
`ated computer—readable media provide nonvolatile storage
`of computer readable instructions, data structures, program
`modules and other data for the personal computer 20.
`
`1E]
`
`15
`
`1E]
`
`40
`
`60
`
`4
`
`Although the exemplary environment described herein
`employs a hard disk, a removable magnetic disk 29 and a
`removable optical disk 31, it should be appreciated by those
`skilled in the art that other types of computer readable media
`which can store data that is accessible by a computer, such
`as magnetic cassettes, flash memory cards, digital video
`disks, Bernoulli cartridges, random access memory (RAM),
`read only memory (ROM), and the like, may also be used in
`the exemplary operating environment.
`A number of program modules may be stored on the hard
`disk, magnetic disk 29, optical disk 31, ROM 24 or RAM 25,
`including an operating system 35, one or more application
`programs 36, other program modules 37, and program data
`38. A user may enter commands and information into the
`personal computer 20 through input devices such as a
`keyboard 40 and pointing device (or mouse) 42. Other input
`devices (not shown) may include a microphone, joystick,
`game pad, satellite dish, scanner, or the like. These and other
`input devices are often connected to the processing unit 21
`through one ofa plurality of ports. For instance, keyboard 40
`and mouse 42 are connected through a PS2 or USB interface
`45. In the illustrative embodiment, interface (or port) 45 is
`coupled to the system bus 23. User input devices may also
`be connected by other interfaces, such as a sound card, a
`parallel port, or a game port. A monitor 47 or other type of
`display device is also connected to the system bus 23 via an
`interface, such as a video adapter 48. In addition to the
`monitor 47, personal computers may typically include other
`peripheral output devices such as speakers and printers {not
`shown).
`The personal computer 20 may operate in a networked
`environment using logic connections to one or more remote
`computers, such as a remote computer 49. The remote
`computer 49 may be another personal computer, a server, a
`router, a network PC, a peer device or other network node,
`and typically includes many or all of the elements described
`above relative to the personal computer 20, although only a
`memory storage device 50 has been illustrated in FIG. 1. The
`logic connections depicted in FIG. 1 include a local area
`network (LAN) 51 and a wide area network (WAN) 52. Such
`networking environments are commonplace in offices,
`enterprise-wide computer network intranets and the lntemet.
`When used in a LAN networking environment, the per-
`sonal computer 20 is connected to the local area network 51
`through a network interface or adapter 53. When used in a
`WAN networking environment, the personal computer 20
`typically includes a modem 54- or other means for establish-
`ing communications over the wide area network 52, such as
`the Internet. The modem 54, which may be internal or
`external, is connected to the system bus 23 via the serial port
`interface 46. In a network environment, program modules
`depicted relative to the personal computer 20', or portions
`thereof, may be stored in the remote memory storage
`devices. It will be appreciated that the network connections
`shown are exemplary and other means of establishing a
`communications link between the computers may be used.
`FIGS. 2A—2C illustrate conventional peripheral devices
`coupled to conventional interfaces. FIG. 2A illustrates a
`high—speed USB peripheral device 100 connected through
`USB interface 102 to CPU 21 of host computer 20. It should
`be noted that high-speed USB peripheral device 100 can be
`any suitable peripheral device, such as keyboard 40 or
`mouse 42 or another suitable peripheral device. Peripheral
`device 100 is connected to USB interface 102 and commu—
`nicates therewith over two conductors 104 and 106. Con—
`ductors 104 and 106 are connected to con'esponding con-
`ductors 108 and 110 through USB connector 112.
`
`ZTE/SAMSUNG 1010-0010
`ZTE/SAMSUNG 1010-0010
`IPR2018-00110
`|PR2018-00110
`
`
`
`US 6,625,790 Bl
`
`5
`Conductors 104 and 106 carry signals denoted D+ and I)—
`in a high—speed USB device. Signals D+ and D— are difler—
`ential digital data signals with which peripheral device 100
`communicates with computer 20.
`In a high-speed USB arrangement, conductor 104, which
`carries signal D+, is pulled to a logical high level (such as
`a +5 Volt supply or other desired supply voltage potential
`hereinafter referred to as VCC or the VCC rail) by a pull—up
`resistor 114. Resistor 114 is preferably valued such that the
`voltage potential
`to which conductor 104 is pulled is
`approximately 3.3 volts. Therefore, resistor 114 can, for
`instance, be a 7.5 k ohm resistor connected to a 5 volt VCC
`rail.
`
`ln USB interface 102 on computer 20, both conductors
`108 and 110 (which correspond to the 13+ and D— signals)
`are pulled to a logic low level by two 15 k ohm resistors 116
`and 118. When peripheral device 100 is initially attached to
`computer 20 through USB interface 102, computer 20 can
`determine that peripheral device 100 is a high—speed USB
`peripheral device because the conductor 104 cotTesponding
`to signal D+ is pulled to a logical high level, while conductor
`106 which corresponds to signal D— is not.
`FIG. 2B illustrates the connection of a low—speed USB
`peripheral device 120 to computer 20. Some items are
`similar to those shown in FIG. 2A, and are similarly num-
`bered.
`IIowever,
`rather
`than having conductor 104
`(corresponding to signal D+) pulled to a logical high level
`with resistor 114, conductor 106 (which corresponds to
`signal D—) is pulled to a logical high level with resistor 12.
`Thus, computer 20 determines that peripheral device 120 is
`a low-speed USB device.
`FIG. 2C illustrates another peripheral device 124 con-
`nected to computer 20. Peripheral device 124 is configured
`to communicate with computer 20 through a PS2 interface
`126. P82 peripheral device 124 communicates with com-
`puter 20 over a pair of conductors 104 and 106, which
`correspond to a data signal and a clock signal. Conductors
`104 and 106 are connected to transistors 131 and 133, which
`are configured as open—collector or open—drain switches
`controlled by the microprocessor in peripheral device 124.
`Conductors 104 and 106 are connected to conductors 108
`and 110 through P82 connector 128. Conductors 104 and
`106 are pulled to a logical high level at peripheral device 124
`by resistors 130 and 132 which are typically in a 2 k—lU k
`ohm range.
`In PS2 interface 126, conductors 108 and 110 are also
`pulled to a logical high level by resistors 134 and 136, which
`are also typically in a 2 k—lO k ohm range. Conductors 108
`and 110 are also coupled to ground by transistors 138 and
`140, which are typically open-drain or open-collector and
`driven by appropriate circuitry in processor 21.
`It should
`also be noted that transistors 138 and 140 can typically be
`implemented inside processor 21, or discretely.
`With the open—collector configured interface, when a
`logical
`1
`is Written to either conductor 108 or 110,
`the
`conductor is not actively driven high. Instead, it is pulled
`high, to nearly the rail voltage VCC, via the pull—up resistors
`134 and 136. In this manner, either host processor 21 or
`peripheral device 124 can drive the conductor low without
`the concern ol‘ the conductor already being actively driven
`high.
`Peripheral device 124 is responsible for providing the
`clock signal over conductors 106 and 110, to host processor
`21, regardless of the direction of data flow over conductors
`104 and 108. Ilost processor 21 can pull the conductor 110
`carrying the clock signal low by controlling transistor 140
`
`1!]
`
`‘15
`
`1E]
`
`6
`
`appropriately. This inhibits communication from peripheral
`device 124. Host processor 21 can also pull the data con—
`ductor 108 low by manipulating transistor 138 in order to
`signal peripheral device 124 that host processor 21 intends
`to transmit data.
`
`1710. 3 illustrates a peripheral device .142 in accordance
`with one embodiment of the present invention. Peripheral
`device 142 includes a communication controller 144 which,
`in turn, includes a USB SIE interface engine 146 and a PS2.
`communications controller 148. Peripheral device 142 also,
`in one illustrative embodiment, includes pull-up resistor .150
`which pulls the PS2 datanSB D— signal line to a predeter-
`mined voltage potential (such as VCC). Peripheral device
`142 also includes, in one illustrative embodiment, a cable
`with USB connector 152.
`
`It should be noted that, in FIG. 3, the PS2 data and USB
`0— lines are indicated as being carried by signal line or
`conductor 160 while the PS2 clock and USB D+ signals are
`indicated as being carried by conductor 158. Of course, the
`USB D+ signal can be carried by the same conductor as the
`PS2 data signal and the USB l)— signal can be carried by the
`same conductor as the PS2 clock signal. Also, while pull-up
`resistor 150 is shown coupled to conductor 160 (which
`corresponds to the USB D— signal), it could also be coupled
`to the conductor which corresponds to the USB D+ signal
`where the USB device is a high speed device, rather than a
`low speed device. However,
`the present discussion will
`proceed with respect to the embodiment illustrated in FIG.
`3, for the sake of simplicity.
`FIG. 3 further illustrates a P82 adapter 154 in accordance
`with one embodiment of the present invention. Adapter 154
`includes a USB connector 156 which mates with USB
`
`connector 152. Adapter 154 connects the signal lines 158
`and 160 to an output connector 162 which is suitable for
`being coupled to a connector or cable from computer 20. In
`one illustrative embodiment, connectors 152 and 156 are
`implemented as a U511 series A plug and receptacle, respec-
`tively. Connector 162 is implemented as a PS2 minidin
`connector.
`
`40
`
`Adapter 154, in the illustrative embodiment, also includes
`a pair of pull—up resistors 164 and 166. When adapter 154 is
`coupled to peripheral device 142, pull-up resistor 'l64 pulls
`the PS2 clockaSB I)+ signal line to VCC. Resistor 166
`pulls the P82 datanSB D— signal line to VCC as well. The
`pull—ups in adapter 154 eliminate the necessity for the
`microprocessor on peripheral device 142 to control these
`dynamically. This saves firmware code space and also
`reduces necessary pin count on the microprocessor by one or
`two pins. This provides a significant cost savings.
`
`Table 1 below illustrates the configuration of the two
`signals provided by both USB and P82 devices. Table 1
`illustrates the signals for a USB low speed device.
`
`60
`
`[IO
`State
`I)
`
`‘l
`
`2
`
`3
`
`’I‘ABLL-Z 1
`
`DHCLK
`L
`
`l)—,’I)A’]‘
`L
`
`I
`
`I']
`
`II
`
`H
`
`L
`
`II
`
`[ISIS
`SEO
`(Single
`lindcd 0)
`or Reset
`I, Idle
`
`K, Xmit
`Resume
`SE1
`
`PS}?
`Ilost
`Inhibit
`
`Host
`Inhibit
`Ilost Xmit
`
`Idle,
`
`ZTE/SAMSUNG 1010-0011
`ZTE/SAMSUNG 1010-0011
`IPR2018-00110
`|PR2018-00110
`
`
`
`US 6,625,790 Bl
`
`8
`
`TABLE l-continued
`
`li’O
`State
`
`DHCLK
`
`D—IDAT
`
`USE
`
`PSIZ
`
`(Single
`linded 1}
`
`Confirm
`Connect
`
`FIG. 4 is a state diagram illustrating the operation of
`peripheral device 142 shown in 1"] G. 3 and will be described
`with reference to FIG. 3 and Table 1. Communication
`controller 144 begins by starting the initialization process, as
`indicated by state 170 in FIG. 4. After power—up, commu—
`nication controller 144 waits for a time-out period (such as
`I'D—100 milliseconds). This alloWs time for contact bounce
`during mating of the connectors illustrated in FIG. 3. This is
`indicated by state 172 in FIG. 4.
`After reaching the designated time-out period, communi-
`cation controller 144- enters an indeterminate state 174. In
`the indeterminate state, controller 144 “assumes” that it is
`connected to a USB interface. In other words, controller 144
`is configured to receive a valid USB communication, or
`USB reset signaling. In the event that controller 144 is in the
`indeterminate state 174 and receives valid USB 1.0 or 1.1
`communications, controller 144 determines that
`it has
`detected a USB interface and moves to state 176. The USB
`
`1!]
`
`15
`
`1E]
`
`interface engine 146 in controller 144 then takes over
`communications beIWeen peripheral device 14-2 and com-
`puter 20.
`In the indeterminate state 174, controller 144 also peri—
`odically polls for the presence of a P82 interface by moni—
`toring the state of signal lines 158 and 160. In one specific
`embodiment, controller 144 looks for NO state 3 in Table l
`(or the SE1 condition) on signal lines 158 and 160. If such
`a condition is detected, controller 144 moves to state 178
`and determines whether the SE1 condition is detected for a
`sufficient
`time period (such as in excess of three
`milliseconds). If not, control reverts back to indeterminate
`state 174.
`if the SEl condition is maintained for the
`However,
`necessary time period, and the terminal count is reached,
`controller 144 determines that it has detected a P82 interface
`and moves to state 180. This causes USB functions to be
`terminated, and P82 communications controller 148 takes
`over communication between peripheral device 142 and
`computer 20. It will be noted that in this case, P52 adapter
`154- will be plugged into peripheral device 142 and computer
`20. Thus, pull-up resistors 164 and 166 are present on both
`signal lines 158 and 160. Therefore, as long as the host
`computer 20 is not inhibiting the device communications (by
`holding one or both of the clock and data lines low), the
`interface is immediately identified as a P82 interface, and
`communications are implemented according to the P52
`specification.
`illustrated in FIGS. 3 and 4 has a
`The embodiment
`number of advantages. No external USB pull-up resistors
`are required. Instead, resistor 150 is simply hard wired to
`VCC. This allows the elimination of pull—up resistor control,
`and reduces pin count. Similarly, since the P82 adapter 154
`provides pull—up resistors 164 and 166, no internal control is
`required for P82 pull-up resistors. This results in fewer
`components in the peripheral device controller. This also
`renders the device simpler and less costly. Similarly, this
`embodiment provides immediate conformance and response
`to USB 1.] interface signaling requirements.
`It has been found that the above embodiment works very
`well on a vast majority of host computers. However, some
`
`40
`
`60
`
`computers were discovered to hold P82 interface commu-
`nication lines in an inhibited state for extensive periods of
`time, even on power—up. This can make it difficult to detect
`and respond to initial communication sequences in a timely
`manner. Similarly, where a peripheral device 142 is “hot
`plugged” into the host computer, the inhibition of the P82
`communication by the host computer can make it difficult
`for the detection system discussed above to make an imme—
`diate detection.
`
`invention can be implemented
`the present
`Therefore,
`according to a second embodiment as well. FIG. 5 illustrates
`peripheral device 182 which is implemented in accordance
`with a second illustrative embodiment of the present inven—
`tion. A number of the items illustrated in FIG. 5 are similar
`to those found in FIG. 3, and are similarly numbered.
`However, in the embodiment illustrated in FIG. 5, peripheral
`device 182 includes communication controller 184 which
`
`not only includes USB interface engine 146 and P52 com—
`munications component 148, but also includes resistor pull-
`up control component 186. Control component 186 provides
`an output 188 to a switch 190.
`In the embodiment illustrated in FIG. 5, switch 190 is
`implemented as a bi—polar transistor 192 which is coupled
`between pull—up resistor 150 and a predetermined voltage
`potential (in this case VCC). This provides control compo-
`nent 186 with the ability to either enable pull-up resistor .150
`by connecting pull—up resistor 150 to VCC, or to disable
`pull—up resistor 150, by etfectively disconnecting pull—up
`resistor 150 from VC'C.
`
`FIG. 6 is a state diagram which better illustrates the
`operation of peripheral device 182 shown in FIG. 5. A
`number of the states are similar to those shown in FIG. 4,
`and are similarly numbered. Therefore, controller 184 first
`begins the initialization routine at state 170. Controller 184
`also waiLs, after power-up, for a predetermined time period
`in order to accommodate for contact bounce. This is indi-
`cated by state 172. After the desired delay, controller 184
`enters indeterminate state 200.
`
`Controller 184 {and specifically pull—up control compo—
`nent 186) then performs a USB attach operation by enabling
`pull-up resistor 150. In other words, control component 186
`provides an output to bi—polar transistor 192 which effec—
`tively connects pull—up resistor 150 to VCC. It will be noted
`that this does not effect PS2. operation since, where a P82
`interfac