Universal Serial Bus Specification Revision 2.0
`
`Table 6-7. USB Electrical, Mechanical, and Environmental Compliance Standards (Continued)
`
`Test Description
`
`Test Procedure
`
`Performance Requirement
`
`UL 94 V—0
`
`The manufacturer will require its
`thermoplastic resin vendor to
`supply a detailed C of C with each
`This procedure is to ensure
`resin shipment. The C of C shall
`thermoplastic resin compliance to
`clearly show the resin’s UL listing
`UL flammability standards.
`number, lot number, date code.
`etc.
`
`Flammability
`
` UL 94 V—0
`
`specified in Table 7—9 (20).
`
`
`The manufacturer will require its
`thermoplastic resin vendorto
`supply a detailed C of C with each
`resin shipment. The C of C shall
`clearly show the resin’s UL listing
`number, lot number. date code,
`etc.
`
`Impedance must be in the range
`
`Flammability
`
`This procedure is to ensure
`thermoplastic resin compliance to
`UL flammability standards.
`
`
`
`Cable Impedance
`(Only required for high-ifull-speed)
`
`The object of this test is to insure
`the signal conductors have the
`proper impedance.
`
`1. Connect the Time Domain
`Refiectometer (TD R) outputs
`to the impedancei‘delaylskew
`test fixture (Note 1). Use
`separate 50 (1 cables for the
`plus (or tme) and minus [or
`complement) outputs. Set the
`TDR head to differential TDR
`mode.
`
`Connect the Series "A" plug of
`the cable to be tested to the
`text fixture. leaving the other
`end open—circulted.
`
`Define a waveform composed
`of the difference between the
`true and complement
`waveforms, to allow
`measurement of differential
`impedance.
`
`Measure the minimum and
`maximum impedances found
`between the connector and the
`open circuited far end ofthe
`cable.
`
`Ill]
`
`ZTE/SAMSUNG 1008-0138
`ZTE/SAMSUNG 1008-0138
`IPR2018-00110
`|PR201 8-001 10
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`Table 6-7. USB Electrical, Mechanical, and Environmental Compliance Standards (Continued)
`
`Test Description
`
`Test Procedure
`
`Performance Requirement
`
`The object ofthis test is to insure
`that adequate signal strength is
`presented to the receiver to
`maintain a low error rate.
`
`Refer to Section 7.1.1? for
`frequency range and allowable
`attenuation.
`
`1. Connect the Network Analyzer
`output port [port 1 ) to the input
`connector on the attenuation
`test fixture [Note 2).
`
`
`
`
`
`Signal Pair Attenuation
`(Only required for high-ifuli-speed)
`
`Connect the Series “A" piug of
`the cable to be tested to the
`
`test fixture, leaving the other
`end open~circuited.
`
`Calibrate the network analyzer
`and fixture using the
`appropriate calibration
`standards over the desired
`
`frequency range.
`
`Foilowthe method listed in
`Hewlett Packard Application
`Note 380—2 to measure the
`open-ended response of the
`cable.
`
`Short circuit the Series “El“ end
`(or bare leads end. ifa captive
`cable) and measure the short»
`circuit response.
`
`Using the software in H-P App.
`Note 380-2 or equivalent,
`calculate the cable attenuation
`accounting for resonance
`effects in the cable as needed.
`
`Ill
`
`ZTE/SAMSUNG 1008-0139
`ZTE/SAMSUNG 1008-0139
`IPR2018-00110
`|PR201 8-001 10
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`Table 6-7. [[83 Electrical, Mechanical, and Environmental Compliance Standards (Continued)
`
`Test Description
`
`Test Procedure
`
`Performance Requirement
`
`Hig h-lfull—s peed.
`
`See Section 7.1.1.1,
`Section 7.1.4, Section 7.1.16, and
`Table 7-9 (TFSCBL).
`
`Low—speed.
`
`See Section 7.1.1.2,
`Section 7.1.16, and Table 7-9
`(TLSCBL).
`
`
`
`
`
`Propagation Delay
`
`The purpose of the test is to verify
`the end to end propagation of the
`cable.
`
`1. Connect one output of the
`TDR sampling head to the 0+
`and D- inputs of the
`impedanceldelayl'skew test
`fixture (Note 1). Use one 50 a
`cable for each signal and set
`the TDR head to differential
`TDR mode.
`
`Connect the cable to be tested
`to the test fixture.
`If
`detachable, plug both
`connectors in to the matching
`fixture connectors.
`If captive,
`plug the series "A" plug into
`the matching fixture connector
`and solder the stripped leads
`on the other end to the test
`fixture.
`
`Measure the propagation delay
`of the test fixture by
`connecting a short piece of
`wire across the fixture from
`input to output and recording
`the delay.
`
`Remove the short piece ofwire
`and remeasure the
`propagation delay. Subtract
`from it the deiay of the test
`fixture measured in the
`previous step.
`
`112
`
`ZTE/SAMSUNG 1008-0140
`ZTE/SAMSUNG 1008-0140
`IPR2018-00110
`|PR201 8-001 10
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`Table 6-7. USB Electrical, Mechanical, and Environmental Compliance Standards (Continued)
`
`Test Description
`
`Test Procedure
`
`Performance Requirement
`
`This test insures that the signal on
`both the 0+ and 0- lines arrive at
`the receiver at the same time.
`
`Propagation skew must meetthe
`requirements as listed in
`Section 7.1.3.
`
`Propagation Delay SKEW
`
`Connect the TDR to the fixture
`with test sample cable, as in
`the previous section.
`
`. Measure the difference in
`delay for the two conductors in
`the test cabte. Use the TDR
`cursors to find the open-
`circuited end of each
`
`conductor (where the
`impedance goes infinite) and
`subtract the time difference
`between the two values.
`
`
`
`See Section 7.1.1.2 and Table 7-?
`(CLINUA).
`
`Capacitive Load
`
`Only required for low-speed
`
`The purpose of this test is to insure
`the distributed inter-wire
`capacitance is less than the
`lumped capacitance specified by
`the townspeed transmit driver.
`
`1. Connect the one lead of the
`Impedance Analyzer to the [H
`pin on the
`impedancei'delayi'skew fixtu re
`N t
`1
`d th
`th
`t dt
`Ehgg- 3:."
`e0 er ea
`0
`
`Connect the series "A" plug to
`the fixture, with the series ”B"
`end leads open-circuited.
`
`Set the Impedance Analyzer to
`a frequency of 100 kHz. to
`measure the capacitance.
`
`
`
`Note1:
`
`Impedance. propagation delay, and skew test fixture
`This fixture will be used with the TDR for measuring the time domain performance of the cable under test. The
`fixture impedance should be matched to the equipment. typically 50 £1. Coaxial connectors should be provided
`on the fixture for connection from the TDR.
`
`Note 2: Attenuation text fixture
`This fixture provides a means of connection from the network analyzer to the Series "A" plug. Since USB
`signals are differential in nature and operate over balanced cable. a transionner or balun (North Hills NH13734
`or equivalent) is ideally used. The transformer converts the unbalanced (also known as single-ended) signal
`from the signal generator which is typically a 50 [2 output to the balanced {also known as differential) and likely
`different impedance loaded presented by the cable. A second transformer or balun should be used on the other
`end of the cable under test to convert the signal back to unbalanced form of the correct impedance to match the
`network analyzer.
`
`113
`
`ZTE/SAMSUNG 1008-0141
`ZTE/SAMSUNG 1008—01 41
`IPR2018-00110
`|PR2018—001 1O
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`6.7.1 Applicable Documents
`
`American National Standardelectronic Industries Association
`
`ANSUEIA-364-C (12i’94)
`
`Electrical Connector!Socket Test Procedures
`Including Environmental Classifications
`
`American Standard Test Materials
`
`ASTM-D-4565
`
`Physical and Environmental Performance Properties
`of Insulation and Jacket for Telecommunication
`
`ASTM-D-4566
`
`Wire and Cable, Test Standard Method
`
`Electrical Performance Properties of Insulation and
`Jacket for Telecommunication Wire and Cable, Test
`Standard Method
`
`Underwriters’ Laboratory, Inc.
`
`UL STD-94
`
`Test for Flammability of Plastic materials for Parts
`in Devices and Appliances
`
`UL Subject-444
`
`Communication Cables
`
`6.8 USB Grounding
`
`The shield must be terminated to the connector plug for completed assemblies. The shield and chassis are
`bonded together. The user selected grounding scheme for USB devices, and cables must be consistent with
`accepted industry practices and regulatory agency standards for safety and EMUESDIRFI.
`
`6.9 PCB Reference Drawings
`
`The drawings in Figure 6-12, Figure 6-13, and Figure 6-14 describe typical receptacle PCB interfaces.
`These drawings are included for informational purposes only.
`
`114
`
`ZTE/SAMSUNG 1008-0142
`ZTE/SAMSUNG 1008-0142
`IPR2018-00110
`|PR201 8-001 10
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`
`
`
`
`
`
`.J' _ \..
`
`3.3 REF i
`7.6 REF
`R 0.64 i 0.13 Typical (2)
`
`J
`
`6.00 1 0.10—ln—bl
`
`1,34 1 0.05
`
`5.12:0.10
`
`: Printed Circuit Board (PCB) Layout-
`
`Thermoplastic insulator UL 94—VIJ
`
`2_50 +Dflz50 + n05
`
`1.0t0.05 Wide - Selectively Plated Contact (4}
`
`70° + °1°
`2on .t 0.10
`
`$4}63—
`
`2?1:D1D
`
`.
`
`1314:0110 fipi
`o 2 30 + (110(2)
`
`;
`.
`
`I
`
`NOTES:
`
`1. Critical Dimensions are TOLERANCED
`andM be deviated.
`2. Dimensions that are labeled REF are
`typical dimensions and may vary from
`manufacturer to manufacturer.
`
`3. All dimensions are in millimeters (mm) unless
`othemrise noted.
`
`Figure 6—12. Single Pin-type Series "A" Receptacle
`
`115
`
`ZTE/SAMSUNG 1008-0143
`ZTE/SAMSUNG 1008-0143
`IPR2018-00110
`|PR2018—001 1O
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`
`
`
`
`15,60 REF
`
`14.70 :t 0.10
`
`i 3.0? 1 0.1012)
`.'
`2.001010
`2.50 1 0.10
`
`7.00 1 0.10
`25010.10
`
`'
`_.
`252 + 0.05$_..
`19—e-e~~e---9‘?-
`I“"i‘"' _@-_e_._e_.. 50010.10
`
`10.23 1 0.20
`
`121 0.92 1 0.10 (a)
`
`121 2.3 1 0.10 (4}
`
`m Connector Front Edge —
`
`Primed Circuit Board (PCB) Layout
`
`j
`
`Reference Drawing Only
`
`Dual Pin-Type
`
`Series "A" Receptacle
`5.25 WE
`WWG mass
`m
`some: m
`
`_I-—I;
`
`4
`
`3 F
`
`I I | | || l I| I I | I| | |
`
`‘1110 REF -
`
`NOTES:
`
`1. Critical Dimensions are TOLERANCED
`and should not be deviated.
`
`. Dimensions that are labeled REF are
`
`typical dimensions and may vary from
`manufacturer to manufacturer.
`
`. All dimensions are in millimeters (mm)
`
`misssmsssss miss.
`
`igure 6—13. Dual Pin-type Series “A" Receptacle
`
`116
`
`ZTE/SAMSUNG 1008-0144
`ZTE/SAMSUNG 1008-0144
`IPR2018-00110
`|PR201 8-001 10
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
` 3
`
`7
`
`5
`
`L 5 “nu—l
`
`1.0 2 11.05 Wide ~ aeremively PIaIecI ContacIs (4)
`
`Thermapla stic Insulator UL 94-VO
`
`naium
`
`11.50 REF
`
`
`
`
`asoREF
`
`301+010
`200+01CI
`' —‘
`
`2?1+u10
`
`431+u1u
`
`.1_
`
`12.00 REF
`
`1U30 REngl
`16 00 REF
`
`E
`
`a
`
`
`
`El 1192 1 0.1 (4)
`
`252.30: 0.1 [2}
`
`Printed Circuit Board (1303} Layout
`
`REference DraWing only
`_
`_
`Smgle PIn-Type
`II "
`
`sane-‘5 B Receptade
`2193
`”IA
`A
`C
`SIZE |
`DATE
`mamas NUMBER
`REV
`SCALE: NIA
`
` '
`
`NOTES.
`
`1. Critical Dimensions are TOLERANCED
`and should not be deviated
`
`2. DImenSIonsthatare labeled REF are
`typical dimensions and may vary from
`manufacturer to manufacturer.
`
`3. All dimensions are in millimeters (mm)
`UI'IIBSS othenmse noted
`
`SHEET ‘I Of 1 -— 5
`
`s
`
`.1
`
`Figure 6-14. Single Pin-type Series "B" Receptacle
`
`11'.1r
`
`ZTE/SAMSUNG 1008-0145
`ZTE/SAMSUNG 1008-0145
`IPR2018-00110
`|PR201 8-001 10
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`118
`
`ZTE/SAMSUNG 1008-0146
`ZTE/SAMSUNG 1008-0146
`IPR2018-00110
`|PR201 8-001 10
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`Chapter 7
`Electrical
`
`It contains signaling, power distribution, and
`This chapter describes the electrical specification for the USB.
`physical layer Specifications. This specification does not address regulatory compliance.
`It is the responsibility
`of product designers to make sure that their designs comply with all applicable regulatory requirements.
`
`The USB 2.0 specification requires hubs to support high-speed mode. USB 2.0 devices are not required to
`support high-speed mode. A high-speed capable upstream facing transceiver must not support low-speed
`signaling mode. A USB 2.0 downstream facing transceiver must support high-speed, full-speed, and low-speed
`modes.
`
`To assure reliable operation at hi gh-speed data rates, this specification requires the use of cables that conform to
`all current cable specifications.
`
`In each of
`In this chapter, there are numerous references to strings ofJ’s and K’s, or to strings of 1’s and 0’s.
`these instances, the leftmost symbol is transmittedfreceived first, and the rightmOst is transmittedi’received last.
`
`7.1 Signaling
`
`The signaling specification for the USB is described in the following subsections.
`
`Overview of High-speed Signaling
`
`A hi gh-speed USB connection is made through a shielded, twisted pair cable that conforms to all current USB
`cable specifications.
`
`119
`
`ZTE/SAMSUNG 1008-0147
`ZTE/SAMSUNG 1008-0147
`IPR2018-00110
`|PR201 8-001 10
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`+3.3!
`
`Rpu_Enab!e b—————_____..__....__I
`HS_Current_Souree_Enahle
`HS_Drive_Enahle
`HS_Dala_Driver_lnput
`
`kfi
`High Speed Cunent Driver
`
`l
`
`LNFS Drivel
`
`Rs
`
`I
`
`Note: The Rpu pulMIp resislnl. and
`the cicuilnr mulled In enable and
`dlBIlIIR it. are only rewlreu In
`“Ill-rum fae'flg UIIIICIMI‘S
`
`Rpu
`
`Data+
`
`Data—
`
`LSIFS_DaIa_Dnver_Input
`
`fissert_5lngle_E nded_Zero
`F5_Edge_Mode_‘Sel
`LSIFS_Drlver_Outpul_Enable
`
`Minn“w i
`
`Am" sen
`
`-
`
`“3
`
`|
`Ha Dillulatltinl Data Rlcumr
`Transmission Emlopl Dale
`
`otol
`
`n
`
`I—
`
`LSIF5_Dil‘ferenlial_Receiver_0ulput ‘_I
`
`Lsrrs Dill-rant»! out. Receiver
`
`'
`
`Disconnedian Envelope
`
`Detaclnl
`
`'
`
`SE_Data+_Receiver_0utput
`.
`SE_Data-_Recewer_0ulpul
`
`‘
`
`‘
`Single Ended Rm
`
`Mate: The Rad resistan to ground
`are only required in downsbealn
`lath: “Inseam"
`
`de
`
`de
`
`Figure 7-]. Example High-speed Capable Transceiver Circuit
`
`Figure 7~l depicts an example implementation which largely utilizes USB 1.1 transceiver elements and adds the
`new elements required for hi gh-speed operation.
`
`High—speed operation supports signaling at 480 Mbr’s. To achieve reliable signaling at this rate, the cable is
`terminated at each end with a resistance from each wire to ground. The value of this resistance (on each wire) is
`nominally set to ”2 the specified differential impedance of the cable, or 45 .9. This presents a differential
`termination of 90 (1.
`
`For a link operating in high-speed mode, the high-speed idle state occurs when the transceivers at both ends of
`the cable present high-speed terminations to ground, and when neither transeeiver drives signaling current into
`the D+ or D- lines. This state is achieved by using the low-lfull-speed driver to assert a single ended zero, and to
`closely control the combined total of the intrinsic driver output impedance and the Rs resistance (to 45 Q,
`nominal). The recommended practice is to make the intrinsic driver impedance as low as possible, and to let Rs
`contribute as much of the 45 Q as possible. This will generally lead to the best termination accuracy with the
`least parasitic loading.
`
`In order to transmit in high-speed mode, a transceiver activates an internal current source which is derived from
`its positive supply voltage and directs this current into one of the two data lines via a high speed current steering
`switch.
`In this way, the transeeiver generates the high-speed J or K state on the cable.
`
`The dynamic switching of this current into the D+ or D- line follows the same NRZI data encoding scheme used
`in low-speed or full-speed operation and also in the bit stuffing behavior. To signal a J, the current is directed
`into the D+ line, and to signal a K, the current is directed into the D- line. The SYNC field and the BOP
`delimiters have been modified for high-speed mode.
`
`120
`
`ZTE/SAMSUNG 1008-0148
`ZTE/SAMSUNG 1008-0148
`IPR2018-00110
`IPR201 8-001 10
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`The magnitude of the current source and the value of the termination resistors are controlled to specified
`tolerances, and together they determine the actual voltage drive levels. The DC resistance from D+ or D- to the
`device ground is required to be 45 (2 $1096 when measured without a load, and the differential output voltage
`measured across the lines (in either the J or K state) must be $400 mV i10% when D+ and D- are terminated
`with precision 45 Q resistors to ground.
`
`The differential voltage developed across the lines is used for three purposes:
`
`U
`
`0
`
`I
`
`A differential receiver at the receiving end of the cable receives the differential data signal.
`
`A differential enve10pe detector at the receiving end of the cable determines when the link is in the Squelch
`state. A receiver uses squelch detection as indication that the signal at its connector is not valid.
`
`In the case of a downstream facing hub transceiver, a differential envel0pe detector monitors whether the
`signal at its connector is in the high-speed state. A dovirnstream facing transceiver operating in high—speed
`mode is required to test for this state at a particular point in time when it is transmitting a SOF packet, as
`described in Section 7.1.7.3. This is used to detect device disconnection.
`In the absence ofthe far end
`
`terminations, the differential voltage will nominally double (as compared to when a high-speed device is
`present) when a high-speed J or K are continuously driven for a period exceeding the round-trip delay for
`the cable and board~traces between the two transceivers.
`
`USB 2.0 requires that a dowustream facing transceiver must be able to operate in low-speed, full-speed, and
`high-speed signaling modes. An upstream facing high-speed capable transceiver must not operate in low~speed
`signaling mode, but must be able to operate in full~speed signaling mode. Therefore, a 1.5 kQ pull-up on the D-
`line is not allowed for a high—speed capable device, since a high-speed capable transceiver must never signal
`low-speed operation to the hub port to which it is attached.
`
`Table 7-1 describes the required functional elements of a hi gh-speed capable transceiver, using the diagram
`shown in Figure 7-] as an example.
`
`121
`
`ZTE/SAMSUNG 1008-0149
`ZTE/SAMSUNG 1008-0149
`IPR2018-00110
`|PR201 8-001 10
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`
`
`Table 7-]. Description of Functional Elements in the Example Shown in Figure 7-1
`Description
`
` The low-lfull-speed driver is used for low-speed and full-speed transmission.
`Low-ifulI-speed Driver
`
`
`It
`is required to meet all specifications called out in USB 1.1 for tow-speed and full~
`
`speed operation. with one exception. The exception is that in high-speed
`
`
`capable transceivers, the impedance of each output. including the contribution of
`
`
`Rs, must be 45 Q 110%.
`
`
`
`
`The line terminations for high-speed operation are created by having this driver
`
`(This is equivalent to driving SEO in the full~speed or
`drive D+ and D- to ground.
`
`
`lowwspeed mode.) Because of the output impedance requirement described
`above. this provides a well-controlled high-speed termination on each data line
`
`to ground. This is equivalent to a 90 fl differential termination.
`
`
` Low-ifuII-speed Differential
`
`
`The low-ifull-speed differential receiver is used for receiving low-speed and full-
`Receiver
`speed data.
`
`
`
`
`The single ended receivers are used for low-speed and full-speed signaling.
`Single Ended Receivers
`
`
`The high-speed current driver is used for high—speed data transmission. A
`High-speed Current Driver
`current source derived from a positive supply is switched into either the D+ or D-
`
`
`Iines to signal a J or a K, respectively. The nominal value of the current source
`
`is 17.78 mA. When this current is applied to a data line with a 45 Q. termination
`
`to ground at each end. the nominal high level voltage (VHsOH) is +400 mV. The
`
`nominal differential high—speed voltage (D+ - D-) is thus 400 mV for a J and
`
`4100 mV for a K.
`
`
`
`The current source must comply with the Transmit Eye Pattern Templates
`specified in Section 7.1.2.2, starting with the first symbol of a packet. One
`
`means of achieving this is to leave the current source on continuously when a
`
`transceiver is operating in high—speed mode.
`If this approach is used, the
`
`current can be directed to the port ground when the transceiver is not
`
`transmitting (the example design in Figure 7—1 shows a control line called
`
`HS_Current_Source_Enable to turn the current on. and another called
`
`HS_Drive_Enable to direct the current into the data lines.) The penalty of this
`
`approach is the 17.78 mA of standing current for every such enabled transceiver
`
`in the system.
`
`
`
`
`The preferred design is to fully turn the current source off when the transceiver
`is not transmitting.
`
`
`
`
`High-speed Differential Data
`The high-speed differential data receiver is used to receive high—speed data.
`It
`Receiver
`is left to transceiver designers to choose between incorporating separate high—
`
`
`
`
`speed and low-ifull-speed receivers. as shown in Figure 74, or combining both
`
`
`
`functions into a single receiver.
`
`
`
`
`122
`
`ZTE/SAMSUNG 1008-0150
`ZTE/SAMSUNG 1008-0150
`IPR2018-00110
`|PR201 8-001 10
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`Table 7-]. Description of Functional Elements in the Example Shown in Figure 7-! (Continued)
`
`Transmission Envelope
`Detector
`
`Disconnection Envelope
`Detector
`
`Pull—up Resistor (RPu)
`
`
`
`This envelope detector is used to indicate that data is invalid when the
`amplitude of the differential signal at a receiver's inputs falls below the squelch
`threshold (VHssc-J.
`it must indicate Squelch when the signal drops below
`100 mV differential amplitude, and it must indicate that the line is not in the
`Squelch state when the signal exceeds 150 mV differential amplitude. The
`response time of the detector must be fast enough to allow a receiver to detect
`data transmission, to achieve DLL lock, and to detect the end of the SYNC field
`within 12 bit times, the minimum number of SYNC bits that a receiveris
`guaranteed to see. This envelope detector must incorporate a filtering
`mechanism that prevents indication of squelch during the longest differential
`data transitions allowed by the receiver eye pattern specifications.
`
`This envelope detector is required in downstream facing ports to detect the high—
`speed Disconnect state on the line (VHsosc). Disconnection must be indicated
`when the amplitude of the differential signal at the downstream facing driver's
`oonnector 2625 mV, and it must not be indicated when the signal amplitude is
`$525 mV. The output of this detector is sampled at a specific time during the
`transmission of the high-speed SOF EOP‘ as described in Section 7.1.7.3.
`
`This resistor is required only in upstream facing transceivers and is used to
`indicate signaling speed capability. A high-speed capable device is required to
`initially attach as a full-speed device and must transition to high-speed as
`described in this specification. Once operating in high-speed, the 1.5 kfl
`resistor must be electrically removed from the circuit.
`In Figure 7-1, a control
`line called RPu_EnabIe is indicated for this purpose. The preferred embodiment
`is to attach matched switching devices to both the D+ and D— lines so as to Keep
`the lines' parasitic loading balanced. even though a pull-up resistor must never
`be used on the D- line of an upstream facing high-speed capable transceiver.
`When connected, this pull~up must meet all the specifications called out for full—
`speed Operation.
`
`Pull-down Resistors (RPo)
`
`These resistors are required only in downstream facing transceivers and must
`conform to the same specifications called out for low-speed and full-speed
`operation.
`
`7.1.1 USB Driver Characteristics
`
`The USB uses a differential output driver to drive the USB data signal onto the USB cable.
`
`For low-speed and full-speed operation, the static output swing of the driver in its low state must be below VOL
`(max) of 0.3 V with a 1.5 kQ load to 3.6 V, and in its high state must be above the VOH (min) of 2.8 V with a
`15 k9 load to ground as listed in Table 7-7. Full-speed drivers have more stringent requirements, as described
`in Section 7.1.1.1. The output swings between the differential high and low state must be well-balanced to
`minimize signal skew. Slew rate control on the driver is required to minimize the radiated noise and cross talk.
`The driver’s outputs must support three-state Operation to achieve bi-directional half-duplex operation.
`
`Low-speed and fiJlI-speed USB drivers must never “intentionally” generate an SE1 on the bus. SE] is a state in
`which both the D+ and D- lines are at a voltage above VDSEI (min), which is 0.8 V.
`
`High-speed drivers use substantially different signaling levels, as described in Section 7.1.1.3.
`
`USB ports must be capable of withstanding continuous exposure to the waveforms shOWn in Figure 7-2 while in
`any drive state. These waveforms are applied directly into each USB data pin from a voltage source with an
`
`123
`
`ZTE/SAMSUNG 1008-0151
`ZTE/SAMSUNG 1008-0151
`IPR2018-00110
`lPR2018-001 1O
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`output impedance of 39 Q. The open-circuit voltage of the source shown in Figure 7-2 is based on the expected
`worst-case overshoot and undershoot.
`
`AC Stress Evaluation Setu
`
`D+ or 0- pin
`on USB connector
`nearest device
`
`
`
`Rsnc = 390. $290
`The signal produced by the voltage generator may be
`distorted Men observed at the data pln due to Input
`protection devices possibly incorporated In the USB
`device.
`
`
`
`
`
`Figure 7-2. Maximum Input Waveforms for USB Signaling
`
`Short Circuit Withstand
`
`A USB transceiver is required to withstand a continuous short circuit of D+ anda’or D- to VBUS, GND, other data
`line, or the cable shield at the connector, for a minimum of24 hours without degradation. It is recommended
`that transceivers be designed so as to withstand such short circuits indefinitely. The device must not be damaged
`under this short circuit condition when transmitting 50% ofthe time and receiving 50% ofthe time (in all
`supported speeds). The transmit phase consists of a symmetrical signal that toggles between drive high and
`drive low. This requirement must be met for max value of VBUS (5.25 V).
`
`It is recommended that these AC and short circuit stresses be used as qualification criteria against which the
`long-term reliability of each device is evaluated.
`
`7.1.1.1 Full-speed (12 Mbi's) Driver Characteristics
`
`A full-speed USB connection is made through a shielded, twisted pair cable with a differential characteristic
`impedance (Zn) of 90 .Q. i15%, a common mode impedance (Zeta) of30 Q i30%, and a maximum one-way
`delay {TFSCBL) of 26 ns. When the full-speed driver is not part of a high-speed capable transceiver, the
`impedance of each of the drivers (Zoav) must be between 23 Q and 44 Q, i.e., within the gray area in Figure 74.
`When the full-speed driver is part of a high-speed capable transceiver, the impedance of each of the drivers
`(ZHson) must be between 40.5 Q and 49.5 (2, i.e., within the gray area in Figure 7-5.
`
`For a CMOS implementation, the driver impedance will typically be realized by a CMOS driver with an
`impedance significantly less than this resistance with a discrete series resistor making up the balance as shown in
`Figure 7-3. The series resistor RS is included in the buffer impedance requirement shown in Figure 7-4 and
`Figure 7-5.
`In the rest of the chapter, references to the buffer assume a buffer with the series impedance unless
`stated otherwise.
`
`124
`
`ZTE/SAMSUNG 1008-0152
`ZTE/SAMSUNG 1008-0152
`IPR2018-00110
`|PR201 8-001 10
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`Buffer Output lmped. (ZBUF)
`
`D+ (ZBQ to 449 Equiv. Imped.)
`
`(239 to 449 Equiv. lmped.)
`
`D-
`
`Figure 7-3. Example Full-speed CMOS Driver Circuit (non High-speed capable)
`
`Full—speed Buffers in Transceivers Which are Not High-speed Capable
`
`The buffer impedance must be measured for driving high as well as driving low. Figure 7—4 shows the
`composite WI characteristics for the fullnspeed drivers with included series damping resistor (R3). The
`characteristics are normalized to the steady-state, unloaded output swing of the driver. The normalized driver
`characteristics are found by dividing the measured voltages and currents by the actual swing of the driver under
`test. The normalized Wl curve for the driver must fall entirely inside the shaded region. The WI region is
`bounded by the minimum driver impedance above and the maximum driver impedance below. The minimum
`drive region is intersected by a constant current region of |6. l VOl-II mA when driving low and -16.1VOH| mA
`when driving high.
`In the special case ofa full-speed driver which is driving low, and which is part ofa high-
`speed capable transceiver, the low drive region is intersected by a constant current region of 22.0 mA. This is
`the minimum current drive level necessary to ensure that the waveform at the receiver crosses the opposite
`single-ended switching level on the first reflection.
`
`When testing, the current into or out ofthe device need not exceed i103] *VOH mA and the voltage applied to
`DMD» need not exceed 0.3*VOH for the drive low case and need not drop below 0.7*VOH for the drive high
`02158.
`
`Full-speed Buffers in High-speed Capable Transceivers
`
`Figure 7-5 shows the WI characteristics for a Full-speed buffer which is part of a high-speed capable
`transceiver. The output impedance, Znsonv (including the contribution of R5), is required to be between 40.5 $1
`and 49.5 $2. Additionally, the output voltage must be within leV of ground when no current is flowing in or
`out of the pin (VHsTERM).
`
`125
`
`ZTE/SAMSUNG 1008-0153
`ZTE/SAMSUNG 1008—0153
`IPR2018-00110
`|PR2018-00110
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`IOUT
`("'A’
`
`10.71 a IVOHI
`
`Slope = 11289
`n
`n \
`TESt LII-"It
`
`I K
`
`:
`
`:
`
` drive low
`("1N
`
`6.1 * IVOHI
`
`2.32
`o
`
`Slope = 1I44£2
`
`0
`
`0.3V
`
`o.27*VoH
`
`o.3*vcH
`
`VouT (Volts)
`
`V0”
`
`0
`
`s.1*|v0H|
`
`drive high
`
`SI
`
`“449
`ope = \
`
`.1031 * |VOH|
`
`TESt Limit
`
`slope = 11289
`
`IOUT
`
`o
`
`VOUT (Volts)
`
`o.7*voH 0.73*V0H
`
`VOH
`
`Figure 7-4. Full-speed Buffer VII Characteristics
`
`126
`
`ZTE/SAMSUNG 1008-0154
`ZTE/SAMSUNG 1008-0154
`IPR2018-00110
`|PR201 8-001 10
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`drive low
`
`lOUT
`(mA)
`
`Slope = 1140.59
`\A
`
`10.71 * IVOHI
`
`Test Limit
`
`22.0
`
`I
`(mA)
`
`\k:\
`{:
`'
`
`Slope=1l49.5§l
`
`0
`
`1.09V 0.434“V
`
`DH VOUT (VO'tSi
`
`drive high
`
`Slope = 1l49.5£}\
`
`-5.1*|voH|
`
`_1 of” . [VDHI
`
`Test Limit
`
`IOUT
`
`‘1
`
`VOUT (Volts)
`
`0.566*VDH 0.698*VOH
`
`VDH
`
`Figure 7-5. F nil-speed Buffer VII Characteristics for High-speed Capable Transceiver
`
`127r
`
`ZTE/SAMSUNG 1008-0155
`ZTE/SAMSUNG 1008-0155
`IPR2018-00110
`|PR201 8-001 10
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`Figure 7-6 shows the full-Speed driver signal waveforms.
`
` Driver
`
`
`Signal pins pass
`input spec Bevel:
`afier one cable
`delay
`
`\'
`
`Signal Pins
`
`Vss
`
`Vm (min)
`
`Receiver
`Signal Pins
`
`VIL {max}
`
`Vss
`
`Figure 7-6. Full-speed Signal Waveforms
`
`7.1.1.2 Low-speed (1.5 Mbis) Driver Characteristics
`
`A low-speed device must have a captive cable with the Series A connector on the plug end. The combination of
`the cable and the device must have a single-ended capacitance of no less than 200 [JP and no more than 450 pF'
`on the D+ or D- lines.
`
`The propagation delay (TLSCBL) of a low-speed cable must be less than 18 ns. This is to ensure that the
`reflection occurs during the first halfofthe signal riseffall, which allows the cable to be approximated by a
`lumped capacitance.
`
`Figure 7-7 shows the low-speed driver signal waveforms.
`
`VIH (min)
`Driver
`.
`.
`Signal Pins
`
`VIL (max) Vss
`
`._
`
`Signal pins
`pass output
`spec Ievets
`with mlnlrnal
`reflections and
`ringing
`
`Figure 7-7. Low-speed Driver Signal Waveforms
`
`128
`
`ZTE/SAMSUNG 1008-0156
`ZTE/SAMSUNG 1008-0156
`IPR2018-00110
`|PR201 8-001 10
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`7.1.1.3 High-speed (480 Mbis) Driver Characteristics
`
`A hi gh-speed USB connection is made through a shielded, twisted pair cable with a differential characteristic
`impedance (20} of 90 Q i15%, a common mode impedance (Zora) of 30 Q 130%, and a maximum one-way
`delay of 26 ns {Trscac}. The D+ and D- circuit board traces which run between a transceiver and its associated
`connector should also have a nominal differential impedance of 90 Q, and together they may add an additional
`4 ns ofdelay between the transceivers. (See Section 7.1.6 for details on impedance specifications of boards and
`transceivers.) The differential output impedance of a hi gh-speed capable driver is required to be 90 Q 140%.
`When either the D+ or D— lines are driven high, VHSCIH (the hi gh-speed mode high—level output voltage driven on
`a data line with a precision 45 (2 load to GND) must be 400 mV 110%. On a line which is not driven, either
`because the transceiver is not transmitting or because the opposite line is being driven high, Vnsm. [the high-
`speed mode low-level output voltage driven on a data line with a 45 Q load to GND) must be 0 V i 10 mV.
`
`Note: Unless indicated otherwise, all voltage measurements are to be made with respect to the local circuit
`ground.
`
`Note: This specification requires that a high-speed capable transceiver operating in full—speed or low-speed
`mode must have a driver impedance (ZHSDRV) of 45 Q i10%.
`it is recommended that the driver impedances be
`matched to within 5 9 within a transceiver. For upstream facing transceivers which do not support high-speed
`mode, the driver