IN THE UNITED STATES DISTRICT COURT
`FOR THE EASTERN DISTRICT OF TEXAS
`MARSHALL DIVISION
`
`
`ALACRITECH, INC.,
`
`
`Plaintiff,
`
`v.
`
`
`CENTURYLINK, INC., et al.,
`
`WISTRON CORP., et al.
`
`DELL, INC.
`
`
`
`
`
`
`
`
`
`Case No. 2:16-cv-693-RWS-RSP
` (LEAD CASE)
`
`
`Case No. 2:16-cv-692-RWS-RSP
`
`
`
`
`
`Case No. 2:16-cv-695-RWS-RSP
`
`Defendants.
`
`
`
`
`
`DEFENDANTS’ INVALIDITY CONTENTIONS
`
`Pursuant to the Court’s Scheduling Order, Defendants collectively serve their Disclosures
`
`Under Local Patent Rule 3-3 on Plaintiff Alacritech, Inc. These invalidity contentions relate to
`
`the following U.S. Patent Nos. and claims:
`
`U.S. Patent No. 7,124,205 (“the ’205 Patent”), claims 1, 3-11, 13, 16, 22, 24-33, 35, and
`
`36
`
`U.S. Patent No. 7,237,036 (“the ’036 Patent”), claims 1-7
`
`U.S. Patent No. 7,337,241 (“the ’241 Patent”), claims 1-10, 12-19, and 22
`
`U.S. Patent No. 7,673,072 (“the ’072 Patent”), claims 1-5 and 7-19
`
`U.S. Patent No. 7,945,6991 (“the ’699 Patent”), claims 1-3, 6-7, 10-11, 13, and 16-17
`
`U.S. Patent No. 8,131,880 (“the ’880 Patent”), claims 1, 5-10, 12, 14, 16-17, 20-23, 27, 28,
`
`32, 34-35, 37-39, 41-43, 45, and 55
`
`
`1 U.S. Patent No. 7,945,699 is not asserted against any defendant in Alacritech, Inc. v. Wistron
`Corp., et al., Case No. 2:16-cv-692-RWS-RSP.
`
`
`
`Alacritech Ex. 2002, Page1
`
`

`

`U.S. Patent No. 8,805,948 (“the ’948 Patent”), claims 1, 3, 6-9, 11, 14-17, 19, 21, and 22
`
`U.S. Patent No. 9,055,104 (“the ’104 Patent”), claims 1, 6, 9, 12, 15, and 22 (collectively
`
`“Asserted Patents”).
`
`RESERVATIONS AND SCOPE
`
`Defendants’ Invalidity Contentions reflect present knowledge and contentions, and
`
`Defendants reserve all rights to modify and supplement these contentions without prejudice in the
`
`event that additional invalidity or unenforceability grounds are identified. Defendants’ Invalidity
`
`Contentions are not, and should not been seen as, admissions or adoptions as to any particular
`
`claim scope or construction, or as any admission that any particular element is met in any particular
`
`way. Defendants object to any attempt to imply claim constructions from any identification or
`
`description of potential prior art. In addition, Defendants’ Invalidity Contentions may rely upon
`
`Alacritech’s improper assertions of infringement and improper applications of the claims, but
`
`Defendants do not agree with those applications and deny infringement.
`
`Defendants reserve all rights to rely on witness testimony to supplement these Invalidity
`
`Contentions, where appropriate. Further, to the extent an accused product or feature comprises or
`
`arises from prior art, Defendants contend, without admitting purported infringement, that the
`
`Asserted Patents are anticipated and/or made obvious in light of that prior art.
`
`Defendants further reserve all rights to seek leave to amend their Invalidity Contentions in
`
`view of, without limitation: (1) information provided by Alacritech concerning its infringement
`
`allegations, theories, contentions, facts supporting them, prior suits involving the Asserted Patents
`
`or related patents, and/or positions that Alacritech or its fact or expert witness(es) may take
`
`concerning claim construction, infringement, and/or invalidity issues; (2) information provided by
`
`Alacritech concerning the alleged priority, conception, and reduction to practice dates for any of
`
`the asserted claims; (3) any change by Alacritech in the asserted claims; (4) the claim construction
`
`2
`
`Alacritech Ex. 2002, Page2
`
`

`

`process; (5) additional prior art, including, without limitation, prior art obtained through discovery
`
`from Alacritech or a third party or from prior suits involving the Asserted Patents or related patents;
`
`or (6) any other basis in law or in fact.
`
`BACKGROUND OF THE ART AND MOTIVATIONS TO COMBINE
`
`
`
`All network communication entails protocol processing overhead. All of the art cited in
`
`these invalidity contentions is directed to solving the problem of accomplishing the required
`
`protocol processing in the face of ever-increasing network communication speeds and traffic.
`
`Additionally, all of the art cited in these invalidity contentions is directed to solving the well-
`
`known problems of optimizing the networking protocol processing path, reducing the overall
`
`network protocol processing impact on the host computer system, while maintaining or increasing
`
`networking communication performance, and distributing protocol overhead among computing
`
`elements. Persons of skill in the art understood that a variety of well understood techniques could
`
`be applied, individually or collectively, to solve these problems. Thus, persons of skill in the art
`
`would be motivated to combine the teachings of the references cited in these invalidity contentions
`
`to solve these problems.
`
`
`
`The fast-path slow-path concept articulated and claimed by the Asserted Patents was an
`
`application of a well-known prior art performance tuning technique that had been applied to
`
`network protocol processing by many researchers and practitioners. Software practitioners would
`
`frequently profile and analyze the commonly used execution path to determine if any optimizations
`
`to this common execution path would benefit the performance of the overall software system.
`
`These techniques are almost as old as the software field itself and have long been taught in
`
`introductory courses in the field. Persons of skill in the art in the mid-1990s were aware of the
`
`application of these profiling and performance tuning techniques and applied them to the field of
`
`3
`
`Alacritech Ex. 2002, Page3
`
`

`

`protocol processing generally and TCP/IP specifically. Networking protocols including TCP/IP
`
`are frequently described and implemented using state machines with a variety of states and actions
`
`required to transition between those states. These state machines have typically been first
`
`implemented in software and then optimized and implemented in whole or in part in dedicated
`
`hardware.
`
`
`
`For example, Front-end protocol processors (or FEPs) date at least from the 1970s and
`
`were deployed with mainframe computers manufactured by IBM, Burroughs, and others. Front-
`
`end processors that ran the majority of the protocol stack were well-known in the prior art during
`
`the 1970s development of the ARPANET. Offloading via a front-end processor or network front
`
`ends (NFE) was so well-known to the early Internet pioneers that they stated in RFC 647 (dated
`
`November 1974) that “[i]n what might be thought of as the greater network community, the
`
`consensus is so broad that the front-ending is desirable that the topic needs almost no discussion
`
`here.”
`
`
`
`ARPANET has been in existence since the 1970s and the TCP/IP-based Internet since the
`
`early 1980s. However, the introduction of the World Wide Web in the early 1990s precipitated
`
`the wide-spread use of the Internet outside of the established government, business and academic
`
`communities. The foundational protocol of the World Wide Web was HTTP, which was above
`
`the TCP/IP level in the protocol stack. The number of World Wide Web users increased
`
`exponentially during the mid-1990s, driving an exponential growth of TCP/IP traffic as well.
`
`Local area network speeds also increased by orders of magnitude in the early to mid-1990s, rapidly
`
`increasing demands on network protocol stacks and network adapters. This exponential growth in
`
`TCP/IP network traffic and speeds motivated researchers and practitioners to investigate and apply
`
`4
`
`Alacritech Ex. 2002, Page4
`
`

`

`known networking and computer system optimization principles and techniques to the TCP/IP
`
`protocol stack.
`
`
`
`Analysis of high volume, high usage network loads and protocol processing paths led
`
`practitioners and researchers to understand that the majority of TCP/IP protocol processing
`
`overhead was due to connections in the “established” state. Analysis of networking traffic led Van
`
`Jacobson to realize that the majority of the fields of the TCP/IP protocol headers did not change
`
`from packet to packet over such an established connection. His analysis showed that only a few
`
`fields of the TCP/IP header changed and that the TCP/IP header of the next-expected TCP segment
`
`could frequently be accurately predicted from the header of the previous packet. As such, he
`
`devised a header compression technique that took advantage of this observation and only
`
`transmitted an indication that the next header is, in fact, the predicted header. Other researchers
`
`relied on Van Jacobson’s and related work in this area to optimize the transmit and receive protocol
`
`processing paths based on the small number of fields in the TCP/IP header that are likely to change
`
`between successive packets on an established TCP/IP connection.
`
`Van Jacobson’s work in the TCP protocol field resulted in a widely cited paper entitled,
`
`“An Analysis of TCP Processing Overhead,” coauthored with Clark, Romkey, and Salwen and
`
`published in 1989. This paper and Van Jacobson’s other works were cited by numerous references
`
`in these invalidity contentions including, but not limited to, Afterburner, Biersack, Chua, Hotz,
`
`Floyd, Hall, IBM Redbook, Koelbel, Maclean, Nectar, Rutsche, Stevens, Tanenbaum, Thia, Thia
`
`2, Whetton, Traw, and Woodside. These and other commonly cited authors and literature
`
`demonstrate that the references cited in these invalidity contentions are directed to the common
`
`set of well-known problems described above, and the teachings of these references would readily
`
`be combined by persons of ordinary skill in the art.
`
`5
`
`Alacritech Ex. 2002, Page5
`
`

`

`Furthermore, a persona having ordinary skill in the art would be motivated to combine
`
`references by the same author that relate to the same general subject matter area to solve the
`
`problems indicated in each reference, including, but not limited to, reference by Osborne, Traw,
`
`Thia, Lindsay, and others. A person having ordinary skill in the art would also be motivated to
`
`combine references that relate to the same products or systems to take full advantage of solutions
`
`available for those products or systems.
`
`This Section is incorporated by reference below in the obviousness section for each
`
`Asserted Patent.
`
`I.
`
`IDENTIFICATION OF PRIOR ART UNDER §§ 102 AND 103
`
`Defendants list below the currently known prior art that anticipates or renders obvious the
`
`Asserted Patents’ Asserted Claims under 35 U.S.C. § 102 and/or § 103 (pre-AIA) expressly or
`
`inherently as is detailed below and in the charts attached as Exhibits 1-11.
`
`For references that invalidate under 35 U.S.C. § 102(b), those references were publicly
`
`known and available no later than their publication dates, and persons with knowledge of that
`
`public availability include without limitation the author(s) of the reference. Defendants continue
`
`to investigate the prior art identified below and reserve the right to offer additional evidence that
`
`may be uncovered after further discovery.
`
`United States Patent References
`
`Patent number, priority date, and date of issue or
`publication
`
`Bates Nos.
`
`Connery et al., U.S. Patent Number 5,937,169 – Offload of
`TCP Segmentation to a Smart Adapter (August 10, 1999)
`(“Connery” or “3Com)
`
`DEFS-ALA0006946-DEFS-
`ALA0006964
`
`6
`
`Alacritech Ex. 2002, Page6
`
`

`

`Patent number, priority date, and date of issue or
`publication
`
`Bates Nos.
`
`Bach et al., U.S. Patent Number 5,619,650 - Network
`Processor for Transforming a Message Transported from an
`I/O Channel to a Network by Adding a Message Identifier
`and then Converting the Message (April 8, 1997) (“Bach
`650”)
`
`Border et al., Pub. No.: US 2002/0038373 A1 - Method and
`System for Improving Network Performance Enhancing
`Proxy Architecture with Gateway Redundancy (March 28,
`2002) (“Border 373”)
`
`Morris, III, U.S. Patent Number 5,915,124 – Method and
`Apparatus for a First Device Accessing Computer Memory
`and a Second Device Detecting the Access and Responding
`by Performing Sequence of Actions (June 22 ,1999)
`(“Morris 124”)
`
`Yokoyama et al., U.S. Patent Number 5,678,060 – System
`for Executing High Speed Communication Protocol
`Processing by Predicting Protocol Header of Next Frame
`Utilizing Successive Analysis of Protocol Header Until
`Successful Header Retrieval (October 14, 1997)
`(“Yokoyama”)
`
`DEFS-ALA0007042-DEFS-
`ALA0007065
`
`DEFS-ALA0007077-DEFS-
`ALA0007109
`
`DEFS-ALA0010646-DEFS-
`ALA0010661
`
`DEFS-ALA0011906-DEFS-
`ALA0011931
`
`Harumoto, et al., U.S. Patent Number 6,009,471 – Server
`System and Methods for Conforming to Different Protocols
`(April 19, 1997) (“Haurmoto”)
`
`DEFS-ALA0011326-DEFS-
`ALA0011344
`
`Traw, et al., U.S. Patent No. 5,274,768 - High-performance
`host interface for ATM networks (filed May 28, 1991,
`issued Dec. 28, 1993(“Traw 768”)
`
`DEFS-ALA0009941-DEFS-
`ALA0009961
`
`Row, et al., U.S. Patent No. 5,355,453, Parallel I/O network
`file server architecture (filed Oct. 13, 1992, issued Oct. 11,
`1994, priority Sept. 8, 1989) (“Row 453”)
`
`DEFS-ALA0010943-DEFS-
`ALA0010989
`
`Connery, et al., U.S. Patent No. 6,246,683 - Receive
`processing with network protocol bypass (filed May 1,
`1998, issued June 12, 2001) (“Connery 683”)
`
`DEFS-ALA0011421-DEFS-
`ALA0011430
`
`Robles, et al., U.S. Patent No. 6,282,172 - Generating
`acknowledgement signals in a data communication system
`(filed Apr. 1, 1997, issued Aug. 28, 2001) (“Robles 172”)
`
`DEFS-ALA0011431-DEFS-
`ALA0011463
`
`Dillon, U.S. Patent No. 6,701,370 - Network system with
`TCP/IP protocol spoofing (filed June 19, 2000, issued
`March 2, 2004, priority June 8, 1994) (“Dillon 370”)
`
`DEFS-ALA0011570-DEFS-
`ALA0011592
`
`7
`
`Alacritech Ex. 2002, Page7
`
`

`

`Patent number, priority date, and date of issue or
`publication
`
`Bates Nos.
`
`Kelleher, U.S. Patent No. 6,757,767 - Method for
`acceleration of storage devices by returning slightly early
`write status (filed May 31, 2000, issued June 29, 2004)
`(“Kellerher 767”)
`
`Dighe, et al., U.S. Patent No. 5,717,691 - Multimedia
`network interface for asynchronous transfer mode
`communication system (filed Oct. 30, 1995, issued Feb. 10,
`1998) (“Dighe 691”)
`
`Jolitz, et al., U.S. Patent No. 6,173,333 - TCP/IP network
`accelerator system and method which identifies classes of
`packet traffic for predictable protocols (filed Jul. 17, 1998,
`issued Jan. 9, 2001, priority Jul. 18, 1997)
`
`DEFS-ALA0011593-DEFS-
`ALA0011601
`
`DEFS-ALA0011121-DEFS-
`ALA0011135
`
`DEFS-ALA0014691-DEFS-
`ALA0014706
`
`Beach, et al., U.S. Patent No. 5,058,110 - Protocol
`Processor (filed May 3, 1989, issued Oct. 15, 1991)
`
`DEFS-ALA0014335-DEFS-
`ALA0014360
`
`Kirby, et al., U.S. Patent No. 5,828,846 - Controlling
`passage of packets or messages via a virtual connection or
`flow (filed Nov. 22, 1995, issued Oct. 27, 1998) (“Kirby
`846”)
`
`DEFS-ALA0014574-DEFS-
`ALA0014586
`
`Van Renesse, et al. U.S. Patent No. 6,208,651 - Method and
`system for masking the overhead of protocol layering (filed
`Aug. 9, 1998, issued Mar. 27, 2001, priority June 10, 1997)
`
`DEFS-ALA0014707-DEFS-
`ALA0014720
`
`Yokoyama, et al., U.S. Patent No. 5,303,344 - Protocol
`processing apparatus for use in interfacing network
`connected computer systems utilizing separate paths for
`control information and data transfer (filed Feb. 25, 1991,
`issued Apr. 12, 1994, priority Mar. 13, 1989) (“Yokoyama
`344”)
`
`Jayam, et al., U.S. Patent No. 6,981,014 - Systems and
`methods for high speed data transmission using TCP/IP
`(filed Aug. 30, 2002, issued Dec. 27, 2015, priority Aug. 31,
`2001) (“Jayam 014”))
`Lindsay, U.S. Patent No. 6,564,267 - Network adapter with
`large frame transfer emulation (filed Nov. 11, 1999, issued
`May 13, 2003) (“Lindsay 267”)
`
`DEFS-ALA0014361-DEFS-
`ALA0014435
`
`DEFS-ALA0011678-DEFS-
`ALA0011702
`
`DEFS-ALA0011520-DEFS-
`ALA0011543
`
`Lindsay, U.S. Patent No. 6,788,704 - Network Adapter with
`TCP windowing support (filed Aug. 5, 1999, issued Sept. 7,
`2004) (“Lindsay 704”)
`
`DEFS-ALA0011602-DEFS-
`ALA0011618
`
`8
`
`Alacritech Ex. 2002, Page8
`
`

`

`Patent number, priority date, and date of issue or
`publication
`
`Bates Nos.
`
`Puerzer, et al., U.S. Patent No. 4,858,112 - Interface
`comprising message and protocol processors for interfacing
`digital data with a bus network (filed Dec. 17, 1987, issued
`Aug. 15, 1989) (“Puerzer”)
`
`DEFS-ALA0010859-DEFS-
`ALA0010868
`
`Szwerinski et al, U.S. Patent No. 5517668 - Distributed
`protocol framework (filed Jan. 10, 1994) (Szwerinski)
`
`DEFS-ALA0007226 - DEFS-
`ALA0008073
`
`Osborne, UK Patent Number 2,301,264 - Computer network
`interface and interface protocol (November 27, 1996)
`(“Osborne 264”)
`
`DEFS-ALA0009852 – DEFS-
`ALA0009940
`
`Osborne, US Patent Number 5,682,553 – Host Computer
`and Network Interface Using a Two-dimensional Per-
`application List of Application Level Free Buffers (filed
`April 14, 1995; issued October 28, 1997) (“Osborne 553”)
`
`DEFS-ALA0011110 – DEFS-
`ALA0011120
`
`Minami et al., US Patent Number 6,034,963 – Multiple
`Network Protocol Encoder/Decoder and Data Processor
`(filed October 31, 1996; issued March 7, 2000) (“Minami”)
`
`DEFS-ALA0011345 – DEFS-
`ALA0011366
`
`Rubin et al., US Patent Number 5,265,261 - Method and
`system for network communications using raw mode
`protocols (filed Feb. 2, 1993, issued Nov. 23, 1993) (“Rubin
`261”)
`
`DEFS-ALA0010932 – DEFS-
`ALA0010942
`
`Border et al., US Patent Number 6,973,497 - Selective
`spoofer and method of performing selective spoofing (filed
`Sep. 18, 2000, issued Dec. 6, 2005)
`
`DEFS-ALA0005219 – DEFS-
`ALA0005226
`
`
`
`Prior Art Publications
`
`Title, date of publication, and author
`
`Bates Nos.
`
`Byron Gillespie, PCI Intelligent I/O Design for High
`Performance Servers (1996) (“Gillespie”)
`
`DEFS-ALA0002156-DEFS-
`ALA0002170
`
`Alteon Networks, Inc., Gigabit Ethernet Technical Brief:
`Achieving End-to-End Performance (September 1996)
`(“Alteon”)
`
`Ernst W. Biersack, Erich Rutsche, Thomas Unterschutz,
`Demultiplexing on the ATM Adapter: Experiments with
`Internet Protocols in User Space (December 1994)
`(“Biersack”)
`
`DEFS-ALA0007016-DEFS-
`ALA0007041
`
`DEFS-ALA0007066-DEFS-
`ALA0007076
`
`9
`
`Alacritech Ex. 2002, Page9
`
`

`

`Title, date of publication, and author
`
`Bates Nos.
`
`Protocol Engines Incorporated, Protocol Engine Handbook
`(Exh. D of Declaration of Dr. Gregory L. Chesson in
`Support of MSFT’s Opposition to Alacritech’s Mot. for
`Preliminary Injunction) (October 9, 1990) (“Protocol
`Engine”)
`
`David D. Clark et al., An Analysis of TCP Processing
`Overhead (June 1989) (“Clark”)
`
`Roy Chua, MacDonald Jackson, Marylou Orayani, A Fast
`Track Architecture for UDP/IP and TCP/IP (May 9, 1995)
`(“Chua”)
`
`Chris Dalton et al., Afterburner: Architectural Support for
`High-Performance Protocols (July 1993) (“Dalton”)
`
`Gerard Bourbigot and Frank Vandewiele of IBM, TCP/IP
`Tutorial and Technical Overview (June 1995) (“Bourbigot”)
`
`Intel, 82557 10/100 Mbps PCI LAN Controller A Guide to
`82596 Compatibility (November 1995) (“Intel 82557”)
`
`Special Interest Group on Data Communication, Computer
`Communication Review (April 1990) (“Special Interest
`Group”)
`
`DEFS-ALA0007117-DEFS-
`ALA0007162
`
`DEFS-ALA0007181-DEFS-
`ALA0007187
`
`DEFS-ALA0007163-DEFS-
`ALA0007180
`
`DEFS-ALA0007188-DEFS-
`ALA0007205
`
`DEFS-ALA0010002- DEFS-
`ALA0010483
`
`DEFS-ALA0010490-DEFS-
`ALA0010505
`
`DEFS-ALA0010506- DEFS-
`ALA0010510
`
`Hemant Kanakia et al., The VMP Network Adapter Board
`(NAB): High-Performance Network Communication for
`Multiprocessors (August 1988) (“Kanakia”)
`
`DEFS-ALA0010586-DEFS-
`ALA0010600
`
`R. Andrew Maclean and Scott E. Barvick, An Outbound
`Processor for High Performance Implementation of
`Transport Layer Protocols (December 1991) (“Maclean”)
`
`DEFS-ALA0010601-DEFS-
`ALA0010607
`
`Emmanuel A. Arnould, The design of Nectar : a network
`backplane for heterogeneous multicomputers (January
`1989) (“Arnould”)
`
`Eric C. Cooper, Protocol implementation on the Nectar
`communication processor (September 1990) (“Cooper”)
`
`Erich Rutsche, The Architecture of a Gb/s Multimedia
`Protocol Adapter (July 1993) (“Rutsche”)
`
`Y.H. Thia and C.M. Woodside, A Reduced Operation
`Protocol Engine (ROPE) for a multiple-layer bypass
`architecture (1995) (“Thia”)
`
`DEFS-ALA0010662-DEFS-
`ALA0010681
`
`DEFS-ALA0010704DEFS-
`ALA0010725
`
`DEFS-ALA0010789-DEFS-
`ALA0010798
`
`DEFS-ALA0010834-DEFS-
`ALA0010849
`
`10
`
`Alacritech Ex. 2002, Page10
`
`

`

`Title, date of publication, and author
`
`Bates Nos.
`
`Brain Whetten, Todd Montgomery and Malik Kalfane, A
`Fast Track Architecture for High Performance, Fault-
`Tolerant Reliable Distributed Group Communication
`(February 21, 1995) (“Whetten”)
`
`C. M. Woodside, K. Ravindran, and R. G. Franks, The
`Protocol Bypass Concept for High Speed OSI Data Transfer
`(1991) (“Woodside”)
`
`J. Satran, Internet Task Force Draft entitled “SCSI/TCP
`(SCSI over TCP) (February 2000) (“Satran I”)
`
`J. Satran, Internet Task Force Draft entitled “iSCSI (Internet
`SCSI)” (June 2000) (“Satran II”)
`
`Technical Standard: Protocols for X/Open PC Interworking:
`SMC, Version 2 (1992) (“SMB Technical Standard”)
`
`R. Snively, Implementing a Fibre Channel SCSI Transport
`(1994) (“Snively”)
`
`W. Richard Stevens, TCP/IP Illustrated, Volume 1 (1994)
`(“Stevens I”)
`
`Gary R. Wright and W. Richard Stevens II, TCP/IP
`Illustrated Volume 2, The Implementation (February 10,
`1995) (“Stevens II”)
`
`Andrew S. Tanenbaum, Computer Networks (1996)
`(“Tanenbaum”)
`
`Van Meter et al., VISA: Netstation’s Virtual Internet SCSI
`Adapter (1998) (“VISA”)
`
`RFC 2054: WebNFS Client Specification (1996)
`(“WebNFS”)
`
`Steve Hotz, Rodney Van Meter, and Gregory Finn, Internet
`Protocols for Network-Attached Peripherals (March 1998)
`(“Hotz”)
`
`DEFS-ALA0011866-DEFS-
`ALA0011885
`
`DEFS-ALA0011886-DEFS-
`ALA0011901
`
`DEFS-ALA0004492-DEFS-
`ALA0004537
`
`DEFS-ALA0004538-DEFS-
`ALA0004598
`
`DEFS-ALA0003958-DEFS-
`ALA0004491
`
`DEFS-ALA0004610-DEFS-
`ALA0004614
`
`DEFS-ALA0004615-DEFS-
`ALA0005218
`
`DEFS-ALA0012545-DEFS-
`ALA0013749
`
`DEFS-ALA0014283-DEFS-
`ALA0014320
`
`DEFS-ALA0005263-DEFS-
`ALA0005272
`
`DEFS-ALA0017060-DEFS-
`ALA0017075
`
`DEFS-ALA0003943-DEFS-
`ALA0003957
`
`TCP/IP Tutorial and Technical Overview (“IBM Redbook”) DEFS-ALA0017365-DEFS-
`ALA0017975
`
`Meryem Primmer, An Introduction to Fibre Channel
`(October 1996) (“Primmer”)
`
`D. Schmidt, Measuring the Performance of Parallel
`Message-based Process Architectures (April 1995)
`(“Schmidt”)
`
`DEFS-ALA0003920- DEFS-
`ALA0003926
`
`DEFS-ALA0014272- DEFS-
`ALA0014282
`
`Intel, 82558 Ethernet Controller Software Developer's
`Manual, Version 2.0 (November 15, 1997) (“Intel 82558”)
`
`DEFS-ALA0016880-DEFS-
`ALA0017039
`
`11
`
`Alacritech Ex. 2002, Page11
`
`

`

`Title, date of publication, and author
`
`Bates Nos.
`
`PSi: a silicon compiler for very fast protocol processing
`(Abu-Amara et al, Asynchrony and Columbia 1989) (“Abu-
`Amara”)
`
`Rainbow II Gigabit Optical Network (Hall et all, IEEE June
`1996) (“Hall”)
`
`VLSI Implementations of Communication Protocols
`(Krishnakumar et al, IEEE 1989) (“Krishnakumar”)
`
`XTP in VLSI Protocol Decomposition for ASIC
`Implementation (Schwaderer, IEEE 1990) (“Schwaderer” or
`“Schwaderer 1990”))
`
`DEFS-ALA0010763- DEFS-
`ALA0010778
`
`DEFS-ALA0010779- DEFS-
`ALA0010788
`
`DEFS-ALA0011857- DEFS-
`ALA0011865
`
`DEFS-ALA0011902- DEFS-
`ALA0011905
`
`Hemant Kanakia et al., Universal Network Device Interface
`Protocol (UNDIP) (1988) (“UNDIP”)
`
`DEFS-ALA0010850- DEFS-
`ALA0010858
`
`I2O Special Interest Group, Intelligent I/O (I2O)
`Architecture Specification (Revision 1.5 March 1997) (“I2O
`Architecture”)
`
`DEFS-ALA0013769- DEFS-
`ALA0014271
`
`Randy Haagens, iSCSI (Internet SCSI) Requirements (July
`2000) (“Haagens”)
`
`DEFS-ALA0015623- DEFS-
`ALA0015643
`
`IBM Corporation, Local Area Network Concepts and
`Products: Routers and Gateways (First Edition May 1996)
`(“LAN Concepts”)
`
`IBM Corporation, Network Clients for OS 2 Warp Server
`(First Edition August 1997) (“Warp Server”)
`
`PCI Special Interest Group, PCI Local Bus Specification
`(Revision 2.1 June 1, 1995) (“PCI Specification”)
`
`Microsoft Corporation, SMB File Sharing Protocol (January
`1, 1996) (“SMB Protocol”)
`
`B. Callaghan, et al., NFS Version 3 Protocol Specification
`(June 1995) (“Callaghan”) (RFC 1813)
`
`High Speed OSI Protocol Bypass Algorithm with Window
`Flow Control by Y.H. Thia and C.M. Woodside (April 16,
`1992) (“Thia 2”)
`
`DEFS-ALA0015942- DEFS-
`ALA0016241
`
`DEFS-ALA0016242- DEFS-
`ALA0016685
`
`DEFS-ALA0015644- DEFS-
`ALA0015941
`
`DEFS-ALA0016686- DEFS-
`ALA0016879
`
`DEFS-ALA0001662- DEFS-
`ALA0001787
`
`DEFS-ALA0003005- DEFS-
`ALA0003014
`
`C. Koelbel, et al. Workshop on Experiences with Building
`Distributed and Multiprocessor Systems (April 1990)
`(“Koelbel”)
`
`DEFS-ALA0017054- DEFS-
`ALA0017059
`
`Van Jacobson, Re: maximum Ethernet throughput (March
`10, 1988) (“Jacobson Posting”)
`
`DEFS-ALA0017076- DEFS-
`ALA0017364
`
`12
`
`Alacritech Ex. 2002, Page12
`
`

`

`Title, date of publication, and author
`
`Bates Nos.
`
`IBM Corporation, 3172 Interconnect Controller Model 390
`Supplement to Maintenance Information (Second Edition
`April 1996) (“IBM 3172 Supplement”)
`
`DEFS-ALA0013750- DEFS-
`ALA0013768
`
`Intel Corporation, Intel 82599 10 GbE Controller Datasheet
`(Revision 2.3 April 2010) (“Intel 82599”)
`
`DEFS-ALA0014781- DEFS-
`ALA0015622
`
`A VLSI Receive Architecture for High Speed ATM
`Computer Networks (Chow, Univ. of British Columbia
`1994) (“Chow 1994”)
`
`Hardware/Software Organization of a High Performance
`ATM Host Interface (Traw et al., Univ. of Pennsylvania
`1993) (“Traw 1993”)
`
`Torsten Braun, et al., A Modular VLSI Implementation
`Architecture for Communication Subsystems (1995)
`(“Braun”)
`
`DEFS-ALA0011757 – DEFS-
`ALA0011856
`
`DEFS-ALA0009978 – DEFS-
`ALA0010001
`
`DEFS-ALA0010630 – DEFS-
`ALA0010645
`
`
`
`Prior Art Products and Uses2
`
`Prior Art Products and Uses
`
`Bates Nos.
`
`Greg Chesson and Des Young, The Protocol Engine®
`Chipset (1992) (“Chesson”)
`
`Zygmunt Haas, A Communication Architecture for High-
`Speed Networking, IEEE (1990) (“Haas”)
`
`Jeffrey R. Michel, The Design and Evaluation of an Off-
`Host Communications Protocol Architecture, University of
`Virginia (August 1993) (“Michel” or “Michel 1993”).
`
`DEFS-ALA0010752- DEFS-
`ALA0010762
`
`DEFS-ALA0006965- DEFS-
`ALA0006973
`
`DEFS-ALA0012071- DEFS-
`ALA0012209
`
`Nanette J. Boden et al., Myrinet: A Gigabit-per-Second
`Local Area Network, IEEE (February 1995) (“Boden”)
`
`DEFS-ALA0001473- DEFS-
`ALA0001480
`
`IBM Corporation, 3172 Interconnect Controller Model 390
`Supplement to Maintenance Information (Second Edition
`April 1996) (“IBM 3172 Supplement”)
`
`DEFS-ALA0013750- DEFS-
`ALA0013768
`
`Intel Corporation, Intel 82599 10 GbE Controller Datasheet
`(Revision 2.3 April 2010) (“Intel 82599”)
`
`DEFS-ALA0014781- DEFS-
`ALA0015622
`
`On information and belief, an Intel engineer, Uri Elzur,
`conceived of offloading TCP segmentation to a network
`adapter during 1996. On information and belief, Mr. Elzur
`met with Microsoft technical personal in early 1997 to
`
`N/A
`
`
`2 These prior uses are prior art under 35 U.S.C. § 102(a) (known or used in the US); (b) (public
`use in the US); and/or (g) (made in the US).
`
`13
`
`Alacritech Ex. 2002, Page13
`
`

`

`Prior Art Products and Uses
`
`Bates Nos.
`
`discuss the operating system support required to effectuate
`and standardize such a TCP segmentation offload. On
`information and belief, Intel and Microsoft collaborated
`during 1997 on operating system details for TCP
`Segmentation Offload support. On information and belief,
`Intel implemented TCP Large Send on at least one network
`interface card by January, 1998. On information and belief,
`Mr. Elzur described Intel’s TCP Segmentation Offload
`design in a design document for a Gigabit Ethernet
`controller code named Livengood. Intel released the 82543
`Gigabit Ethernet product based on this design no later than
`the second quarter of 2000.
`
`On information and belief, Mr. Elzur communicated the
`status of his work on TCP segmentation offloading to at
`least the following people during August 1997:
`
`Gideon Prat
`Yuval Bachrach
`Levy Yossi
`Gil Frostig
`Amir Zinaty
`Avi Salmon
`Noam Etzion
`David Madar
`Dany Rettig
`Dan Warski
`Oded Rosenstein
`Solomon Trainin
`Mark J Abel
`
`On information and belief, at least the following individuals
`were involved in describing operating system changes
`required for TCP Segmentation Offload support in August-
`October 1997:
`
`kyleb
`Derrell Piper
`nk
`Rob Adams
`v-johnph
`Sanjay Anand
`
`This product is referred to as “Intel TSO.”
`
`14
`
`Alacritech Ex. 2002, Page14
`
`

`

`Prior Art Products and Uses
`
`Bates Nos.
`
`Intel 82558 Product
`
`Offered for sale: April 21, 1997
`
`Offered for sale to: Intel’s customers
`
`Intel 82557 Product
`
`Offered for sale: September 1, 1995
`
`Offered for sale to: Intel’s customers
`
`N/A
`Collectively, “Intel Prior Art”
`
`Exelan Inc., NX 200 Network Executive Reference Manual
`(Rev. A, May 28, 1986) (“NX 200”)
`
`DEFS-ALA0008755 – DEFS-
`ALA0008988
`
`
`Copies of the foregoing references identified above have been or are being produced along
`
`with these Invalidity Contentions. Defendants are also producing art that they feel is relevant to
`
`the claimed patents and may rely on such to teach the state of the art.
`
`Each of the references and systems listed above qualifies as prior art under one or more
`
`sections of 35 U.S.C. §§ 102 and/or 103, as detailed below. The invalidating disclosure in each of
`
`the listed references and materials is express, implicit, and/or inherent. Defendants reserve the
`
`right to rely on prior art in the accompanying production, prior art produced by Plaintiff or third
`
`parties, and/or prior art cited in the charts accompanying these invalidity contentions to show the
`
`state of the art, the knowledge of one of ordinary skill in the art, and/or the anticipation or
`
`obviousness of the Asserted Patents. The references provided herein may also be relied upon to
`
`show the state of the art in the relevant time frame. Also, to the extent that any of the references
`
`listed above are deemed not to be prior art, they may nevertheless provide evidence of prior or
`
`simultaneous invention, thereby supporting the obviousness of the asserted claims.
`
`To the extent they constitute prior art, Defendants reserve the right to rely upon any of the
`
`following art related to the prior art identified herein: (i) foreign counterparts of the U.S. patents
`
`identified; (ii) U.S. counterparts of any foreign patents and foreign patent applications identified;
`
`(iii) U.S. and foreign patents and patent applications corresponding to any articles and publications
`
`15
`
`Alacritech Ex. 2002, Page15
`
`

`

`identified; (iv) any products, prior inventions, or publications that relate to any references
`
`identified; and (v) any patents, patent applications or publications that relate to any identified
`
`system. In addition, the specification and prosecution history of the Asserted Patents and related
`
`patents and/or applications contain descriptions of, and admissions concerning, the scope of the
`
`claims. Defendants intend to rely upon these descriptions and admissions. Defendants also
`
`identify all prior art references cited or included in the Asserted Patents and their prosecution
`
`history, as well as any statements in either regarding the prior art in either. Defendants reserve the
`
`right to rely on documents produced by third parties as prior art. Defendants’ Invalidity
`
`Contentions and identification of prior art meet the disclosure requirements of 35 U.S.C. §282(c).
`
`Defendants reserve their rights to amend their contentions to include additional prior art references.
`
`II.
`
`INVALIDITY CONTENTIONS REGARDING THE ’205 PATENT
`
`A. Anticipation and Obviousness References
`
`Pursuant to P.R. 3-3(a) and the Court’s Discovery Order, and in light of Alacritech’s
`
`Infringement Contentions and accompanying claim charts, Defendants list below the prior art now
`
`known to Defendants that anticipates or renders obvious the asserted claims under 35 U.S.C. § 102
`
`and/or 103. Defendants’ contentions do not imply any admission or suggestion that a specific
`
`prior art reference does not independently anticipate the ’205 Patent Asserted Claims. Each
`
`individual prior art reference identified in Section I(A), above, that anticipates and/or each
`
`combination that renders obvious the ’205 Patent Asserted Claims is described below.
`
`Although Defendants have identified at least one disclosure of a limitation for each prior
`
`art reference, each and every disclosure of the same limitation in the same reference is