`
`United States Patent [19]
`Russo et al.
`
`[54] NETWORK ADAPTER WITH HIGH
`THROUGHPUT DATA TRANSFER CIRCUIT
`TO OPTIMIZE NETWORK DATA
`TRANSFERS, WITH HOST RECEIVE RING
`RESOURCE MONITORING AND
`REPORTING
`[75] Inventors: Andrew P. Russo, Hyde Park; Satish
`L. Rege, Groton, both of Mass.;
`Edward T. Sullivan, Highland
`Village, Tex.; Mark F. Kempf, Stow,
`
`Mass.
`
`-
`
`[73] Assignee:
`
`Digital Equipment Corporation,
`Maynard, Mass.
`[21] Appl. No.: 815,008
`[22] Filed:
`Dec. 27, 1991
`[51] Int. Cl* .............................................. G06F 13/00
`[52] U.S. Cl. .................................... 395/200; 395/250;
`395/275
`[58] Field of Search .................. 364/DIG. 1, DIG. 2;
`395/200, 275,250; 370/60, 85.1, 85.2, 94.1
`References Cited
`U.S. PATENT DOCUMENTS
`4,449,122 5/1984 Rubinson et al. ................... 364/200
`4,692,918 9/1987 Elliott et al. .......................... 370/85
`4,942,574 7/1990 Zelle ................................. 370/85.15
`5,058,110 10/1991 Beach et al.
`.... 370/85.6
`5,103,446 4/1992 Fischer ............................... 370/85.1
`
`[56]
`
`||||||||||||||||IIII
`
`5,293,487
`Mar. 8, 1994
`
`US005293487A
`
`[11] Patent Number:
`[45] Date of Patent:
`
`5,136,582 8/1992 Firoozmand ....................... 370/85.1
`OTHER PUBLICATIONS
`Satish Rege, The Architecture and Implementation of a
`High-performance FDDI Adapter, Digital Technical
`Journal, vol. 3, No. 3, Summer 1991, pp. 48–77.
`Primary Examiner—Robert L. Richardson
`Attorney, Agent, or Firm—A. Sidney Johnston; Albert P.
`Cefalo
`ABSTRACT
`[57]
`A network adapter with high throughput data transfer
`circuit to optimize network data transfers, with host
`receive ring resource monitoring and reporting is dis
`closed. Time critical network data is transferred be
`tween the network adapter and the host computer sys
`tem by means of a high throughput data transfer circuit.
`The high throughput data transfer circuit is designed to
`provide throughput equal to the bandwidth of a high
`speed local area network such as the Fiber Distributed
`Data Interconnect. The high throughput data transfer
`circuit will inform the local intelligence of the network
`adapter if the network adapter has used up all host
`computer system memory allocated for storing data
`received from the network. Adapter management data
`is transferred between the network adapter and the host
`computer system local area network through a lower
`throughput data transfer circuit.
`
`18 Claims, 10 Drawing Sheets
`
`
`
`HOST
`MEMORY
`
`SYSTEM
`BUS
`
`HIGH T-PUT
`DATA XFER
`CIRCUIT
`
`PACKET
`MEMORY
`
`LOW T-PUT
`DATA XFER
`CIRCUIT
`
`NETWORKADAPTER
`
`ADAPTER
`MANAGE
`MENT
`SUB
`SYSTEM
`
`HOST
`COMPUTER
`
`Ex.1046.001
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`Mar. 8, 1994
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`Sheet 1 of 10
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`5,293,487
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`Sheet 2 of 10
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`5,293,487
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`Ex.1046.003
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`Sheet 3 of 10
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`5,293,487
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`64
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`Ex.1046.004
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`Sheet 4 of 10
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`5,293,487
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`94
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`Ex.1046.005
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`Mar. 8, 1994
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`Sheet 5 of 10
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`124
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`126
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`UNSOLICITED DATA
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`Ex.1046.006
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`DELL
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`Mar. 8, 1994
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`Mar. 8, 1994
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`Sheet 10 of 10
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`Ex.1046.011
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`DELL
`
`
`
`1
`
`NETWORK ADAPTER WITH HIGH
`THROUGHPUT DATA TRANSFER CIRCUIT TO
`OPTIMIZE NETWORK DATA TRANSFERS, WITH
`HOST RECEIVE RING RESOURCE MONITORING
`AND REPORTING
`
`15
`
`5,293,487
`2
`cated by the host computer system. If all receive buffers
`in host memory are full, the packets cannot be delivered
`to the host computer system. If this event occurs fre
`quently, the host computer system's allocation of re
`ceive buffers in host memory is insufficient.
`Need for New Network Adapter Designs
`The higher bandwidth of the latest generation of
`networks makes solving these problems more difficult
`than in network adapters for previous generation net
`works. A typical fiber optic network, the ANSI defined
`Fiber Distributed Data Interconnect (FDDI), has a
`maximum bandwidth of approximately 100 megabits
`per second, and a packet carrying capacity of approxi
`mately 450,000 packets per second. This is approxi
`mately 10 times the bandwidth, and 30 times the packet
`carrying capacity of Ethernet, a typical previous gener
`ation network. Known designs for Ethernet network
`adapters were designed to meet the lower throughput
`requirements of that network, and are inadequate to
`meet the throughput requirements of networks such as
`FDDI.
`It is therefore desirable to have a network adapter
`design with a data transfer circuit, providing packet
`throughput between the network adapter and the host
`computer system, equal to the packet throughput of a
`high speed network such as FDDI. It is further desir
`able to have a network adapter design include a means
`for informing the host computer system when all re
`ceive buffers in host memory are filled.
`SUMMARY OF THE INVENTION
`The invention solves the problem of providing packet
`throughput between a network adapter and a host com
`puter system, equal to the packet throughput of a high
`speed network such as FDDI. In accordance with prin
`ciples of the invention, there is provided a network
`adapter comprising two data transfer circuits for mov
`ing data to and from the memory in the host computer
`system. The first data transfer circuit provides higher
`throughput, equal to that of a high speed local area
`network such as the Fiber Distributed Data Intercon
`nect (FDDI), for packets directly transferred to or from
`the communications medium. It is implemented entirely
`in hardware. The second data transfer circuit provides
`lower throughput, for data related to adapter manage
`ment services performed internal to the adapter, which
`typically have lower throughput requirements. It is
`implemented partially in hardware, and partially in
`software or firmware running on a microprocessor
`based adapter management subsystem within the
`adapter.
`The invention further provides means to inform the
`host computer system when all receive buffers in host
`memory are filled. This includes a detection means
`within the first data transfer circuit, detecting when all
`host memory allocated for the receipt of packets from
`the network has been filled. A reporting means, respon
`sive to indication provided by the detection means,
`notifies the host computer system of this event via the
`lower throughput data transfer circuit.
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a logic diagram of a network adapter in
`accordance with the principles of the invention;
`FIG. 2 is a diagram of a transmit ring data structure
`in host memory;
`
`FIELD OF THE INVENTION
`This invention relates to communications between a
`10
`network adapter and a host computer, and more partic
`ularly to multiple communications channels between a
`network adapter and a host computer for data transfers
`of different types.
`BACKGROUND INFORMATION
`Network Adapters
`In computer networks a host computer system is
`normally connected to the network by a network
`adapter. In some designs, the network adapter is a board
`that plugs into the backplane bus of the host computer
`20
`system. In other designs, the network adapter is built
`into the CPU motherboard.
`Computer networks transfer data from one network
`node to another in the form of packets. For the purposes
`here, packets may include information for all layers of
`25
`the ISO/OSI model at and above the data link layer.
`The network adapter transmits packets from the host
`computer system onto the network, and delivers pack
`ets from the network to the host computer system.
`Potential Limit on Packet Throughput
`30
`A problem arises when the network adapter cannot
`deliver packets to the host computer system as quickly
`as the network can transfer them to the network
`adapter. In that case, when packets are sent to the net
`work adapter at a sufficient rate for a sustained period,
`35
`packet memory in the network adapter becomes full.
`Subsequent packets sent to the network adapter cannot
`be stored, and will be lost. Lost packets result in costly
`retransmissions, increased network latency, and virtual
`circuits being broken.
`A related problem occurs when the network adapter
`cannot read packets from the host memory in the host
`computer system as quickly as the network can transfer
`them. In this case, the network adapter limits the rate at
`which the host computer system can transmit packets
`45
`onto the network.
`The network adapter provides many services to the
`host computer system. These services include packet
`transmission and packet reception, as well as network
`adapter initialization, network adapter diagnostics, and
`50
`network management functions. The services that may
`limit packet throughput rates are packet transmission
`and packet reception. To avoid a limit on packet
`throughput between the host computer system and the
`network, those two services must move packets be
`55
`tween the network adapter and the host computer sys
`tem, at the same rate packets are transferred on the
`network itself.
`Sufficiency of Host Memory Buffers for Receiving
`Packets
`Another problem occurs when there are insufficient
`buffers in host memory allocated to store packets re
`ceived from the network. When packets are received
`from the network by the network adapter, and are to be
`delivered to the host computer system, the packets are
`65
`first received into the internal packet memory of the
`network adapter. The network adapter then moves the
`packets into receive buffers in the host memory allo
`
`Ex.1046.012
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`unsolicited data resulting from network events, and
`FIG. 3 is a diagram of a receive ring data structure in
`host memory;
`network adapter internal events. An example of unsolic
`ited data is a notification message sent to the host com
`FIG. 4 is diagram of a command ring data structure in
`host memory;
`puter system 20, from the network adapter 10, indicat
`ing the network has changed state, i.e. become available
`FIG. 5 is a diagram of an unsolicited ring data struc
`ture in host memory;
`or unavailable.
`FIG. 6 is a logic diagram associating the higher speed
`Ring Data Structures in Host Memory
`data transfer circuit with the transmit and receive rings,
`FIGS. 2, 3, 4, and 5 show ring data structures in host
`and the lower speed data transfer circuit with the com
`memory 22, used to pass data, including packets, be
`mand and unsolicited rings;
`10
`tween the host computer system 20 and the network
`FIG. 7 is a logic diagram of the elements in FIG. 6,
`adapter 10. The basic protocol of ring operation com
`showing the logical state machines within the higher
`mon to all of these rings is first described. A specific
`throughput data transfer circuit;
`example of operation for each ring is provided below.
`FIG. 8 is a logic diagram of the elements in FIG. 7,
`showing the logical state machines and processes within
`A ring data structure consists of a number of sequen
`tial ring entries. Each ring entry consists of various
`the lower throughput data transfer circuit;
`fields, including an ownership bit. The value of the
`FIG. 9 is a logic diagram of the elements in FIG. 8,
`ownership bit indicates whether the host computer
`further showing the locations of the pointers referenced
`in FIGS. 2 through 5; and
`system 20 or the network adapter 10 owns the ring
`entry. For example, if on a particular ring, when the
`FIG. 10 is a logic diagram of the elements of FIG. 8,
`ownership bit is 1, the host computer system 20 owns
`showing the preferred embodiment where all logical
`the ring entry, then when the ownership bit is 0, the
`stat machines described in the previous drawings are
`implemented in a single application specific integrated
`network adapter 10 owns the ring entry. In the alterna
`tive, if when the ownership bit is 1 the network adapter
`circuit.
`20 owns the ring entry, then the host computer system
`owns the entry when the ownership bit is 0.
`Both the owner and the non-owner may read the
`ownership bit in a ring entry, but only the owner my
`write the ownership bit. Only the owner of a ring entry
`may read or write any of the other fields in the ring
`entry, or the buffer whose address is contained in the
`buffer address field of the ring entry.
`Rings are circular data structures. In the following
`figures, the ring entries are processed from top to bot
`tom, and the bottom ring entry is followed in sequence
`by the ring entry at the top of the ring.
`FIG. 2 shows the transmit ring 30, containing a fixed
`number of transmit ring entries 32a, 32b, ..., 32n (in this
`example, n=i). Each transmit ring entry 32a through
`32n includes an ownership bit 38, a transmit buffer ad
`dress field 40, a transmit buffer length field 44, and a
`transmit completion code 46. A transmit free pointer 48,
`and a transmit fill pointer 50, exist in the host computer
`system 20. A next transmit pointer 52, exists in the net
`work adapter 10.
`For purposes of example, the transmit free pointer 48
`and the transmit fill pointer 50, in the host computer
`system 20, point to transmit ring entry 32e and transmit
`ring entry 32h, respectively. The transmit next pointer
`52 in the network adapter 10 points to transmit ring
`entry 32e. Transmit ring entries with ownership bit
`equal to 1 (32e, 32f, and 32g), are owned by the network
`adapter 10. The transmit buffer address fields of these
`three entries contain the addresses of transmit buffers
`54, 56, and 58 respectively. These transmit buffers each
`contain a packet to be sent by the adapter 10 onto the
`network 26. Those ring entries with ownership bit equal
`to 0 (32a, 32b, 32c, 32d, 32h, and 32i), are owned by the
`host computer system.
`Prior to when this example begins, the host computer
`system 20 passed the ownership of three transmit ring
`entries, 32e, 32f, and 32g, to the network adapter 10.
`The events occurring as the network adapter 10 pro
`cesses these entries are as follows. The higher through
`put data transfer circuit 16 reads the ownership bit 38 of
`the transmit ring entry pointed to by the transmit next
`pointer 52 (transmit entry 32e), and determines the net
`work adapter 10 owns the entry. Using the transmit
`
`DETAILED DESCRIPTION
`In FIG. 1, there is shown a network adapter 10 in
`accordance with principles of the invention, including a
`lower throughput data transfer circuit 12, an adapter
`management subsystem 14, a higher throughput data
`30
`transfer circuit 16, and a packet memory 18. The lower
`throughput data transfer circuit 12 is coupled to a sys
`tem bus 24, as well as to the adapter management sub
`system 14. The higher throughput data transfer circuit
`16 is coupled to the system bus 24, the packet memory
`35
`18, and the adapter management subsystem 14. External
`to the adapter, a host computer system 20 is shown with
`a host memory 22. The host memory 22 is coupled to
`the system bus 24 by path 25. A network 26 is shown
`coupled to the packet memory 18,
`Now with respect to the operation of the elements in
`FIG. 1, packets received from the network 26 for deliv
`ery to the host computer system 20 are first stored in the
`packet memory 18, The packets are then transferred
`from the packet memory 18 into the host memory 22 by
`45
`means of the higher throughput data transfer circuit 16.
`If no space is available in the host memory 22 for
`packets received from the local area network 26, the
`higher throughput data transfer circuit 16 informs the
`adapter manager 14, which in turn notifies the host
`computer system 20 by means of the lower throughput
`data transfer circuit 12.
`Packets from the host computer system 20, to be
`transmitted onto the network 26, are first read from the
`host memory 22 into the packet memory 18 by means of 55
`the higher throughput data transfer circuit 16. The
`packets are then transferred from the packet memory 18
`onto the network 26.
`-
`Adapter management data is transferred between the
`adapter management subsystem 14 and the host com
`60
`puter system 20 by means of the lower throughput data
`transfer circuit 12. Adapter management data includes
`adapter management commands issued by the host com
`puter system 20 to the network adapter 10 requesting
`adapter initialization, as well as diagnostic, and network
`65
`management functions. Adapter management data also
`includes data transferred to the host computer system
`20 in response to adapter management commands, and
`
`25
`
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`buffer address field 40 and transmit buffer length field
`44 to locate the transmit buffer 54 in host memory 22,
`the higher throughput data transfer circuit 16 moves the
`data from the transmit buffer 54 into the packet memory
`18, for subsequent transmission onto the network 26.
`This movement of data requires multiple accesses to the
`system bus 24 by both the host computer system 20 and
`the network adapter 10. Upon completion of the data
`move, the higher throughput data transfer circuit 16
`writes the tranSmit completion code 46 in the transmit
`ring entry 32e, changes the ownership of the transmit
`ring entry to 0, and advances the transmit next pointer
`52 to point to the next transmit ring entry in sequence
`(32f). Transmit ring entries 32f and 32g are then pro-
`cessed similarly. After transmit ring entries 32fand 32g
`have been processed, the next transmit pointer 52 points
`to transmit ring entry 32h.
`To transmit another packet, the host computer sys-
`tem 20 uses the transmit ring entry pointed to by the
`transmit fill pointer 50 (ring entry 32h). The host com-
`puter system 20 first writes the transmit buffer address
`field 40, and the transmit buffer length field 44 of the
`transmit entry 32):, with the address and length of the
`transmit buffer containing the packet to be transmitted.
`The host computer system 20 then changes the owner-
`ship bit 38 of transmit ring entry 32): to l. The higher
`throughput data transfer circuit 16 reads the ownership
`bit 38 of the transmit ring entry 3211, detects that trans-
`mit ring entry 3211 is owned by the network adapter 10,
`processes it as described above, and sets the next trans-
`mit pointer 52 to point to transmit ring entry 321'. This
`process continues, with the host computer system 20
`providing transmit buffers containing packets to the
`network adapter 10, and the network adapter 10 mov-
`ing the transmit buffers into packet memory 18, for
`transmission on the network 26.
`FIG. 3 shows the receive ring 60, a data structure in
`the host memory 22. The receive ring 60 contains a
`fixed number of receive ring entries 62a, 62b,
`.
`.
`.
`, 62;:
`(in this example. n=1'). Each receive ring entry 62a
`through 62» includes an ownership bit 64, a receive
`buffer address field 66, a receive buffer length field 68,
`and a receive completion code field 70. A receive free
`pointer 72, and a receive fill pointer 74, exist in the host
`computer system 20. A next receive pointer 76, exists in
`the higher throughput data transfer circuit 16.
`For purposes of example, in FIG. 3, the receive free
`pointer 72 and the receive filled pointer 74, in the host
`computer system 20, point to receive ring entry 62b and
`receive ring entry 6211, respectively. The next receive
`pointer 76 in the higher throughput data transfer circuit
`16 points to receive ring entry 62h. Receive ring entries
`with ownership bit equal to 1 (62):, 621', and 620), are
`owned by the network adapter 10. The receive buffer
`address fields of these three entries contain the ad-
`dresses of receive buffers 78, 80, and 82 respectively.
`Those receive ring entries with ownership bit equal to 0
`(62b, 62c, 62d, 62e, 62f, and 62g), are owned by the host
`computer system 20.
`Prior to when the example begins, the host computer
`system 20 has passed the ownership of three receive
`ring entries, 62h, 621’, and 62a, to the network adapter
`10. The events occurring as the network adapter 10
`processes these entries are as follows. The higher
`throughput data transfer circuit 16 reads the ownership
`bit 64 in the receive ring entry pointed to by the next
`receive pointer 76 (receive entry 6211), and determines
`that the network adapter 10 owns the entry. Using the
`
`5
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`10
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`15
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`20
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`25
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`30
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`35
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`45
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`50
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`65
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`6
`receive buffer address field 66 and receive buffer length
`field 68 to locate the receive buffer 78 in host memory
`22, the higher throughput data transfer circuit 16 moves
`a packet from packet memory 18 into the receive buffer
`78. This movement of data requires multiple accesses to
`the system bus 24 by both the host computer system 20
`and the network adapter 10. When the data move com-
`pletes, the higher throughput data transfer circuit 16
`writes the receive completion code 70, and changes the
`ownership of the receive ring entry 62h to 0. It then
`advances the next receive pointer 76 to point to the next
`receive ring entry in sequence (621'). Receive ring
`entries 621' and 620 are then processed similarly. When
`processing of receive ring entries 621' and 62a is com-
`pleted, the next receive pointer 76 points to receive
`entry 62b.
`To provide another receive buffer to the network
`adapter 10, the host computer system 20 uses the re-
`ceive ring entry pointed to by the receive free pointer
`72 (ring entry 62b). The host computer system 20 first
`writes the receive buffer address field 66 and the receive
`buffer length field 68 of the receive entry 62b with the
`address and length of a new receive buffer. It then
`changes the ownership of receive ring entry 62b to l.
`The higher throughput data transfer circuit 16 reads the
`ownership bit 64 of the receive ring entry 62b, deter-
`mines that the network adapter 10 owns it, processes it
`as described above, and sets the next receive pointer to
`point to receive ring entry 622. This process continues,
`with the host computer system 20 providing new re-
`ceive buffers to the network adapter 10, and the higher
`throughput data transfer circuit 16 moving data from
`the packet buffer 18 into the receive buffers.
`FIG. 4 shows the command ring 90, a data structure
`in the host memory 22. The command ring 90 contains
`a fixed number of command ring entries 92a, 92b, .
`.
`.
`,
`92n (in this example, n=1'). Each command ring entry
`920 through 9211 includes an ownership bit 94, a com-
`mand buffer address field 96, a command buffer length
`field 98, and a command completion code field 100. A
`command fill pointer 102, and a command free pointer
`104, exist in the host computer system 20. A next com-
`mand pointer 106, exists in the network adapter 10.
`For purposes of example, in FIG. 4, the command fill
`pointer 102 and the command free pointer 104, point to
`command ring entry 92d and command ring entry 92b,
`respectively. The next command pointer 106 points to
`transmit ring entry 92b. Command ring entries with
`ownership bit equal to 1 (92b and 92c), are owned by the
`network adapter 10. The command buffer address fields
`of these two entries contain the addresses of command
`buffers 108 and 110, respectively. Those command ring
`entries with ownership bit equal to 0 (92a, 92d, 62e, 62f,
`62g, 92):, and 921'), are owned by the host computer
`system 20.
`Prior to when the example begins, the host computer
`system 20 passed the ownership of two command ring
`entries, 92b and 92c, to the network adapter 10. The
`events occurring as the network adapter 10 processes
`these entries are as follows. The adapter management
`subsystem 14 uses the lower throughput data transfer
`circuit 12 to read the ownership bit 94 of the command
`ring entry pointed to by the next command pointer 106
`(command ring entry 92b), and determines the network
`adapter 10 owns the entry. Using the command buffer
`address field 96 and command buffer length field 98 to
`locate the command buffer 108 in host memory 22, the
`adapter management subsystem 14 then uses the lower
`
`DELL Ex.1046.014
`Ex.1046.014
`
`DELL
`
`
`
`5,293,487
`8
`7
`throughput data transfer circuit 12 to read the data in
`mines that the network adapter 10 owns the entry. On
`the command buffer 108. The adapter management
`request from the adapter management subsystem 14, the
`subsystem 14 then processes the command data. After
`lower throughput data transfer circuit 12 moves unso
`processing the command data, the adapter management
`licited data from the adapter management subsystem 14
`subsystem requests the lower throughput data transfer
`into the unsolicited data field 126 of the unsolicited ring
`circuit 12 to write the command results to the command
`entry 122a. This data move is across the system bus 24
`buffer 108, write the command completion code 100 in
`from the network adapter 10 to the host memory 22.
`the command ring entry 92b, and write the ownership
`When the data move completes, the adapter manage
`bit 94 of the command ring entry 92b to 0. The adapter
`ment subsystem 14 uses the lower throughput data
`management subsystem 12 then advances the next com
`transfer circuit 12 to change the ownership bit 124 of
`10
`mand pointer 106 to point to the next command ring
`the unsolicited ring entry 122a to 0. The adapter man
`entry in sequence (92c). Command ring entry 92c is then
`agement subsystem 14 then advances the next unsolic
`processed similarly. After command entry 92c is pro
`ited ring entry pointer 136 to point to the next unsolic
`cessed, the next command pointer points to command
`ited ring entry in sequence (122b). Unsolicited ring
`entry 92d.
`15
`entry 122b is then processed similarly. When processing
`To pass another command buffer to the network
`of unsolicited ring entry 122b completes, the next unso
`adapter 10, the host computer system 20 uses the com
`licited pointer points to unsolicited ring entry 122c.
`mand ring entry pointed to by the command fill pointer
`To process an unsolicited ring entry provided by the
`102 (command ring entry 92d). The host computer
`network adapter 10, the host computer system 20 uses
`system 20 first writes the command buffer address field
`20
`the unsolicited ring entry pointed to by the unsolicited
`96, and the command buffer length field 98, of the com
`ring fill pointer 134 (unsolicited ring entry 122c). The
`mand entry 92d, with the address and length of the new
`host computer system 20 first reads the unsolicited data
`command buffer. It then changes the ownership bit 94
`field 126 in unsolicited ring entry 122c, and then
`of command ring entry 92d to 1. The adapter manage
`changes the ownership bit 124 of unsolicited ring entry
`ment subsystem 14 then uses the lower throughput data
`25
`122c to 1. The adapter management subsystem 14 then
`transfer circuit 12 to read the ownership bit 94 of the
`uses the lower throughput data transfer circuit 12 to
`command ring entry 92d, and detects that the network
`read the ownership bit 124 of the unsolicited ring entry
`adapter 10 owns the command ring entry 92d. The new
`122c, and detects that the network adapter 10 owns it.
`command buffer is then processed as described above.
`On request from the adapter management subsystem 14,
`This process continues, with the host computer system
`30
`the lower throughput data transfer circuit uses the entry
`20 providing new command buffers to the network
`to pass unsolicited data from the adapter management
`adapter 10, the adapter management subsystem 14 using
`subsystem 14 to the host computer system 20. This
`the lower throughput data transfer circuit 12 to read the
`process continues, with the host computer system 20
`command entries and the command buffers, the adapter
`processing new unsolicited ring entries as they are pro
`management subsystem 14 then processing the com
`35
`vided by the network adapter 10.
`mand buffers, and finally using the lower throughput
`FIG. 6 shows the elements of FIG. 1, as well as the
`data transfer circuit 12 to write back the command
`transmit ring 30, the receive ring 60, the command ring
`results, and return the ownership of the command ring
`90, and the unsolicited ring 120. The higher throughput
`entry and command buffer to the host computer system
`data transfer circuit 16 is logically coupled (shown with
`20.
`dotted lines) to the transmit ring 30 and receive ring 60.
`FIG. 5 shows the unsolicited ring 120, a data struc
`The lower throughput data transfer circuit 12 is logi
`ture in the host memory 22. The unsolicited ring 120
`cally coupled (again shown with dotted lines) to the
`contains a fixed number of unsolicited ring entries 122a,
`command ring 90 and the unsolicited ring 120.
`122b, ..., 122n (in this example, n=i). Each unsolicited
`. Operation of the elements shown in FIG. 6 is now
`ring entry 122a through 122m includes an ownership bit
`described. The network adapter 10 stores packets re
`124, and an unsolicited data field 126. An unsolicited fill
`ceived from the network 26 in packet memory 18. The
`pointer 134 exists in the host computer system 20. A
`higher throughput data transfer circuit 16 then moves
`next unsolicited pointer 136, exists in the network
`the packets into memory buffers in host memory 22
`adapter 10.
`whose addresses are contained in receive ring entries in
`For purposes of example, in FIG. 5, the unsolicited
`the receive ring 60.
`fill pointer 134 in the host computer system 20 points to
`To transmit packets onto the network 26, the host
`unsolicited ring entry 122a. The unsolicited next pointer
`computer system 20 writes the addresses of transmit
`136 in the network adapter 10 points to unsolicited ring
`buffers containing packets to be transmitted onto the
`entry 122a. Unsolicited ring entries with ownership bit
`network 26 in transmit ring entries in the transmit ring
`equal to 1 (122a and 122b), are owned by the network
`55
`30. The higher throughput data transfer circuit 16 then
`adapter 10. Those unsolicited ring entries with owner
`moves the packets into the packet memory 18, from
`ship bit equal to 0 (122c, 122d, 122e, 122?, 122g, 122h,
`which they are subsequently transmitted onto the net
`and 122i), are owned by the host computer system 20.
`Prior to when the example begins, the network
`work 26.
`To issue commands to the network adapter 10, the
`adapter has passed the ownership of seven unsolicited
`host computer system 20 writes the addresses of com
`ring entries, 122c, 122d, 122e, 122?, 122g, 122h, and 122i,
`to the host computer system 20. The events occurring
`mand buffers containing command data to command
`as the network adapter 10 processes the two remaining
`ring entries on the command ring 60. The lower
`throughput data transfer circuit 12 reads the co
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