Approved for use through‘iO/31/2002. OMB 0651—0032
`U.S. Patent and Trademark Office; U.S. DEPARTMENT OF COMMERCE
`.Under the Paperwork Reduction Act of 1995, no persons are required to respond to a collection of information unless it displays a valid OMB control number.
`
`Lt?“ 0' gL/O
`
`flaw
`PTO/SB/iGfi-Ot
`
`PROVISIONAL APPLICATION FOR PATENT COVER SHEET
`
`This is a re uest for filin- a PROVISIONAL APPLICATION FOR PAI'ENT under 37 CFR 1.53 c .
`
`30X37/
`
` 'S'nTSOTF
`ZU/ZB/IUllllllllllllllllllllllllllllllllllllll
`
`
`
`Express Mail Label No.
`
`E L“) &,8 $4 8 q 4 O U S
`
`INVENTOR(S)
`
`Given Name (first and middle [if any])
`
`Family Name or Surname
`
`Residence
`(City and either State or Foreign Country)
`
`
`
`Colin
`. Clive,
`E Additional inventors are being named on the A.
`
`P
`
`San TosejCoilitomia.
`San Sosa CRII‘HW'AIOL
`separately numbered sheets attached hereto
`
`TITLE OF THE INVENTION (500 characters max)
`
`TC P/I P Ofiloqd Device:
`
`Direct all correspondence to:
`CORRESPONDENCE ADDRESS
`mm C: —»
`Type Customer Number here
`OR
`
`Bar Code Label here
`.
`
`.
`T Le S'I'Ef’ WQ I I Q Ca
`ESE/Shel Name
`’13
`704 KOI
`CQVI‘I'CF I) rkWoL
`Address
`SUI'I'e. 180
`I.
`4
`Address
`City mm- 4 666
`Count
`m—I-mam- ', Ara—061
`ENCLOSED APPLICATION PARTS (check all that apply)
`
`12
`
`territorial.)
`(“MIMI/IS
`Drawing(s) Number of Sheets LEI
`I:I Application Data Sheet. See 37 CFR 1.76
`
`cw...
`Other (specify)
`
`-ccw+Cowa>
`‘
`.
`
`,
`
`Applicant claims small entity status. See 37 CFR 1.27.
`.—..
`A check or money order is enclosed to cover the filing fees
`The Commissioner is hereby authorized to charge filing
`fees or credit any overpayment to Deposit Account Number:
`Payment by credit card. Form PTO-2038 is attached.
`
`FILING FEE
`AMOUNT ($)
`
`I Q 0. 00
`
`The invention was made by an agency of the United States Government or under a contract with an agency of the
`United States Government.
`No.
`
`I: Yes, the name ofthe U.S. Government agency and the Government contract number are:
`
`
`[ be
`I
`I
`[
`Respectfully submitted,
`SIGNATURE
`TYPED or PRINTED NAME Le SICK w“ I I0. ce-
`——_————
`ALA OOI PROV
`TELEPHONE
`qag Afig—G‘fl Q3
`‘
`USE ONLYFOR FILING A PROVISIONAL APPLICATION FOR PATENT
`This collection of information is required by 37 CFR 1.51. The information is used by the public to file (and by the PTO to process) a
`provisional application. Confidentiality is governed by 35 U.S.C. 122 and 37 CFR 1.14. This collection is estimated to take 8 hours to
`complete. including athering. preparin , and submitting the complete provisional a plication to the PTO. Time will vary depending upon
`the individual case. ny comments on t e amount of time you require to complete t
`IS form and/or suggestions for reducing this burden,
`should be sent to the Chief Information Officer. U.S. Patent and Trademark Office, U.S. Department of Commerce, Washington, D.C.
`20231. DO NOT SEND FEES OR COMPLETED FORMS TO THIS ADDRESS. SEND TO: Box Provisional Application, Assistant
`Commissioner for Patents, Washington, D.C. 20231.
`
`Date
`REGISTRATION NO.
`(if appropriate)
`DOCket Number:
`
`34 74 8
`
`DELL Ex.1045.001
`Ex.1045.001
`
`DELL
`
`

`

`PROVISIONAL APPLICATION COVER SHEET
`Additional Page
`
`PTO/SB/16 (02-01)
`Approved for use through 10/31/2002. OMB 0651-0032
`U.S. Patent and Trademark Office; U.S. DEPARTMENT OF COMMERCE
`Under the Paperwork Reduction Act of 1995, no persons are required to res 0nd to a collection of information unless it disola s a valid OMB control number.
`
`
`|NVENTOR(S)IAPPLICANT(S)
`m—m
`Given Name first and middle if an
`Famil or Surname
`Cit and either State or Foreion Count
`>
`
`EangSAsMo us
`
`Mllpl'l'qs) quncor‘mm
`
`San Jose , Ca lfifom Fat
`
`
`
`
`
`
`
`
`
`Daryl
`
`$16 Phen
`
`
`
`Number C9\
`
`of
`
`<1
`
`WARNING: Information on this form may become public. Credit cardl information should not be
`included on this form. Provide credit card information and authorization on PTO—2038.
`
`DELL Ex.1045.002
`Ex.1045.002
`
`DELL
`
`

`

`COMPACT DISC TRANSMITTAL LETTER
`
`(under 37 CFR 1.52(e)3(ii))
`
`Title: “TCP/IP Offload Device”
`
`Alacritech, Inc.
`Assignee:
`Sharp, et al.
`Inventors:
`Filing Date: April 22, 2002
`Atty Docket: ALA—l 00—PROV
`
`TO THE ASSISTANT COMMISSIONER FOR PATENTS:
`
`Sir:
`
`Transmitted herewith are:
`
`Two Labeled Compact Discs — Recordable (CD—R) — “Copy 1” and “Copy 2”,
`each in a CD case and contained in a padded envelope.
`
` The content on the two discs is identical. The machine format is: HBM—PC. The operating
`
`system is: MS—Windows. The creation date of the CDs is: April 201 2002. The name, date and
`size of the files on the CDs are listed below:
`
`
`
`There are three folders on each disc: 1) CD Appendix A, 2) CD Appendix B, and 3) CD
`Appendix C. There is also a file entitled “Title Pagetxt” Its size is 280 bytes. It was created
`(written to disc) 04/20/02.
`
`Folder CD Appendix A contains: 1) a folder entitled “Mojave microcode” (Its size is 892KB. It
`was created (written to disc) 04/20/02); and 2) a folder entitled ”Mojave verilog code” (Its size is
`1.56 MB. It was created (written to disc) 04/20/02).
`
`Folder CD Appendix B contains: 1) a folder entitled “atcp (free BSD stack and code added to
`it)” (Its size is 1.62 MB. It was created (written to disc) 04/20/02; 2) a folder entitled “include
`(set of files shared by ATCP and device driver)” (Its size is 137 KB. It was created (written to
`disc) 04/20/02; and 3) a folder entitled “simba (device driver software for Mojave)” (Its size is
`16.8 MB. It was created (written to disc) 04/20/02).
`
`Folder CD Appendix C contains: 1) a file entitled “mojave_rcv_seq(instruction set
`description).mdl” (Its size is 25.0 KB.
`It was created (written to disc) 04/20/02; and 2) a file
`entitled “mojave_rcv_seq(program executed by receive processor).mal” (Its size is 83.2 KB. It
`was created (written to disc) 04/20/02).
`
`I hereby certify that this correspondence is being deposited
`with the United States Postal Service as “Express Mail Post
`Office to Addressee” addressed to Box Provisional
`
`Application, Assistant Commissioner for Patents,
`Washington, DC. 20231, on April 22, 2002, as
`
`Express Mail No. EL928548940US.
`
`T. Lester Wallace
`
`Lw flgm
`
`Signature
`
`Egg“ 293001
`
`D te of Signature
`
`
`
`
`
`Respectfufly su bmitteda
`'
`
`(9
`3
`
`'
`
`T_ Lester Wauace
`
`Attorney fOI' Applicants
`Reg. No. 34,748
`
`DELL Ex.1045.003
`Ex.1045.003
`
`DELL
`
`

`

`ALA— l O O — PROV
`
`PATENT
`
`This correspondence is being deposited with the United States Postai Service as Express Mail addressed
`to: Box PROVISIONAL Application, Assistant Commissioner for Patents, Washington, D. C. 20231, on
`Apcil an ggog
`,Express Mail Receipt No. EL928548940US.
`
`TCP/IP OFFLOAD DEVICE
`
`Colin Sharp
`
`Clive M. Philbrick
`
`Daryl D. Starr
`
`Stephen E]. Blightman
`
`
`
`CROSS-REFERENCE TO COMPACT DISC APPENDIX
`
`[0 0 0 l] The Compact Disc Appendix, which is a part of the present disclosure, includes
`
`a recordable Compact Disc (CD—R) containing information that is part of the disclosure
`
`of the present patent document. A portion of the disclosure of this patent document
`
`contains material that is subject to copyright protection. All the material on the Compact
`
`Disc is hereby expressly incorporated by reference into the present application. The
`
`copyright owner of that material has no objection to the facsimile reproduction by anyone
`
`of the patent document or the patent disclosure, as it appears in the Patent and Trademark
`
`Office patent files or records, but otherwise reserves all copyright rights.
`
`TABLE OF CONTENTS
`
`[0 0 0 2] This provisional patent application document includes the following parts:
`
`[0 0 0 3] l) Cross-Reference To Compact Disc Appendix.
`
`[0 0 04] 2) The Compact Disc Appendix (the disc referred to in the “Cross-Reference To
`
`Compact Disc Appendix” section).
`
`[0 0 0 5] 3) Brief Description Of The Drawings.
`
`[0 0 0 6] 4) Detailed Description.
`
`[0 0 07] 5) Mojave Hardware Specification (including figures).
`
`[0 0 0 8] 6) PCT Redaction Publication (including figures).
`
`1
`
`DELL Ex.1045.004
`Ex.1045.004
`
`DELL
`
`

`

`ALA- l O O — PROV
`
`PATENT
`
`[0 0 O 9] 7) US. Patent Application Serial No. 09/416,925, entitled “Queue System For
`
`Microprocessors”, filed October 13, 1999 (including figures) [atty. docket ALA-005].
`
`[0 0 1 0] 8) US. Patent Application Serial No. 09/3 84,792, entitled “Intelligent Network
`
`Interface Device And System For Accelerated Communication”, filed August 27, 1999
`
`(including figures) [atty. docket ALA-008].
`
`[0 011] 9) US. Patent Application Serial No. 09/801 ,488, entitled “Port Aggregation
`
`For Network Connections That Are Offloaded To Network Interface Devices”, filed
`
`March 7, 2001 (including figures) [atty. docket ALA—01 1].
`
`[0 012] 10) US. Patent Application Serial No. 10/085,802, entitled “TCP/1P Offload
`
`Device With Fast-Path TCP ACK Generating And Transmitting Mechanism”, filed
`
`February 26, 2002 (including figures) [atty. docket ALA-019].
`
`[0 013] 1 1) US. Patent Application Serial No. 09/970,124, entitled “Network Interface
`
`Device That Fast—Path Processes Solicited Session Layer Read Commands”, filed
`
`October 2, 2001 (including figures) [atty. docket ALA—020].
`
`[0 014] 12) US. Patent No. 6,247,060 (including figures).
`
`[ 0 015] 13) US. Patent No. 6,226,680 (including figures).
`
`[0 0 1 6] 14) Published US. Patent Application No. 20010021949 (including figures).
`
`[0 0 17] 15) Published US. Patent Application No. 20010047433 (including figures).
`
`[0 0 1 8] 16) Claims (the claims for the present provisional patent document).
`[0 0 1 9] 17) Abstract (the abstract for the present provisional patent document).
`
`[0 02 O] 18) Figures (the figures for the present provisional patent document).
`
`[0 02 1] In the realization of different embodiments, the techniques, methods, and
`
`structures set forth in parts 6—15 are applied to the system, and/or to the network interface
`
`device (NID), and/or to the application specific integrated circuit (ASIC) set forth in the
`
`text below and in the associated figures.
`
`
`
`DELL Ex.1045.005
`Ex.1045.005
`
`DELL
`
`

`

`
`
`
`
`ALA-lOO-PROV
`
`PATENT
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0 022] The present invention is illustrated by way of example and not limitation in the
`
`figures of the accompanying drawings, in which:
`
`[0023] Figure l is a diagram of a system 1 in accordance with one embodiment of the
`
`present invention.
`
`[0 02 4] Figure 2 is a simplified diagram of various structures and steps involved in the
`
`processing of an incoming packet in accordance with an embodiment of the present
`
`invention.
`
`[0025] Figure 3 is a flowchart of a method in accordance with an embodiment of the
`
`present invention.
`
`[002 6] Figures 4, 5, 6, 7, 8 and 9 are diagrams that illustrate various system
`
`configurations involving a network interface device in accordance with the present
`
`invention.
`
`DETAILED DESCRIPTION
`
`[0027] Figure l is a simplified diagram of a system 1 in accordance with a first
`
`embodiment. System 1 is coupled to a packet-switched network 2. Network 2 can, for
`
`example, be a local area network (LAN) and/or a collection of networks. Network 2 can,
`
`for example, be the Internet. Network 2 can, for example, be an IP—based SAN that runs
`iSCSI. Network 2 may, for example, be coupled to system 1 Via' media that
`-
`communicates electrical signals, via fiber optic cables, and/or via a wireless
`
`communication channel. System 1 includes a network interface device (NID) 3 as well
`
`as a central processing unit (CPU) 4. CPU 4 executes software stored in storage 5. NID
`
`3 is coupled to CPU 4 and storage 5 via host bus 6, a bridge 7, and local bus 8. Host bus
`
`6 may, for example, be a PCI bus or another computer expansion bus.
`
`[0 02 8] In the illustrated particular embodiment, NID 3 includes an application specific
`
`integrated circuit (ASIC) 9, an amount of dynamic random access memory (DRAM) 10,
`
`and Physical Layer Interface (PHY) circuitry 11. NID 3 includes specialized protocol
`
`accelerating hardware for implementing “fast—path” processing whereby certain types of
`
`3
`
`DELL Ex.1045.006
`Ex.1045.006
`
`DELL
`
`

`

`
`
`ALA-lOO-PROV
`
`'
`
`PATENT
`
`network communications are accelerated in comparison to “slow-path” processing
`
`whereby the remaining types of network communications are handled at least in part by a
`
`software protocol processing stack. In one embodiment, the certain types of network
`
`communications accelerated are TCP/1P communications. The embodiment of NID 3
`
`illustrated in Figure l is therefore sometimes called a TCP/IP Offload Engine (TOE).
`
`[0 02 9] For additional information on examples of a network interface device
`
`(sometimes called an Intelligent Network Interface Card or “INIC”), see: US. Patent No.
`
`6,247,060; US. Patent No. 6,226,680; Published US. Patent Application No.
`
`20010021949; Published US. Patent Application No. 20010027496; and Published US.
`Patent Application No. 20010047433. System 1 of Figure 1 employs techniques set forth
`
`in these documents for transferring control of TCP/IP connections between a protocol
`
`processing stack and a network interface device.
`
`[0030] ND 3 includes Media Access Control circuitry 12, three processors 13-15, a
`
`pair of Content Addressable Memories (CAMS) 16 and 17, an amount of Static Random
`
`Access Memory (SRAM) 18, queue manager circuitry 19, a receive processor 20, and a
`
`transmit sequencer 21. Receive processor 20 executes codestored its own control store
`
`22.
`
`[0031] In some embodiments Where NID 3 fully offloads or substantially fully offloads
`CPU 4 of the task of performing TCP/IP protocol processing, NID 3 includes a processor
`
`23. Processor 23 may, for example, be a general purpose microprocessor. Processor 23
`
`performs slow-path processing such as TCP error condition handling and exception
`
`condition handling. In some embodiments, processor 23 also performs higher layer
`
`protocol processing such as, for example, iSCSI layer protocol processing such that NID
`
`3 offloads CPU 4 of all iSCSI protocol processing tasks. In the example of Figure 1,
`
`CPU 4 executes code that implements a file system, and processor 23 executes code that
`
`implements a protocol processing stack that includes an iSCSI protocol processing layer.
`
`Overview of One Embodiment Of A Fast—Path Receive Path:
`
`[0032 ] Operation of NID 3 is now described in connection with the receipt onto NID 3
`
`of a TCP/IP packet from network 2. DRAM 10 is initially partitioned to include a
`
`4
`
`DELL Ex.1045.007
`Ex.1045.007
`
`DELL
`
`

`

`
`
`ALA-lOO-PROV
`
`PATENT
`
`plurality of buffers. Receive processor 20 uses the buffers in DRAM 10 to store
`
`incoming network packet data as well as status information for the packet. For each
`
`bufler, a 32-bit buffer descriptor is created. Each 32-bit buffer descriptor indicates the
`
`size of the associated buffer and the location in DRAM‘of the associated buffer. The
`
`location is indicated by a 19-bit pointer.
`
`[O 033] At start time, the buffer descriptors for the fee buffers are pushed onto on a
`
`“free—buffer queue” 24. This is accomplished by writing thebuffer descriptors to queue
`
`manager 19. Queue manager 19 maintains multiple queues including the “free-buffer
`
`queue” 24. In this implementation, the heads and tails'of the various queues are located
`
`in SRAM 18, whereas the middle portion of the queues are located in DRAM 10.
`
`[0034] The TCP/IP packet is received from the network 2 Via Physical Layer Interface
`(PHY) circuitry 11 and MAC circuitry 12. As the MAC circuitry 12 processes the
`
`packet, the MAC circuitry 12 verifies checksurns in the packet and generates “status”
`
`information. After all the packet data has been received, the MAC circuitry 12 generates
`
`“final packet status” (MAC packet status). The status information (also called “protocol
`
`analyzer status”) and the MAC packet status information is then transferred to a free one
`
`of the DRAM buffers obtained from the free-buffer queue 24. The status information and
`
`MAC packet status information is stored prepended to the associated data in the buffer.
`
`[0035] After all packet data has been transferred to the free DRAM buffer, receive
`
`processor 20 pushes a “receive packet descriptor” (also called a “summary”) onto a
`
`“receive packet descriptor” queue 25. The “receive packet descriptor” includes a 14-bit
`hash value, the buffer descriptor, a buffer load—count, the'MAC ID, and a status bit (also
`called an “attention bit”). The 14-bit hash value was previously generated by the receive
`
`processor 20 (from the TCP and IP source and destination addresses) as the packet was
`
`received. If the “attention bit” of the receive packet descriptor is a one, then the packet is
`
`not a “fast-path candidate”; whereas if the attention bit is a zero, then the packet is a
`
`“fast-path candidate’ . In the present example of a TCP/IP offload engine, the attention
`
`bit being a zero indicates that the packet employs both the TCP protocol and the IP
`
`protocol.
`
`[003 6] Once the “receive packet descriptor” (including the buffer descriptOr that points
`
`to the DRAM buffer where the data is stored) has been placed in the “receive packet
`
`5
`
`DELL Ex.1045.008
`Ex.1045.008
`
`DELL
`
`

`

`
`
`ALA—lOO-PROV
`
`PATENT
`
`descriptor” queue 25 and the packet data has been placed in the associated DRAM buffer,
`
`one of the processors 13 and 14 can retrieve the “receive packet descriptor” from the
`
`“receive packet descriptor” queue 25 and examine the “attention bit”.
`
`[0 037] If the attention bit is a digital one, then the processor determines that the packet
`
`is not a “fast-path candidate” and the packet is handled in “slow—path”. In one
`
`embodiment where the packet is a TCP/IP packet, wherein the attention bit indicates the
`packet is not a “fast-path candidate”, and where NIB 3 performs full offload TCP/IP
`
`functions, general purpose processor 23 performs further protocol processing on the
`
`packet (headers and data). In another embodiment where there is no general purpose
`
`processor 23 and where NID 3 performs partial TCP/1P functions, the entire packet
`
`(headers and data) are transferred from the DRAM buffer and across host bus 6 such that
`
`CPU 4 performs further protocol processing on the packet.
`
`[O 038] If, on the other hand, the attention bit is a zero, then the processor determines
`
`that the packet is a “fast-path candidate”. If the’processor determines that the packet is a
`
`“fast—path candidate”, then the processor uses the buffer descriptor from the “receive
`
`packet descriptor” to initiate a DMA transfer the first approximately 96 bytes of
`
`information from the pointed to buffer in DRAM 10 into a portion of SRAM 18 so that
`
`the processor can examine it. This first approximately 96 bytes contains the IP source
`
`address of the IP header, the IP destination address of the IP header, the TCP source
`
`address (“TCP source port”) of the TCP header, and the TCP destination address (“TCP
`destination port”) of the TCP header. The IP source address of the IP header, the IP
`
`destination address of the IP header, the TCP source address of the TCP header, and the
`TCP destination address ofthe TCP header together uniquely define a single “connection
`
`context” with which the packet is associated.
`
`[0039] While this DMA transfer from DRAM to SRAM is occurring, the processor uses
`
`the 14-bit hash fiom the “receive packet descriptor” to identify the connection context of
`
`thepacket and to determine whether the. connection context is one of a plurality of
`
`connection contexts that are under the control of NID 3. The hash points to one hash
`
`bucket in a hash table 104 in SRAM 18. In the diagram of Figure 1, each row of the hash
`
`table 104 is a hash bucket. Each hash bucket contains one or more hash table entries. If
`
`the hash identifies a hash bucket having more than one hash table entry (as set forth
`
`6
`
`DELL Ex.1045.009
`Ex.1045.009
`
`DELL
`
`

`

`
`
`ALA—lOO—PROV
`
`PATENT
`
`below in filrther detail), then the processor attempts to match the IP source address, IP
`
`destination address, TCP source address (port), and TCP destination address (port)
`
`retrieved from DRAM with the same fields, i.e., the IP source address, IP destination
`
`address, TCP source port, and TCP destination port of each hash table entry. The hash
`
`table entries in the hash bucket are searched one by one in this manner until the processor
`
`finds a match. When the processor finds a matching hash table entry, a number stored in
`
`the hash table entry (called a “transmit control block number ” or “TCB number”)
`
`identifies a block of information (called a TCB) related to the connection context of the
`
`packet. There is one TCB maintained on NID 3 for each connection context under the
`
`control of NID 3.
`
`[O 04 0] If the connection context is determined not to be one of the contexts under the
`
`control of NID 3, then the “fast-path candidate” packet is determined not to be an actual
`
`“fast-path packet.” In one embodiment where NID 3 includes general purpose processor
`
`23 and where NID 3 performs full TCP/1P offload functions, processor 23 performs
`
`further TCP/IP protocol processing on the packet. In another embodiment where NID 3
`performs partial TCP/1P offload functions, the entire packet (headers and data) is
`transferred across host bus 6 for further TCP/IP protocol processing by the sequential
`
`protocol processing stack of CPU 4.
`
`[0 O 41] If, on the other hand, the connection context is one of the connection contexts
`
`under control of NID 3, then software executed by the processor (1 3 or 14) checks for
`
`one of numerous exception conditions and determines whether the packet is a “fast-path
`
`packet” or is not a “fast—path packet”. These exception conditions include: 1) IP'
`
`fragmentation is detected; 2) an IP option is detected; 3) an unexpected TCP flag (urgent
`
`bit set, reset bit set, SYN bit set or FIN bit set) is detected; 4) the ACK field in the TCP
`
`header shrinks the TCP window; 5) the ACK field in the TCP header is a duplicate ACK
`
`and the ACK field exceeds the duplicate ACK connt (the duplicate ACK count is a user
`
`settable value); and 6) the sequence number of the TCP header is out of order (packet is
`
`received out of sequence).
`
`[0 042 ] If the software executed by the processor (13 or 14) detects an exception
`
`condition, then the processor determines that the “fast-path candidate” is not a “fast-path
`
`packet.” In such a case, the connection context for the packet is “flushed” (control of the
`
`7
`
`DELL Ex.1045.010
`Ex.1045.010
`
`DELL
`
`

`

`
`
`ALA-lOO-PROV
`
`PATENT _
`
`connection context is passed back to the stack) so that the connection context is no longer
`
`present in the list of connection contexts under control of NID 3. If NID 3 is a full
`
`TCP/IP offload device including general purpose processor 23, then general purpose
`
`processor 23 performs further TCP/1P processing on the packet. In other embodiments
`
`where NID 3 performs partial TCP/1P offload functions and NID 3 includes no general
`
`purpose processor 23, the entire packet (headers and data) is transferred across host bus 6
`
`to CPU 4 for further “slow-path” protocol processing.
`
`[0043] If, on the other hand, the processor (13 or 14) finds no such exception condition,
`
`then the “fast-path candidate” packet is determined to be an actual “fast—path packet”.
`
`The processor executes a software state machine such that the packet is processed in
`
`accordance with the IP and TCP protocols. The data portion of the packet is then DMA
`transferred to a destination identified by another device or processor. In the present
`
`example, the destination is located in storage 5 and the destination is identified by a file
`
`system controlled by CPU 4. CPU 4 does no or very little analysis of the TCP and IP
`
`headers on this “fast-path packet”. All or substantially all analysis of the TCP and IP
`
`headers of the “fast-path packet” is done on NID 3.
`
`Description Of A TCB Lookup Method:
`
`[0044] As set forth above, information for each connection context under the control of
`
`NID 3 is stored in a block called a “Transmit Control Block” (TCB). An incoming
`
`packet is analyzed to determine whether it is associated with a connection context that is
`
`under the control of NID 3. If the packet is associated with a connection context under
`
`the control of NID 3, then a TCB lookup method is employed to find the TCB for the
`
`connection context. This lookup method is described in further detail in connection with
`
`Figures 2 and 3.
`
`[00451NID 3 is a multi-receive processor network interface device. In NID 3, up to
`
`sixteen different incoming packets can be in process at the same time by two processors
`
`13 and 14. (Processor 15 is a utility processor, but each of processors 13 and 14 can
`
`perform receive processing or transmit processing.) A processor executes a software
`
`state machine to process the packet. As the packet is processed, the state machine
`
`8
`
`DELL Ex.1045.011
`Ex.1045.011
`
`DELL
`
`

`

`
`
`ALA—lOO—PROV
`
`PATENT
`
`transitions from state to state. One of the processors, for example processor 13, can work
`
`on one of the packets being received until it reaches a stopping point. Processor 13 then
`
`stops work and stores the state of the software state machine. This stored state is called a
`
`“processor context”. Then, at some later time, either the same processor 13 or the other
`
`processor 14 may resume processing on the packet. In the case where the other processor
`
`14 resumes processing, processor 14 retrieves the prior state of the state machine fiom
`
`the previous “processor contex ”, loads this state information into its software state
`
`machine, and then continues processing the packet through the state machine fiom that
`
`point. In this way, up to sixteen different flows can be processed by the two processors
`
`13 and 14 working in concert.
`
`[004 6] In this example, the TCB lookup method starts after the TCP packet has been
`
`received, after the 14-bit hash and the attention bit has been generated, and after the hash
`
`and attention bit have been pushed in the form of a “receive packet descriptor” onto the
`
`“receive packet descriptor queue”.
`
`, [0047] In a first step (step 200), one of processors 13 or 14 obtains an available
`
`“processor context”. The processor pops (step 201) the “receive packet descriptor” queue
`
`25 to obtain the “receive packet descriptor”. The “receive packet descriptor” contains the
`
`previously—described 14-bit hash value 101 (see Figure 2) and the previously-described
`
`attention bit. The processor checks the attention bit.
`
`[0048] If the attention bit is set (step 202), then processing proceeds to slow-path
`
`processing. As set forth above, if NID 3 is a TCP/IP filll-offload device and if the packet
`
`is a TCP/IP packet, then further TCP/1P processing is performed by general purpose
`
`processor 23. As set forth above, if NID 3 is a TCP/IP partial offload device, then the
`
`packet is sent across host bus 6 for further protocOl processing by CPU 4.
`
`[0 04 9] If, on the other hand, the attention bit is not set (step 203), then the processor
`
`initiates a DMA transfer ofthe beginning part of the packet (including the header) fiom
`
`the identified buffer in DRAM 10 to SRAM 18. 14-bit hash value 101 (see Figure 2)
`
`actually comprises a 12-bit hash value 102 and another two bits 103. The 12-bit hash
`value (bits[13:2]) identifies an associated one of4096 possible 64-byte hash buckets. In
`this embodiment, up to 48 of these hash buckets can be cached in SRAM in a hash table
`
`104, whereas any additional used hash buckets 105 are stored in DRAM 10.
`
`.
`
`I
`
`9
`
`.
`
`DELL Ex.1045.012
`Ex.1045.012
`
`DELL
`
`

`

`
`
`ALA-lOO-PROV
`
`PATENT
`
`Accordingly, if the hash bucket identified by the 12—bit hash value is in DRAM 10, then
`
`the hash bucket is copied (or moved) from DRAM 10 to an available row in hash table
`
`104. To facilitate this, there is a hash byte (SRAM_hashbt) provided in SRAM for each
`
`of the possible 4096 hash buckets. A six-bit pointer field in the hash byte indicates
`
`whether the associated hash bucket is located in SRAM or not. If the pointer field
`
`contains a number between 1 and 48, then the pointer indicates the row of hash table 104
`
`where the hash bucket is found. If the pointer field contains the number zero, then the
`
`hash bucket is not in hash table 104 but rather is in DRAM. The processor uses the 12-
`
`bit hash value 102 to check the associated hash byte to see if the pointed to hash bucket is
`
`in the SRAM hash table 104 (step 204).
`
`[0 050] If the hash bucket is in the SRAM hash table 104 (step 205), then processing is
`
`suspended until the DMA transfer of the header from DRAM to SRAM is complete.
`
`[0 051] If, on the other hand, the hash bucket is not in the SRAM hash table 104 (step
`
`206), then a queue (Q_FREEHASHSLOTS) identifying free rows in hash table 104 is
`
`accessed (the queue is maintained by queue manager 19) and a fiee hash bucket row
`
`(sometimes called a “slot’) is obtained. The processor then causes the hash bucket to be
`
`copied or moved from DRAM and into the free hash bucket row. Once the hash bucket is
`
`present in SRAM hash table 104, the processor updates the pointer field in the associated
`
`hash byte to indicate that the hash bucket is now in SRAM and is located at the row now
`
`containing the hash bucket.
`
`[0 052] Once the pointed to hash bucket is in SRAM hash table 104, the up to four
`
`possible hash bucket entries in the hash bucket are searched one by one (step 207) to
`
`identify if the TCP and IP fields of an entry match the TCP and IP fields of the packet
`
`header 106 (the TCP and IP fields from the packet header were obtained from the receive
`
`descriptor).
`
`[0 053] In the example of Figure 2, the pointed to hash bucket contains two hash entries.
`
`The hash entries are checked one by one. The two bits 103 Bits[1:0] of the 14—bit hash
`
`are used to determine which of the four possible hash table entry rows (i.e., slots) to
`check first. In Figure 2, the second hash entry 107 (shown in exploded View) is
`
`representative of the other hash table entries. It includes a 16-bit TCB# 108, a 32-bit IP
`
`10
`
`DELL Ex.1045.013
`Ex.1045.013
`
`DELL
`
`

`

`
`
`ALA—lOO-PROV
`
`PATENT
`
`destination address, a 32-bit IP source address, a 16—bit TCP destination port, and a 16-bit
`
`TCP source port.
`
`[0 05 4] If all of the entries in the hash bucket are searched and a match is not found
`
`(step 208), then processing proceeds by the slow—path. If, on the other hand, a match is
`
`found (step 209), thenthe TCB# portion 108 of the matching entry identifies the TCB of
`
`the connection context.
`
`[0 055] NID 3 supports both fast—path receive processing as well as fast—path transmit
`
`processing. A TCP/IP connection can involve bidirectional communications in that
`
`packets might be transmitted out of NID 3 on the same TCP/1P connection that other
`
`packets flow into NID 3. A mechanism is provided so that the context for a connection
`
`can be “locked” by one processor (for example, a processor receiving a packet on the
`
`TCP/IP connection) so that the another processor (for example, a processor transmitting a
`
`packet on the same TCP/1P connection) will not interfere with the connection context.
`
`This mechanism includes two bits for each of the up to 8192 connections that can be
`
`controlled by NID 3: 1) a “TCB lock bit” (SRAM_tcblock), and 2) a ”TCB'in-use bit”
`
`(SRAM_tcbinuse). The “TCB lock bits” 109 and the “TCB in-use bits” 110 are
`
`maintained in SRAM 18.
`
`[0 05 6] The processor attempts to lock the designated TCB (step 210) by attempting to
`
`set the TCB’s lock bit. If the lock bit indicates that the TCB is already locked, then the
`
`processor context number (a 4-bit number) is pushed onto a linked list of waiting ‘
`
`processor contexts for that TCB. Because there are sixteen possible processor contexts, a
`
`lock table 112 is maintained in SRAM 18. There is one row in lock table 112 for each of
`
`the sixteen possible processor contexts. Each row has sixteen four-bit fields. Each field
`can contain the 4-bit processor context number for a waiting processor context. Each row
`
`of the lock table 112 is sixteen entries wide because all sixteen processor contexts may be
`
`working on or waiting for the same TCB.
`
`[005 7] If the lock bit indicatesthat the TCB is already locked (step 21 1), then the
`
`processor context number (a four-bit number because there can be up to sixteen processor
`
`contexts) is pushed onto the row of the lock table 112 associated with the TCB. A lock
`
`table content addressable memory (CAM) 111 is used to translate the TCB number (from
`
`_ TCB field 108) into the row number in lock table 112 Where the linked list for that TCB
`
`11
`
`DELL Ex.1045.014
`Ex.1045.014
`
`DELL
`
`

`

`
`
`ALA— l O 0 - PROV
`
`PATENT
`
`number is found. Accordingly, lock table CAM 111 receives a sixteen—bit TCB number
`
`and outputs a four-bit row number. When the processor context that has the TCB. locked
`is ready to suspend itself, it consults the lock table CAM 111 and the associated lock
`
`table 112 to determine if there is another processor context waiting for the TCB. If there
`
`is another processor c