`Petersen et al.
`
`[54]
`
`[75]
`
`[73]
`
`[21]
`[22]
`[51]
`[52]
`[58]
`
`[56]
`
`APPARATUS FOR AUTOMATIC
`INITIATION OF DATA TRANSMISSION
`Inventors: Brian Petersen, Los Altos; David R.
`Brown, San Jose; W. Paul Sherer,
`Sunnyvale, all of Calif.
`Assignee: 3Com Corporation, Santa Clara,
`Calif.
`Appl. No.: 920,893
`Filed:
`Jul. 28, 1992
`Int. Cl." ................... H04L 12/413; H04L 25/36;
`G06F 13/00
`U.S. Cl. ............................ 371/57.1; 364/DIG. 1;
`364/239.51; 370/85.3; 395/200; 395/250
`Field of Search ............... 371/57.1; 395/250, 200;
`364/239.51; 370/85.1, 85.15, 85.3
`References Cited
`U.S. PATENT DOCUMENTS
`Heath .................................. 395/250
`4,258,418 3/1981
`Koch et al. .....
`. 370/35.13
`4,715,030 12/1987
`Bentley et al. ......
`... 395/250
`4,860,193 8/1989
`Firoozmand et al.
`370/85.1
`5,043,981 8/1991
`.... 371/3
`Tarrab et al. ...
`5,195,093 3/1993
`370/85.1
`Firoozmand .......................
`5,210,749 5/1993
`
`||||||||||||||||||||||||||||||||||||||||
`US005434872A
`[11] Patent Number:
`5,434,872
`[45] Date of Patent:
`Jul.18, 1995
`
`5,278,956 1/1994 Thomsen et al. ................... 395/250
`Primary Examiner—Stephen M. Baker
`Attorney, Agent, or Firm—Haynes & Davis
`[57]
`ABSTRACT
`Early initiation of transmission of data in a network
`interface that includes a dedicated transmit buffer is
`provided in a system which includes logic for transfer
`ring frames of data composed by the host computer into
`the transmit buffer. The amount of data of a frame
`which is downloaded by the host to the transmit buffer
`is monitored to make a threshold determination of an
`amount of data of the frame resident in the transmit data
`buffer. The network interface controller includes logic
`for initiating transmission of the frame when the thresh
`old determination indicates that a sufficient portion of
`the frame is resident in the transmit buffer, and prior to
`transfer of all of the data of the frame into the transmit
`buffer. The monitoring logic includes a threshold store,
`which is programmable by the host computer for stor
`ing a threshold value. Thus, the threshold value may be
`set by the host system to optimize performance in a
`given setting.
`
`26 Claims, 13 Drawing Sheets
`
`401
`
`400
`
`403
`
`XMIT BYTE
`TXWR
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`
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`
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`
`4.08
`
`TD HIST
`INTERFACE
`
`XMIT CUNTRDL
`
`411
`
`Ex.1044.001
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`DELL
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`U.S. Patent
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`July 18, 1995
`
`Sheet 1 of 13
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`5,434,872
`
`-
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`4.
`
`HDST
`MEMDRY
`
`HDST
`
`CPU
`
`3
`
`5
`
`
`
`[]THER
`HDST
`DEVICES
`
`2
`
`6A
`
`7
`
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`XMIT LDGIC
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`CVR
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`
`6
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`
`
`
`
`
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`ADAPTDR
`MEMDRY
`
`9
`
`FIG. — 1
`
`Ex.1044.002
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`DELL
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`July 18, 1995
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`Sheet 2 of 13
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`5,434,872
`
`WTICITEW
`
`68
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`- 07
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`
`88
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`
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`Ex.1044.003
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`DELL
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`
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`U.S. Patent
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`July 18, 1995
`
`Sheet 3 of 13
`
`5,434,872
`
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`20
`
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`22
`
`16
`
`11
`
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`
`25
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`HDST
`MEMDRY
`
`19
`Test
`
`18
`
`EISA Bus
`
`13
`
`12
`
`10
`FIG . — 3
`
`[]THER
`HDST DEVICES
`
`52
`62
`
`66
`
`
`
`E-thernet
`Receiver
`
`Ethernet
`Transmitter
`
`67
`
`61
`
`
`
`
`
`Downloo.c.
`DMA
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`
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`
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`Uploo.c.
`DMA
`
`Adopter Mode
`
`Interrupt
`Controller
`
`55
`
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`Inter-foce
`
`
`
`59
`
`Eiso Slove
`Interforce
`
`54
`
`
`
`Moster
`Sloveljnion
`
`53
`
`FIG. — 4
`
`Ex.1044.004
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`DELL
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`U.S. Patent
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`July 18, 1995
`
`Sheet 4 of 13
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`5,434,872
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`50
`
`Rominter-FOce
`
`61
`
`Multicost
`Comporotor
`
`multicost?]++ set[612]
`
`65
`
`Stoltistics
`Controller
`
`sto-tistic?]++ set[712]
`
`57
`
`Uplood Drno.
`
`uploo.cDrno Diffset[1412]
`
`Downlood Drno.
`
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`
`58
`download Dno ByteBn?310]
`downlood Drno Diffset[1212]
`
`63
`
`Receive Drno.
`
`receive Drno Diffset[1412]
`
`67
`
`Tronsmit Dmo.
`
`tronsmit]]rno Diffset[1212]
`
`Autonomous Access Address Bus Structure
`
`FIG. – 4A
`
`Ex.1044.005
`
`DELL
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`
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`U.S. Patent
`
`July 18, 1995
`
`Sheet 5 of 13
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`5,434,872
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`
`
`Ex.1044.006
`
`DELL
`
`
`
`U.S. Patent
`
`July 18, 1995
`
`Sheet 6 of 13
`
`5,434,872
`
`
`
`0800
`
`XMIT AREA
`
`XFER AREA
`
`100C -—
`
`
`
`
`
`
`
`
`
`INFD AND
`STATUS
`REGS,
`
`FIG. – 6
`
`Ex.1044.007
`
`DELL
`
`
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`U.S. Patent
`
`July 18, 1995
`
`Sheet 7 of 13
`
`5,434,872
`
`bose oddress
`
`-
`
`0x0
`
`0xc00
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`size
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`
`5K
`
`22K
`
`1K
`
`256
`
`1.96
`
`96
`
`Adopter RAM Memory Mop
`FIG. – 7
`16 15
`
`0 0++ set
`
`31
`
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`
`Xm tFroit I c.
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`Xm tBuffer Count
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`Xm 1 tºuffer?ount
`times
`
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`
`
`
`
`
`Ex.1044.008
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`DELL
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`U.S. Patent
`
`July 18, 1995
`
`Sheet 8 of 13
`
`5,434,872
`
`150
`
`
`
`prºte CHD
`
`LDGIC
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`153
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`154
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`BUF 0/1
`
`FS
`XT
`
`152
`
`FIG. —9
`
`Ex.1044.009
`
`DELL
`
`
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`US. Patent
`
`July 18, 1995
`
`Sheet 9 of 13
`
`5,434,872
`
`
`
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`U.S. Patent
`
`July 18, 1995
`
`Sheet 10 of 13
`
`5,434,872
`
`300 307
`304 downloadCarry?ut
`jº
`clownlood Bytes
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`ownlood Drno Reset
`clock
`queueFrror
`testAll Counter
`cleorall Counter
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`323
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`Avoil
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`
`Ex.1044.011
`
`DELL
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`
`
`U.S. Patent
`
`July 18, 1995
`
`Sheet 11 of 13
`
`5,434,872
`
`
`
`host.Write Doto [1010]
`stort.ThreshWrite?1.]
`downlood Drno Reset
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`Stort Thresh Volid State Diogram
`FIG. — 14
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`
`Ex.1044.012
`
`DELL
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`U.S. Patent
`
`July 18, 1995
`
`Sheet 12 of 13
`
`5,434,872
`
`11–kyit
`
`350
`
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`otherHost.Write? 310||
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`372
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`FIG. — 17
`
`Ex.1044.013
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`US. Patent
`
`July 18, 1995
`
`Sheet 13 of 13
`
`5,434,872
`
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`1
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`APPARATUS FOR AUTOMATIC INITIATION OF
`DATA TRANSMISSION
`
`5,434,872
`2
`mit data buffer using DMA techniques through a FIFO
`buffer in the interface controller and on to the network.
`Representative prior art systems include the National
`Semiconductor DP83932B, a systems-oriented network
`interface controller (SONIC) and the Intel 82586 local
`area network coprocessor.
`It is desirable to provide the advantages of a transmit
`data buffer, while maintaining the communications
`throughput available from the simpler FIFO based sys
`tem.S.
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`The present application is related to copending U.S.
`patent application entitled NETWORK INTERFACE
`WITH HOST INDEPENDENT BUFFER MAN
`10
`AGEMENT, application Ser. No. 07/921,519, filed 28
`Jul. 1992, now U.S. Pat. No. 5,299,313, which was
`owned at the time of invention and is currently owned
`by the same assignee.
`FIELD OF THE INVENTION
`The present invention relates to interfaces between
`communications networks and data processing systems;
`in particular, systems which involve the transmission of
`packets or frames of data across a communications net
`20
`work.
`
`15
`
`DESCRIPTION OF RELATED ART
`Data communication systems are often based on the
`transmission of packets or frames of data that are com
`25
`posed by a sender. The packets or frames of data are
`designed to be compatible with the network protocol
`involved with the communication system. Thus, the
`sending system must compose the frames of data ac
`cording to the network protocol prior to initiation of 30
`transmission of data. Often, a sending system will wait
`for acknowledgement that a frame of data sent to a
`network adapter has been transmitted prior to perform
`ing a subsequent task, such as composing a second frame
`35
`of data to be transmitted.
`Some network adapter interfaces include dedicated
`transmit buffers into which a frame of data composed
`by the sending system can be downloaded by the send
`ing system. The frame is then stored in the transmit data
`buffer until the media access control functions associ
`ated with transmitting the frame on the network have
`successfully transmitted the frame, or cancelled the
`frame transmission. If the frame transmission is can
`celled, the data may be retained in the transmit data
`45
`buffer until the sending system initiates a second at
`tempt to transmit the frame. Transmit data buffers are to
`be distinguished from first-in-first-out FIFO systems, in
`which the sending system downloads data of a frame
`into the FIFO, while the network adapter unloads the
`FIFO during a transmission. The data in FIFOs cannot
`be retained and reused by the media access control
`functions, or by the host, like data in transmit data buff
`erS.
`Although transmit data buffers enable a sending sys
`tem to compose and download a frame into the transmit
`data buffer, and then attend to other tasks while the
`network adapter attempts to transmit the frame, it suf
`fers the disadvantage that transmission of a frame is
`delayed until the entire frame has been downloaded into
`the buffer. Thus, transmit data buffer type systems im
`prove host system efficiency at the expense of network
`throughput. Operations which are communication in
`tensive suffer a performance downgrade.
`Furthermore, the prior art systems which use trans
`65
`mit data buffers require the host or sending system to
`manage the transmit data buffer. A network interface
`controller transfers data from the host managed trans
`
`50
`
`SUMMARY OF THE INVENTION
`The present invention provides for the early initiation
`of transmission of data in a network interface that in
`cludes a dedicated transmit buffer. The system includes
`logic for transferring frames of data composed by the
`host computer into the transmit buffer. Also, the
`amount of data of a frame which is downloaded by the
`host to the transmit buffer is monitored to make a
`threshold determination of an amount of data of the
`frame resident in the transmit buffer. The network inter
`face controller includes logic for initiating transmission
`of the frame when the threshold determination indicates
`that a sufficient portion of the frame is resident in the
`transmit buffer, and prior to the transfer of all of the
`data of the frame into the transmit buffer. In one aspect
`of the invention, the monitoring logic includes a thresh
`old store, which is programmable by the host computer
`for storing a threshold value and logic for posting status
`information to the host. Thus, the threshold value may
`be set by the host system to optimize performance using
`the alterable threshold store and the posted status infor
`mation.
`According to another aspect of the present invention,
`the transmit buffer includes a transmit descriptor ring,
`and a transmit data buffer. The host system composes a
`frame by storing a transmit descriptor in the adapter
`managed transmit descriptor ring. The transmit descrip
`tor may remain resident in the transmit descriptor ring
`for some time prior to an initiation of the transmission of
`the data by the adapter, because of other transmit de
`scriptors being processed ahead of a current descriptor,
`or other reasons. When the adapter begins processing of
`a transmit descriptor, it retrieves immediate data from
`the descriptor itself, and begins a download process into
`the transmit data buffer of data identified in the descrip
`tor. The threshold logic determines the amount of im
`mediate data from the descriptor, and monitors the
`downloading of data of the frame into the download
`area. When the combination meets the threshold, then
`actual transmission of the frame is initiated. Thus, trans
`mission of a frame may be initiated before the complete
`frame has been downloaded into the download area.
`Accordingly, the present invention provides an archi
`tecture for a network interface controller which greatly
`increases the flexibility for host systems in composing
`and transmitting frames of data, while maintaining com
`munications throughput for applications that are com
`munications intensive.
`Other aspects and advantages of the present inven
`tion can be seen upon review of the figures, the detailed
`description, and the claims which follow.
`BRIEF DESCRIPTION OF THE FIGURES
`FIG. 1 is a simplified block diagram of a system with
`a network interface according to the present invention.
`
`Ex.1044.015
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`DELL
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`5,434,872
`3
`4
`-
`FIG. 2 is a schematic functional block diagram of the
`unit 3, host memory 4, and other host devices 5, all
`early transmit system according to the present inven
`communicating across the bus 2. A network interface
`tion.
`adapter 6 is coupled to the host bus 2. The adapter 6 is
`FIG. 3 is a block diagram of a preferred implementa
`coupled to a transceiver 7 which is, in turn, connected
`tion of the host system and network interface according
`to a network medium 8, such as coaxial cable, a twisted
`to the present invention.
`pair conductor, a fiber optic, satellite, wireless, or other
`FIGS. 4 and 4A are diagrams of the network inter
`communication medium. The network adapter 6 is, in
`face processor of FIG. 3 implementing the present in
`turn, connected to an adapter memory 9, which is man
`vention, and of the structure of the autonomous access
`aged by the interface controller 6 or by the host CPU 3,
`address buses, respectively.
`depending on a particular implementation provided.
`10
`FIG. 5 a schematic diagram illustrating data flow
`The adapter 6 also includes early transmit logic 6A for
`from the host memory space through adapter memory
`monitoring the transfer of data from the host system 1
`to the network according to the present invention.
`into the adapter memory 9. The early transmit logic 6A
`FIG. 6 is a map of the host system address space used
`makes a threshold determination for a given frame
`for any transmission of data according to the present
`being transferred from the host 1 into the adapter mem
`invention.
`ory 9. When the threshold is met, then the adapter 6
`FIG. 7 is a memory map of the adapter memory
`begins transmitting the frame across the network. Of
`independent of the host system address space.
`course, a wide variety of other configurations of these
`FIG. 8 illustrates the transcript descriptor data struc
`components could be implemented. For instance, the
`ture according to one aspect of the present invention.
`adapter memory 9 may be connected directly to the
`20
`FIG. 9 illustrates the management of the transmit
`host bus 2. Also, multiple bus configurations might be
`descriptor ring buffer and transmit data buffer, and
`utilized.
`pointers used during the transmit operation according
`FIG. 2 illustrates the functional components of the
`early transmit system according to the present inven
`to the present invention.
`-
`FIGS. 10A-10E are a schematic illustration of the
`tion. In FIG. 2, a number of functional blocks are repre
`management of the pointers for the transmit descriptor
`sented. The host computer or sending system 30 com
`ring buffer and transmit data buffer.
`municates with a host interface logic 31, receiving data
`FIG. 11 is a logic diagram illustrating the data path
`as indicated by line 32 and control signals as indicated
`arithmetic used in the transmit function for the network
`by line 33. The host interface logic 31 supplies data to a
`interface controller of FIG. 4.
`transmit buffer 34 across line 35. Also, threshold logic
`30
`FIG. 12 is a logic diagram of the transmit start con
`36 is coupled with the host interface logic 31 to monitor
`trol logic for the network interface adapter of FIG. 4.
`the transfer of data from the host computer 30 into the
`FIG. 13 is a logic diagram of the transmit start thresh
`frame buffer 34. The line 37 indicates the coupling of
`old register for the logic of FIG. 12.
`the threshold logic 36 to the host interface logic 31. The
`FIG. 14 is a state diagram for the transmit start
`threshold logic makes the threshold determination and
`35
`threshold register of FIG. 13.
`generates a signal as indicated by line 38 to transmit
`FIG. 15 is a logic diagram of the download compare
`logic 39 including, for instance, media access control
`logic of FIG. 12.
`MAC logic. The transmit logic 39 receives data from
`FIG. 16 is a logic diagram of the immediate data
`the buffer 34 across lines 40 and supplies that data as
`comparator of FIG. 12.
`indicated by line 41 to the network medium 42. Coupled
`FIG. 17 is a state diagram for the data available con
`with the threshold logic 36 is a threshold store 43 which
`trol function in the logic of 12.
`stores a threshold value which indicates an amount of
`FIG. 18 is a simplified block diagram of the transmit
`data of a frame that must be resident in the frame buffer
`logic according to the present invention.
`34 before transmission of that frame may be initiated by
`the transmit DMA logic and MAC 39.
`DESCRIPTION OF THE PREFERRED
`The threshold store 43, in a preferred system, is dy
`EMBODIMENTS
`namically programmable by the host computer 30. In
`A detailed description of preferred embodiments of
`this embodiment, the threshold store 43 is a register
`the present invention is provided with respect to the
`accessible by the host through the interface logic 31.
`figures. FIGS. 1 and 2 provide an overview of the data
`Alternatively, the threshold store may be a read only
`50
`communications systems according to the present in
`memory set during manufacture. In yet other alterna
`vention. FIGS. 3 through 10A-10E provide a detailed
`tives, the threshold store may be implemented using
`description of a preferred implementation of the present
`user specified data in non-volatile memory, such as
`invention, including data structures and data flow.
`EEPROMs, FLASH EPROMs, or other memory stor
`FIGS. 11–18 provide one implementation of logic for
`age devices.
`55
`implementing the early transmission feature of the pres
`The transmit logic 39 also supplies status information
`ent invention.
`across line 44 to the host interface logic 31, for posting
`I. System Overview
`to the host system. The status information includes
`FIG. 1 illustrates a data communication system ac
`indications of underrun conditions and may be used by
`cording to the present invention with a controller cir
`the host to optimize the value in the threshold store 43.
`cuit using a dedicated transmit buffer memory which is
`In operation, the host computer composes a frame of
`automatically enabled to begin transmission of a frame
`data to be transmitted on the network medium 42. The
`on the network when the number of bytes available in
`host computer 30 then identifies that frame through the
`the transmit buffer memory exceeds a preprogrammed
`host interface 31. The host interface coupled with the
`threshold. As shown in FIG. 1, such system for commu
`identifiers of the frame move data from the host com- .
`65
`nicating data includes a host data processing system,
`puter 30 into the buffer 34 according to the description
`generally referred to by reference number 1, which
`of the frame. The threshold logic 36 monitors the trans
`includes a host system bus 2, a host central processing
`fer of data into the buffer 34. When the threshold
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`amount of data is resident in the buffer 34, then the
`The INFO EEPROM 17 stores critical adapter spe
`transmit logic 39 is instructed to begin transmission of
`cific data used by drivers, diagnostics, and network
`the frame. The transmit logic 39 then begins retrieving
`management software. This data is stored during the
`data from the buffer 34 to support transmission of the
`manufacturing process. During initialization of the in
`frame on the medium 42. This operation begins before
`terface controller, the contents of the EEPROM 17 are
`the entire frame has been transferred from the host
`loaded into a prespecified area of the RAM 15 for use
`during operation.
`computer 30 into the buffer 34, if the transmit logic 39
`is available to transmit the frame subject of the ongoing
`Coupled to the interface processor 16 is an encode/
`download from the host computer 30, the frame being
`decode chip 19, such as the National Semiconductor
`downloaded into the buffer 34 is larger than the thresh
`8391 Manchester encode/decode chip. The signals cou
`old set by the threshold store 43, and the host computer
`pled to the AUI connector are provided to allow use of
`30 indicates that immediate transmission of the data is
`a transceiver external to the board.
`desired.
`The transceiver 20 in a preferred system comprises
`As mentioned above, the buffer 34 may be directly
`either a thin Ethernet (coax/BNC) transceiver or a
`addressable by the host computer 30, or in preferred
`10BaseT (Type 3/RJ-45) transceiver. Control signals
`systems is addressable through the host interface 31
`for the transceiver 20 are produced on the network
`which consists of a prespecified area of host address
`interface controller 14, using the conversion logic on
`space into which the host computer 30 writes data and
`the encode/decode chip 19.
`control signals associated with a transmission operation.
`A test port 18 is provided in a preferred system for
`The host interface 31 then maps the transfer of data
`use during manufacture and testing.
`20
`from that prespecified address space into the buffer 34
`III. Controller Functional Units
`and host accessible registers independent of the host.
`FIG. 4 provides a block diagram of the network
`A more detailed description of a preferred embodi
`interface processor 14 of FIG. 3, including functional
`ment of the present invention is illustrated in FIG. 3.
`blocks and data paths. There are numerous connections
`II. System Overview
`not shown having to do with the control of the various
`25
`FIG. 3 is a schematic diagram of a computer system
`data flow paths. The interfaces illustrated include a
`including the network interface controller according to
`RAM interface 50, a host bus interface 51, and a trans
`the present invention. The computer system includes a
`ceiver interface 52. The bus interface 51 is implemented
`host system, including a host processor 10, host memory
`for an EISA bus, and operates at times either as a master
`11, and other host devices 12, all communicating
`or as a slave on the bus. Each of the functional units in
`30
`through a host system bus 13, such as an EISA bus. The
`the implementation shown in FIG. 4 is described below.
`host system bus 13 includes address lines which define a
`A. EISA Slave Interface 54
`host system address space. Typically, for an EISA bus,
`The EISA slave interface 54 provides a path for the
`there are 32 address lines establishing a host system
`EISA host to access the registers and buffers managed
`address space of about 4 Gigabytes.
`by the network interface controller. The module con
`35
`tains configuration registers for the controller, and per
`The network interface controller includes a network
`interface processor 14, implemented in one preferred
`forms crude decoding of the EISA bus for the purpose
`system as an application specific integrated circuit de
`of routing signals. The EISA slave interface 54 does not
`signed to implement the functions outlined below using
`interpret any of the addressing of individual registers
`VERILOG design tools as known in the art (available
`distributed throughout the controller.
`from Cadence, Inc., San Jose, Calif.). The network
`In operation, the EISA slave interface continuously
`interface processor 14 is coupled through appropriate
`monitors the EISA address bus and determines when
`the configuration registers, memory mapped network
`buffers to the bus 13. The network interface processor
`14 is also coupled to random access memory 15, BIOS
`registers, or BIOS ROM of the adapter are being ac
`ROM 16, and INFO EEPROM 17, a test port 18, an
`cessed.
`45
`encode/decode chip 19, and a network transceiver 20.
`In addition, for every memory slave cycle initiated by
`The network transceiver 20 is, in turn, coupled to a
`the EISA bus, the EISA slave interface will post a cycle
`network medium.
`request to the cycle arbiter 56. The cycle arbiter im
`A majority of the functionality is embodied in the
`poses wait states upon the host system until the request
`network interface processor 14. In the preferred em
`has been granted.
`50
`bodiment, all registers that are accessible across the bus
`The EISA slave interface also provides a generic 32
`13 by the host system reside either in the processor 14,
`bit bus interface to the remainder of the network con
`or in the RAM 15. If resident in the RAM 15, their
`troller. The generic nature of the interface allows for
`access is managed by the network interface processor
`easy adaptation of the design to other bus types, such as
`14.
`the microchannel, without requiring redesign of the
`55
`The RAM 15 is a primary resource on the network
`remainder of the chip.
`interface controller. This resource provides buffer
`Bits 14–2 of the EISA address bus are latched and
`memory outside the host address space used in the
`pass through to other modules. The least significant two
`transmit and receive operations of the network inter
`bits (1, 0) of the address are represented by 4 byte ena
`face. Details concerning the organization and utilization
`bles that are also valid throughout a data transfer cycle.
`of this RAM 15 are described below.
`Four 8-bit byte lanes make up the slave data channel.
`The BIOS ROM 16 provides extension to the host
`The data bus is actually a pair of unidirectional buses,
`system’s basic input/output code through the network
`one for writes and one for reads in a preferred system.
`interface processor 14 during initialization. The ad
`The data write bus is wired in a multi-drop fashion to all
`dresses for the BIOS ROM 16 and the data from the
`modules that require connection to the EISA data bus
`65
`BIOS ROM 16 are coupled to the network interface
`through the slave interface. The read bus is multiplexed
`processor 14 across buses 21 and 22, respectively, which
`and masked in the RAM interface module 50. Write
`are also shared by the RAM 15.
`requests by the EISA bus can be held until they are
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`acknowledged by the cycle arbiter 56. When a cycle is
`E. Adapter Mode Module 59
`held, the EISA bus may be released from wait states
`The adapter mode module 59 provides a number of
`while the cycle completes on the adapter. If a second
`functions including setting various basic operating
`cycle is generated by the EISA bus while the first one is
`modes of the controller, and reporting status of various
`still pending, then the EISA bus will be held off with
`conditions of the controller. The adapter module 59 also
`wait states until the pending write is performed. In this
`establishes the base address of a window register used
`specific embodiment, pipelining of EISA reads is not
`for diagnostics by the host system. Furthermore, the
`supported.
`adapter mode module 59 generates reset functions for
`The EISA slave interface also provides an interface
`the adapter. Also, this module provides the MAC ID
`to the EEPROM 17. This interface operates to transfer
`register which identifies the media access controller
`10
`the contents of the EEPROM 17 into the adapter mem
`implemented by the device, for communication to vari
`ory after reset.
`ous modules within the controller and to the host sys
`There are numerous registers in the EISA slave inter
`tem.
`face module 54, primarily related to configuration of the
`F. Cycle Arbiter Module 56
`adapter that conform to the EISA bus specification.
`The cycle arbiter module 56 is responsible for distrib
`These registers do such things as set up the adapter's
`uting access to the adapter's RAM resident and ASIC
`memory base address, the interrupt level, the trans
`resident registers through the RAM interface 50 among
`ceiver type selection, and the BIOS ROM enable. The
`various requestors. It functions to allow timely access to
`configuration registers also provide the host with a
`the RAM by modules that are most in danger of suffer
`positive means of identifying the adapter type and to
`ing an overrun or underrun condition in response to a
`20
`globally disable the adapter.
`priority scheme.
`G. Multicast Comparator Module 61
`B. EISA Master Interface 55
`The EISA master interface 55 handles requests from
`The controller illustrated in FIG. 2 also includes a
`the upload DMA 57 and download DMA 58 for per
`multicast comparator module 61. When enabled by the
`forming bus master operations across the EISA bus.
`adapter mode module 59, the multicast comparator
`25
`The EISA master interface 55 autonomously arbitrates
`module 61 performs a bit by bit comparison of a re
`between pending upload and download requests, be
`ceived frame's destination address field with contents of
`cause of the EISA bus disallowing mixed reads and
`the multicast address table. The multicast address table
`writes while performing burst transfers, used by the
`is established by the host and stored in RAM 15. A
`DMA operations of the preferred embodiment.
`mismatch during this compare, coupled with neither an
`The bus master transfers are always initiated by either
`individual address nor a broadcast address match, will
`result in the rejection of an incoming frame.
`the upload DMA 57 or the download DMA 58. The
`transfers may be terminated by either the DMA mod
`Thus, the multicast comparator module 61 monitors
`ules upon completion of a transfer, or by the EISA
`the activity of the Ethernet receiver module 62 and the
`master interface upon preemption by another arbitrary
`receive DMA module 63 to determine when a new
`35
`device on the EISA bus.
`frame is being received. Each byte that is received by
`the Ethernet receiver 62 and presented at the parallel
`Thus, the function of the EISA master interface 55 is
`to arbitrate for access to the EISA bus when transfer
`interface 64 of the receiver, is shadowed by the mul
`requests are pending from either or both of the upload
`ticast comparator module 61. These bytes are then com
`pared against valid entries in a multicast address table
`DMA 57 and the download DMA 58. The EISA master
`interface 55 performs the signalling necessary to estab
`accessible by the multicast comparator 61.
`The multicast comparator 61 does no