[11]
`4,027,293
`May 31, 1977
`“ ” ”, ”
`
`United States Patent [19]
`"**
`**wuanasoor,
`[54] MICROCODE PROGRAM SEQUENCER
`|75|| Inventors: Neil R. Lincoln, St. Paul; David R.
`Resnick, Arden Hills, both of Minn.
`[73] Assignee: Control Data Corporation,
`Minneapolis, Minn.
`Sept. 12, 1975
`[22] Filed:
`[21 | Appl. No. 612,837
`1521 U.S. Cl. ............................................ 340/172.5
`| 5 | |
`Int. Cl.” ........................................... G06F 9/16
`[58] Field of Search ................................. 340/172.5
`[56)
`References Cited
`UNITED STATES PATENTS
`3,839,705 l ()/ 1974 Davis et al. ..................... 340/172.5
`3,868,649 2/1975 Sato et al. ...................... 34()/ I 72.5
`3,886,523
`5/1975 Ferguson et al. ............... 340/1 72.5
`3,909,800
`9/1975 Recks et al. .......
`... 34()/ 172.5
`3,979,729 9/1976 Eaton et al. ..........
`... 34()} | 72.5
`Primary Examiner—Gareth D. Shaw
`
`Assistant Framiner—C. T. Bartz
`Attorney, Agent, or Firm—Robert M. Angus
`[57]
`ABSTRACT
`A microcode program sequencer includes first and
`second registers (herein designated the Q and P regis
`ters), each connected to a computer memory to receive
`addresses therefrom. Control means is provided for
`each register such that the P register will provide out
`put addresses to a microcode memory, whereas the Q
`register(s) provide output addresses to the P register.
`By properly operating the control means, incrementing
`of addresses from the P register can be accomplished,
`as well as address jumps and returns, using the O regis
`ter. Further, the contents of the Q register may also be
`incremented in synchronism with the P register, as
`desired. One feature of the invention resides in a condi
`tional latch circuit which may be selectively operated
`as a latch or as an OR gate.
`
`13 Claims, 9 Drawing Figures
`
`B RANCH
`ADDRESS
`
`
`
`
`
`Q |
`CONTROL
`
`
`
`(2)
`
`Q 2
`CONTROL
`
`
`
`MASTER
`C - E AR
`
`P
`CGNTROL
`
`CONDITION
`LATCH
`
`
`
`Ex.1051.001
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`U.S. Patent May 31, 1977
`
`Sheet 1 of 5
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`4,027,293
`
`BRANCH
`ADDRESS
`|
`
`f
`
`|
`
`23
`
`@Hoon Rol-(?)
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`2/
`
`Q2
`@-controLH-Q)
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`22
`
`39
`
`P
`CONTROL
`
`P
`REG.
`
`(4)
`
`@
`
`26
`
`+ |
`IN CR
`
`CARRY
`OUT
`
`MASTER
`CLEAR
`
`CONDITION
`LATCH
`
`(3)
`
`|
`|
`
`P OUT
`
`25
`
`CARRY
`control?-27
`( FIG. 4D )
`
`|
`LOAD
`microcod E |
`( FIG. 2 )
`|
`
`( FIG. 3)
`
`CA R RY | N
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`Ex.1051.002
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`U.S. Patent May 31, 1977
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`Sheet 2 of 5
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`4,027,293
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`Ex.1051.003
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`U.S. Patent May 31, 1977
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`Sheet 3 of 5
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`ATVG, 34
`
`FROM
`B RANCH ADDRESS
`7 *, 32
`_2^
`33
`[- - - - - - - -
`|
`|
`|
`
`94
`85
`
`
`
`9 2/o
`AND
`
`AND
`
`R
`
`2//
`
`S2
`OR Ho Q OUT
`
`CONTINUE D
`( F | G. 3B )
`
`95
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`S4
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`96
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`§§ CC
`
`Ano
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`97
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`# Hº
`
`AND P- 93
`D D
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`AA
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`B B CC
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`o P OUT
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`O CARRY
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`U.S. Patent May 31, 1977
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`Sheet 4 of 5
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`73
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`AT/G. JAP
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`Q
`A N D.
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`39
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`O Q OUT
`
`a?ºn
`ADDREss 2
`84
`
`
`
`
`
`J
`W
`
`Z
`
`
`
`LATCH
`
`A
`
`
`
`L ATC H
`
`F
`
`76
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`O
`
`e JLATCH
`H.
`H
`
`/O2
`@
`
`AOO
`
`CR
`
`/O/
`
`/03
`@
`
`2 /8
`
`o P OUT
`
`B5 &c. DD - 2/9
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`/ O4
`
`O Q OUT
`
`O R
`
`O P OUT
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`U.S. Patent May 31, 1977
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`Sheet 5 of 5
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`4,027,293
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`— 3
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`(o) (P)
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`C L O C K
`
`PIG. 44
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`- ;
`
`Q OUT CONTROL
`
`FIG. 4B
`
`ºf
`•-
`FIG. 4C
`
`Q S E LEC T
`
`Ç
`
`FROM
`PRIOR
`CIRCUITS I C
`
`/2O
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`65
`
`C A R R Y CONTROL
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`ATIG. 4D
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`/35
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`ATIG. 5
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`Another feature of the present invention resides in
`the provision of a highly versatile microcode program
`MICROCODE PROGRAM SEQUENCER
`sequencer capable of functioning in a variety of com
`This invention relates to computer processors, and
`puters, regardless of generation, configuration, speed
`particularly to a microcode program sequencer for
`or bit length of word.
`controlling computer operations.
`With a microcode program sequencer according to
`Microcode program sequencers are utilized in com
`the present invention, the size of the microcode mem
`puters for controlling logic functions of a computer.
`ory may be minimized because subroutine techniques
`For example, many computers utilize common cir
`are possible within the microcode sequencer itself. The
`cuitry capable of any of several functions which, when
`microcode program sequencer according to the present
`properly gated from a microde program memory, will 10
`invention may be connected in a chained fashion to
`perform a selected function. Heretofore, most micro
`provide control for larger memories. Further, the se
`code sequencers have been specifically designed for
`quencers may be connected in tandem to provide
`each computer and have been connected to a read-only
`phased execution from independent memory elements,
`memory (ROM) to receive addresses from the micro
`thereby increasing the apparent speed of the se
`code memory, process those addresses and other con- 15
`quencer. Further, the provision of separate registers
`trol signals, and control the microcode memory to send
`within the microcode program sequencer enables two
`appropriate enable signals to the various enable gates
`dimensional decision processes to be accomplished.
`of the logic circuitry. Heretofore, due to the differences
`The above and other features of this invention will be
`in hardwire configuration of various generations of
`more fully understood for the following detailed de
`20
`computers, the difference in the bit length of words,
`scription and the accompanying drawings in which:
`and other significant differences, it has not been possi
`FIG. 1 is a block circuit diagram of a microcode
`ble to construct a microcode program sequencer capa
`program sequencer in accordance with the presently
`ble of functioning in any of several computers. Thus,
`preferred embodiment of the present invention;
`microcode sequencers have heretofore been unique to
`FIG. 2 is a block circuit diagram of the control func
`a single type or model of computer. Further, due to the
`tions of the microcode program sequencer illustrated in
`association of microcode program sequencers with a
`FIG. 1;
`read-only microcode memory, the versatility of most
`FIGS. 3A and 3B, taken together, are a block circuit
`prior microcode sequencers has been hindered, Since
`diagram of the register and output control functions of
`additional functions could not be written into the mem
`the microcode program sequencer illustrated in FIG. 1;
`30
`ory for use with the microcode sequencer. Instead, all
`FIGS. 4A through 4D are block circuit diagrams of
`processing to be accomplished by the microcode se
`certain control circuits utilized in the microcode pro
`quencer had to be inserted into the microcode memory
`gram sequencer shown in FIG. 1; and
`as a design feature of the computer, and could not be
`FIG. 5 is a block circuit diagram of a conditional
`altered in the field.
`latch circuit useful with the microcode program se
`Prior microcode program sequencers utilized a single
`quencer according to the present invention.
`register for storage of the microcode address. As a
`With reference to FIG. 1, there is illustrated a block
`result, such microcode program sequencers were lim
`circuit diagram of a microcode program sequencer in
`ited in their capabilities to perform jump and return
`accordance with the presently preferred embodiment
`routines, as such routines, if performed, had to be per- 40
`of the present invention. The microcode sequencer
`formed elsewhere in the computer.
`comprises a Q1 control circuit 20, a Q2 control circuit
`A microcode program sequencer according to the
`21 and a P control circuit 22. Circuits 20 and 21 each
`present invention comprises a plurality of registers,
`receive 2 bits of input from a microcode memory,
`herein designated Q and P registers, with control cir
`whereas control circuit 22 receives a 4-bit input from
`cuits to control input to the registers. The control cir- 45
`microcode memory. In addition, conditional latch, load
`cuits receive inputs from the microcode memory to
`microcode enable, and master clear signals may be
`selectively operate the Q and P registers to receive
`provided to the P control circuit. Q1 register 23 re
`branch addresses or other functions. By selectively
`ceives inputs from the branch address portion of the
`conditioning the control circuits, new addresses may be
`microcode memory, increment circuit 26 and the Q1
`read into any of the registers, addresses may be incre- 50
`control circuit 20. Q1 register 23 provides an output to
`mented for continuous operation, or jumps and other
`P register 25. Q2 register 24 receives inputs from the
`computer operations can be performed. The output of
`Q2 control circuit 21, increment circuit 26 and the
`the registers is taken directly to the microcode memory
`branch address of the microcode memory, and pro
`vides an output to P register 25. Additionally Q1 and
`for new addresses or for direct operation on the logic
`Q2 registers 23 and 24 may also provide another output
`circuits of the computer.
`(designated Q out) for test and control purposes. P
`One feature of the invention resides in the provision
`of hardware capable of controlling the P and Q register
`register 25 receives inputs from the P control circuit
`22, the branch address of the microcode memory, in
`to selectively store and/or increment addresses so that
`the sequencer will provide one set of addresses from
`crement circuit 26 and the Q1 and Q2 registers di
`rectly, P register 25 provides an output directly to the
`one register, while holding another address for future 60
`microcode memory as well as to plus one increment
`use. The address in the other register may be used for
`circuit 26, which in turn provides outputs to each of the
`returns, jumps or other purposes, depending upon how
`registers 23, 24 and 25. Increment circuit 26 further
`the registers are selectively controlled.
`provides a Carry output to further microcode se
`Another feature of the present invention resides in
`quencer circuits as will be more fully explained herein
`the provision of a microcode program sequencer oper- 65
`after. Several microcode sequencer circuits illustrated
`able with a microcode memory capable of read and
`in FIG. 1 may be arranged in a chained fashion, in
`write functions so that additional instructions may be
`which case a carry output will be forwarded from one
`written into the microcode memory.
`
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`200, 201, 202 and 203 provide outputs to the I, J. K
`microcode sequencer to the next, particularly through
`and L conductors respectively.
`the carry control circuit 27 associated with the plus one
`FIG. 3 illustrates the register, carry and increment
`increment circuit 26.
`portions of the microcode program sequencer illus
`FIGS. 2–4 illustrate a more detailed block circuit
`diagram of the microcode program sequencer illus
`trated in FIG. 1. As shown in FIG. 3 a plurality of latch
`trated in FIG. 1. Referring particularly to FIG. 2, which
`circuits 70–81 are provided to receive branch ad
`dresses via connectors 82, 83, 84 and 85 from the
`illustrates the control circuits 20, 21 and 22, the Q1
`branch address portion of the microcode memory. The
`control circuit 20 is illustrated in the upper left-hand
`portion of FIG. 2, Q2 control circuit 21, which is sub
`details of latch circuit 70 are illustrated in FIG. 3, and
`stantially the same as the Q1 control circuit 20, is
`is understood that the other latch circuits have essen
`shown in the upper right-hand portion of FIG. 2, and
`tially the same type of circuitry, with differences as
`the remainder of the Figure is essentially devoted to the
`noted hereinafter.
`Latch circuit 70 includes an AND gate 86 connected
`P control circuit 22.
`to receive inputs from the Z conductor and from the
`The Q1 control circuit includes a pair of inputs 30,
`31 connected to OR gate 32. OR gate 32 is connected
`branch address via connector 82. AND gate 87 is con
`to AND gate 33 which in turns provide an output to
`nected to receive inputs from the C and I conductors.
`AND gates 86 and 87 provide inputs to OR gate 88
`circuits 35 and 36 and an inverted output to conductors
`A. AND gates 35 and 36 provide outputs to conductors
`which in turn provides outputs to drive circuits 89 and
`90. The output from drive circuit 90 is provided as one
`Z and C, respectively. Drive circuit 35a provides a
`input to AND gate 91 which in turn provides an input
`second input between input 30 and AND gate 35, while
`to OR gate 88. The second input for AND gate 91 is
`drive circuit 36a provides a second input between input
`provided via conductor A.
`31 and AND gate 36. The Q2 control circuit includes
`input terminals 37 and 38 connected to OR gate 39
`Conductor 82 from the branch address is connected
`which in turn provides an output to AND gate 40. AND
`as an input to latch circuits 70, 71 and 72, conductor
`gate 40 provides an inverted output to the conductors
`83 is connected as an input to latch circuits 73, 74 and
`25
`B and an output to AND gates 42 and 43. Drive circuit
`75, conductor 84 is connected as an input to latch
`42a provides direct connection between terminal 37
`circuit 76, 77 and 78, and conductor 85 is connected as
`and AND gate 42 while drive circuit 43a provides con
`an input to latch circuits 79, 80 and 81. Latch circuit
`71 also receives inputs from conductors B, D, I and Y,
`nection between terminal 38 and AND gate 43. AND
`gates 42 and 43 provide outputs to conductors Y and
`while latch circuit 72 receives inputs from conductors
`30
`D, respectively. The second inputs of AND gates 33
`F., I, X and W. Latch circuit 73 receives inputs from
`conductors A, C, J and Z, latch circuit 74 receives
`and 40 are connected to conductor N to receive clock
`pulses.
`inputs from conductors B, D, J and Y, while latch cir
`cuit 75 receives inputs from conductors F, J, W and X.
`The P control circuit has input terminals 44, 45, 46,
`47, 48 and 49. Input terminal 44 is connected as a first
`Latch circuit 76 receives inputs from conductors A, C,
`input to AND gates 50 and 51, input terminal 45 is
`K and Z, latch circuit 77 receives inputs from conduc
`connected to AND gates 51 and 52, input terminal 46
`tors B, D, K and Y, while latch circuit 78 receives
`is connected to AND gates 52 and 53, and input termi
`inputs from conductors F, K, W and X. Latch circuit 79
`receives inputs from conductors A, C, L and Z, latch
`nal 47 is connected to AND gates 50 and 53. The out
`puts from AND gates 50 and 51 are connected separate
`circuit 80 receives inputs from conductors B, D, L, and
`40
`inputs to OR gate 54 and to NOR gate 55 while the
`Y, while latch circuit 81 receives inputs from conduc
`outputs of gates 52 and 53 are connected as separate
`tors F, L, W and X.
`Latch circuit 70 provides inputs to AND gates 210
`inputs to OR gate 56 and NOR gate 57. The output
`and 213 while latch circuit 71 provides inputs to AND
`from OR gate 54 is connected to a first input of AND
`gates 211 and 212. AND gates 210 and 211 provide
`gate 58, the output of OR gate 56 is connected to a first
`45
`input of AND gate 59, and the outputs from NOR gates
`outputs to OR gate 92, while AND gates 212 and 213
`provide outputs to OR gate 93. AND gate 210 receives
`55 and 57 are connected through AND gate 55a to one
`a second input from conductor Q, AND gate 211 re
`input of OR gate 60.
`ceives a second input from conductor R, AND gate 212
`Terminal 49 is connected to drive circuit 61 which
`provides inputs to AND gates 200, 201, 202 and 203
`receive a second input from conductor S and AND gate
`and an inverted output to one input of AND gate 62.
`213 receives a second input from conductor T, OR gate
`92 provides an output to Q out, which is one bit line for
`The other input of AND gate 62 is connected to termi
`the Q output shown in FIG. 1. OR gate 93 provides an
`nal 48. AND gate 62 provides one output to a second
`input to latch circuit 72.
`input of AND gates 58 and 59, and an inverted output
`As shown in the drawings, and particularly in connec
`to a second input of OR gate 60. AND gate 58 provides
`an output to AND gate 204; OR gate 60 provides an
`tion with latch circuit 72, latch circuits 72, 75, 78 and
`output to AND gate 205; and AND gate 59 provides an
`81 each include an additional AND gate 300 each
`output to AND gate 206. Conductor N provides inputs
`connected to receive inputs from the E conductor and
`to drive circuits 66 and 67; drive circuit 67 providing
`from an OR gate (such as OR gate 93) associated with
`an output to AND gates 205 and 206 and an inverted
`a prior latch circuit. The circuit associated with these
`four latch circuits is essentially the same as that shown
`output to conductor F while drive circuit 66 provides
`output to AND gate 204.
`in connection with latch circuit 70, the difference being
`AND gates 204, 205 and 206 provide outputs to the
`that the inputs from the E conductor and the prior OR
`X, W and E conductors respectively. AND gate 200
`circuit 93 are connected to AND gate 300 which in
`turn provides an output to the OR gate shown as OR
`receives a second input from conductor II; gate 201
`gate 88 in latch circuit 72. Latch circuit 72 provides an
`receives a second input from conductor JJ, gate 202
`output through drive circuit 94 to P out, which is the
`receives a second input from conductor KK and gate
`first bit line of the output for the P register. Latch
`203 receives a second input from conductor LL Gates
`
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`It will be appreciated that OR gates 92, 99, 104 and
`circuit 72 also provides an output to latch circuit 95
`109 pass a signal to the respective Q out bit line when
`which in turn provides outputs to AND gate 96 and to
`a signal is present from one (or both) of the inputing
`EXCLUSIVE OR gate 97. AND gate 96 receives inputs
`latch circuits and a corresponding signal appears on a
`from latch circuit 95, and from conductors AA, BB and
`respective one of conductors Q or R. Thus, OR gate 92
`CC which in turn are connected to the output of latch
`provides a Q out signal when a signal is provided from
`circuits 102, 107 and 112. AND gate 96 provides an
`latch circuit 70 and on the Q conductor or when a
`output to Carry Out, for purposes to be hereinafter
`signal is provided from latch circuit 71 and from the R
`explained. AND gate 98 receives inputs from conduc
`conductor. Similarily, OR gate 93, 100, 105 and 110
`tors AA, BB, CC, and DD and provides an output to
`provide outputs on a conditional basis when one or the
`EXCLUSIVE OR gate 97. EXCLUSIVE OR gate 97
`other of the inputing latch circuits provides a signal and
`provides an output to conductor II (for feeding back to
`a corresponding S or T conductors also provide a sig
`AND gate 200 (FIG. 2) to enable inputs to latch cir
`nal. Thus, OR gate 93 provides an output when a signal
`cuits 70, 71 and 72 on conductor I).
`is present from latch circuit 70 and also conductor T or
`Similarly, latch circuits 73 and 74 provide outputs to
`when signal is present from latch circuit 71 and also on
`AND gates 214, 215, 216 and 217 to operate OR gates
`conductor S.
`99 and 100; AND gates 214 and 215 further receiving
`As shown in FIGS. 4A, 4B and 4C, the clock asso
`inputs from conductors Q and R respectively to operate
`ciated with the microcode processor provides outputs
`OR gate 99 to provide and output to a second bit line
`on conductors N and O and inverted outputs on con
`of Q out. AND gate 216 and 217 receive further inputs
`ductors M and P, a Q out control circuit (FIG. 4B)
`20
`from conductors S and T, respectively, to control OR
`provides an output on conductor R and and inverted
`gate 100 to provide an input to latch circuit 75. Latch
`output on conductor Q, and a Q select control (FIG.
`circuit 75 provides an output through drive circuit 101
`4C) provides an output on conductor S and an inverted
`for a second bit line of P out. In addition, latch circuit
`output on conductor T. Also, as shown in FIG. 4D, a
`75 provides output to latch circuit 102 which in turn
`carry control is provided and consists of an AND gate
`25
`provides an output for conductor AA and to EXCLU
`120 having input terminals connected to prior micro
`SIVE OR gate 103. EXCLUSIVE OR gate 103 receives
`code sequencers. As will be more fully understood
`a further input from AND gate 218 which receives
`hereinafter, several microcode sequencers, as illus
`inputs from conductors DD, BB and CC. Gate 103
`trated in FIG. 1, may be provided to operate in a
`provides an output to conductor JJ for feeding back to
`chained fashion. In such an event, the carry out signal
`AND gate 201 to enable to latch circuits 73,74 and 75
`from gate 96 (FIG. 3) will be connected as an input to
`via conductor J.
`AND gate 120 so that if all of the lower-ordered micro
`Latch circuits 76 and 77 provide outputs to AND
`code sequencers provide a carry output, AND gate 120
`gates 219, 220, 221 and 222 to enable OR gate 104 and
`will be operated to provide a signal on conductors DD.
`105; AND gates 219 and 220 receiving further inputs
`It will be evident to those skilled in the art that when a
`35
`from conductors Q and R to control OR gates 104 to
`plurality of sequencers are arranged in a chained fash
`provide an output for a third bit line of Q out, and AND
`ion, conductor DD of the lowest-ordered sequencer
`gates 221 and 222 receiving further inputs from the S
`will be tied to a permanent source of binary 1 signals,
`and T conductors and providing outputs to OR gate
`the next higher ordered sequencer will have its conduc
`105 to provide an output to latch circuit 78. Latch
`tor DD connected to the carry output conductor from
`40
`circuit 78 provides an output through drive circuit 106
`gate 96 of the lowest-ordered sequencer, and the high
`to a third bit line of P out, and provides an output to
`er-ordered sequencer will have its DD conductor con
`latch circit 107. Latch circuit 107 provides outputs to
`nected to the output of AND gate 120 (FIG. 4D) whose
`inputs are connected to the carry outputs of the all
`conductors BB and to EXCLUSIVE OR circuit 108.
`EXCLUSIVE OR circuit 108 receives an input from
`lower-ordered sequencers.
`circuit 401 and provides an output to conductor KK for
`It will be appreciated that latch circuits 70, 73, 76
`feeding back to AND gate 102 to enable latch circuits,
`and 79 comprise the Q1 register, that latch circuits 71,
`74, 77 and 80 comprise the Q2 register and that latch
`76, 77 and 78 via conductor K. AND gate 401 receives
`circuits 72, 75, 78 and 81 comprise the P register.
`an input from conductors DD and EE.
`In operation of the apparatus as thus far described,
`Latch circuits 79 and 80 provides to AND gates 223,
`224, 225 and 226 to enable OR gates 109 and 110;
`assume it is desired to load data into the Q2 register
`AND gates 223 and 224 receiving further inputs from
`from the address field of the microcode memory. The
`four bits of data is applied to lines 82 through 85 and
`the Q and R conductors to control OR gate 109 to
`provide a fourth bit line of Q out, and AND gates 225
`hence to latch circuits 71, 74, 77 and 80. The Q2 con
`and 226 receiving further inputs from conductors S and
`trol is enabled via terminal 37 to supply outputs on the
`55
`T to control OR gates 110 to provide an output to latch
`Y conductors and an inverted output on the B conduc
`circuit 81. Latch circuit 81 provides an output through
`tors to operate the latch circuits associated with the Q2
`register. The data is then loaded into the register during
`drive circuit 1 11 to the fourth bit line of P out, and
`a clock pulse. Upon removal of the signal from terminal
`provides an output to latch circuit 112. Latch circuit
`37, the output of AND gate 40 is inverted so that an
`112 provides outputs to conductors CC, EE and EX
`60
`enable signal is provided via conductors B to the latch
`CLUSIVE OR gate 113. Exclusive OR gate 113 re
`circuits to store the data in the latch. In the respect, the
`ceives a second input from conductor DD and provides
`signal on conductor B and the output of OR gate 88
`an output to conductor LL to enable AND gate 203 to
`through drive circuit 90 serve to operate AND gate 91
`provide a signal via conductor L for latch circuits 79,
`to maintain the output from OR gate 88 after inversion
`80 and 81.
`of the signal on conductor Y. Assuming it is desirable
`As shown in FIG. 3, each of latch circuits 95, 102,
`to transfer that information from the Q2 register to the
`106 and 112 receive inputs from the O and P conduc
`P register, the Q select circuit (FIG. 4C) is operated to
`tors, which are essentially clock inputs. (See FIG. 4A).
`
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`4,027,293
`8
`7
`SIVE OR gate 103, thereby providing a binary 1 output
`provide outputs on the S conductors to enable AND
`gates 212, 216, 221 and 225 to pass the information
`on conductor J.J.
`The binary 0s appearing on conductors KK and LL,
`through OR gates 93, 100, 105 and 110 to AND gate
`when applied to AND gates 202 and 203, cause a 0
`300 of latch circuits 72, 75, 78 and 81. Simultaneously
`signal to be applied via conductors K and L to latch
`the P control circuit provides enable signals over the E
`circuits 78 and 81, so that during the next clock pulse
`conductors to the AND gates 300 of latch circuits of
`these latches will be set to 0. The binary 1 on conductor
`the P register to enable the latch circuits to receive the
`JJ, when applied through AND gate 201, causes a 1 to
`data from the O2 register. (The signals on the E con
`be applied via conductor J to latch circuit 75, so that
`ductors will occur during a clock cycle whenever sig
`during the next clock pulse the latch will be set to 1.
`nals to terminals 45 and 46 or to terminals 46 and 47
`are binary Is. Normally signal to terminals 45 and 46
`It is evident that after the latches are set to 100,
`(stepped up from the 011 initial code), that code is
`come from microcode memory and the signal on termi
`transferred into latches 102, 107 and 112 so that the l
`nal 47 comes from conditional latch circuit (FIG. 5).
`signal on conductors BB, CC and EE are reset to 0 and
`The data can be read out through the P out terminals
`1 binary signals during the next iteration.
`of the P register to the microcode memory as memory
`In the event that all latches 72, 75, 78 and 81 contain
`addresses to select instructions for direct operation of
`binary 1s, signals are impressed onto conductors AA,
`the computer logic. If it is desirable to run a continuous
`BB and CC to operate AND gate 96 to provide a carry
`increment of the addresses, enable and data signals can
`out signal to AND gate 120 (FIG. 4D) of all higher
`be provided through latch circuits 95, 102, 107 and
`ordered sequencers. If all lower-ordered sequencers of
`110 to EXCLUSIVE OR circuits 97, 103, 108 and 113
`a chained arrangement provide 1 inputs to an AND
`to provide outputs on the I conductors back to the latch
`gate 120 of a higher-ordered sequencer, such gate pro
`circuits of the P register to continuously increment the
`vides a 1 signal output on its conductor DD to enable
`address. At the same time, the latch circuits associated
`gates 97, 103, 108 and 113 in such higher-ordered
`with the Q2 register may be incremented if the Q2
`sequencer to invert, depending upon the conditions as
`control circuit provides outputs on the D conductor.
`25
`Otherwise, the Q2 register may hold the original data
`heretofore described.
`In most applications, it would be desirable to read
`from the branch address for a future return. While
`control information through the P register to the micro
`addresses are being issued from the P register, it may be
`code memory, and the separate outputs of the Q regis
`desirable to load a future address into the Q1 or Q2
`ters will be most ordinarily reserved for test and control
`register, which can be accomplished from the branch
`30
`purposes. However, it is possible to selectively operate
`address and proper enabling of the latch circuits in a
`the Q register outputs through the Q out control in FIG.
`manner similar to that described for the Q2 latch cir
`5B for direct reading and application from the Q regis
`cuits.
`ters, Microcode memory may provide signals back to
`In an increment mode, each EXCLUSIVE OR gate
`the microcode processor through suitable control logic
`97, 103, 108 and 113 will pass the signal received from
`35
`circuits (not shown) to selectively operate the condi
`the respective latch circuit, or an inversion of it, de
`pending upon the conditions of other signals into the
`tional latch circuit of FIG. 5.
`While the forgoing is merely illustrative of the opera
`respective EXCLUSIVE OR gate. For exmaple, assume
`tion of the microcode program sequencer according to
`latch circuit 78 and 81 (the two least significant bit
`the present inventions, it is evident that many varia
`positions of the P register) each contain a binary 1,
`tions will be evident to those skilled in the art. Thus,
`while latch circuit 75 (the third least significant bit
`direct loading of any of the P, Q1 or Q2 registers may
`position of the P register) contains a binary 0. If the bit
`be accomplished, independantly or simultaniously, by
`positions of the sequencer are the very lowest of any
`proper selection of control signals from the circuits.
`chained arrangement of sequencers (which is presently
`Thus, loading of the Q1, Q2 and P registers from mem
`assumed for purpose of description), conductors DD
`45
`ory is accomplished by control signals over the Z, Y
`will be permanently tied to a source of binary 1 signal.
`and X conductors, respectively, loading incremental
`Prior to the first clock pulse (after the clock pulse
`addresses is accomplished by control signals on the C,
`causing loading of the signals into the P register), the
`D and W conductors, repsectively, latch storing is ac
`signals stored in latch circuits 75, 78 and 81 are trans
`complished by control signals over the A, B and F
`ferred to latch circuits 102, 107 and 112. This transfer
`conductors, respectively, and transfer from one of the
`is accomplished between clock pulse due to the pres
`Q1 and Q2 registers to the P register may be accom
`ence of a binary 1 on the P conductor from the clock
`plished with control signals on one of the S and T con
`(see FIG. 4A). Latch circuits 112 and 107 provide
`ductors, respectively, and on the E conductors.
`binary 1 outputs, while latch circuit 102 provides a
`binary 0 output. As a result, binary 1 signals are pro
`One feature of the invention resides in a conditional
`55
`latch circuit shown in Fl(3, 5, such circuit consists of an
`vided to EXCLUSIVE OR gates 108 and 113 by latch
`OR gate 130 for receiving inputs from AND gates 131,
`circuits 107 and 112. Also, binary 1 signals are pro
`132, 133 and 134. AND gate 135 receives inputs from
`vided on conductors BB, CC and EE. The binary 1
`terminal 136 and from conductor M and provides in
`signal on conductor EE, together with the binary 1
`verted outputs to each of AND gates 131, 132 and 133.
`already on conductor DD, causes EXCLUSIVE OR
`60
`AND gates 131, 132 and 133 receive second inputs
`gate 108 to invert the signal, causing a 0 output on
`from terminals 137, 138 and 139, respectively. AND
`conductor KK. Further, the binary 1 input to gate 113
`gate 135 also provides an output to an input of AND
`will produce an inverted output due to the presence of
`gate 134. OR gate 130 provides an output through drive
`a binary 1 on conductor DD, thereby providing a 0
`circuit 141 to terminal 142 and through drive circuit
`output on conductor LL. Further the binary 1 signals
`143 to an input of EXCLUSIVE OR gate 144 and a
`on both conductors BB and CC together with the bi
`nary 1 on conductor DD operate AND gate 218 to
`second input of AND gate 134. EXCLUSIVE OR
`invert the 0 input from latch circuit 102 in EXCLU
`gate 144 receives a second input from terminal 145 to
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`provide an output to terminal 146.
`The conditional latch circuit illustrated in FIG. 5 is
`conditionally operable as either a latch circuit or an OR
`gate. AND gate 135 receives inverted clock inputs via
`conductor M (see FIG. 4A). Hence, AND gate 135
`normally receives a l input from conductor M, which
`goes to 0 during a clock input.
`If terminal 136 receives a 0 input from microcode
`memory, an inverted (1) output will be impressed on
`the lower inputs of AND gates 131, 132 and 133.
`Hence, if any one of terminals 137, 138 or 139 (or any
`combinati