•
`
`t
`
`let a highly-active interface lock out the others (which would happen with a single
`queue).
`The transmit request may be a segment that is less than the MSS, or it may be as.much as
`a full 64K SMB READ. Obviously the fonner request will go out as one segment, the
`latter as a number ofMSS-sized segments. The transmitting TCB must hold on tp the
`request until all data in it has been transmitted and acked. Appropriate pointers to do this
`will be kept in the TCB. A large buffer is acquired from the free buffer fifo, and the MAC
`and TCP/IP headers are created in it. It may be quicker/simpler to keep a basic frame
`header set up in the TCB and either dma directly this into the frame each time. Then data
`is dmad from host memory into the frame to create an MSS-sized segment. This dma also
`checksums the data. Then the checksum is adjusted for the pseudo-header and placed into
`the TCP header, and the frame is queued to the MAC transmit interface which may be
`controlled by the third sequencer. The final step is to update various window fieids etc in
`the TCB. Eventually either the entire request will have been sent and acked, or a
`retransmission timer will expire in which case the context is flushed to the host. In either
`case, the INIC will place a command response in the Response queue containing the
`command buffer handle from the original transmit command and appropriate st&tus.
`The above discussion has dealt how an actual transmit occurs. However the real
`challenge in the transmit processor is to determine whether it is appropriate to transmit at
`the time a transmit request arrives. There are many reasons not to transmit: the receiver's
`window size is <= 0, the Persist timer has expired, the amount to send is less thap a full
`segment and an ACK is expected I outstanding, the receiver's window is not half-open
`etc. Much of the transmit processing will be in determining these conditions.
`
`5.3.4 Transmit Details - No Valid Context
`
`The main difference between this and a context-based transmit is that the queued request
`here will already have the appropriate MAC and TCP/IP (or whatever) headers in the
`frame to be output. Also the request is guaranteed not to be greater than MSS-sized in
`length. So the processing is fairly simple. A large buffer is acquired and the frame is
`dmad into it, at which time the checksum is also calculated. If the frame is TCP/IP, the
`checkswn will be appropriately adjusted ifnecessary (pseudo-header etc) and pfaced in
`the TCP header. The frame is then queued to the appropriate MAC transmit intepace.
`Then the command is immediately responded to with appropriate status through the
`Response queue.
`
`5.3.5 Transmit Notes
`
`1. Slow-start: the INIC will handle the slow-start algorithm that is now a part of the
`TCP standard. This obviates waiting until the connection is sending a full-rate
`before passing it to the INIC.
`2. Window Probe vs Window Update: an explanation for posterity ....
`A Window Probe is sent from the sending TCB to the receiving TCB, and it means the
`sender has the receiver in PERSIST state. Persist state is entered when the receiver
`advertises a zero window. It is tbus the state of the transmitting TCB. In this state, be
`sends periodic window probes to the receiver in case an ACK from the receiver bas been
`lost The receiver will return his latest window size in the ACK.
`
`Provisional Pat. App. of Alacritech, Inc.
`Inventors Laurence B. Boucher et al.
`Express Mail Label# EH756230105US
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`57
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`ALA00138443
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`Ex.1031.061
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`A Window Update is sent from the receiving TCB to the sending TCB, usually to tell him
`that the receiving window has altered. It is mostly triggered by the upper layer when it
`accepts some data. This probably means the sending TCB is viewing the receiving TCB
`as being in PERSIST state.
`3. Persist state: it is designed to handle Persist state on the INIC. It seems
`unreasonable to throw a TCB back to the host just because its receiver advertised a
`zero window. This would nonnally be a transient situation, and would tent-1 to
`happen mostly with clients that do not support slow-start. Alternatively, tl:i.e code
`can easily be changed to throw the TCB back to the host as soon as a receiver
`advertises a zero window.
`4. MSS-sized frames: the INIC code will expect all transmit requests for which it has
`no TCB to not be greater than the MSS. If any request is, it will be dropped and an
`appropriate response status posted.
`S. Silly Window avoidance: as a receiver, the INIC will do the right thing here and
`not advertise small windows - this is easy. However it is necessary to also do
`things to avoid this as a sender, for the cases where a stupid client does advertise
`small windows. Without getting into too much detail here, the mechanism requires
`the INIC code to calculate the largest window advertisement ever advertised by the
`other end. It is an attempt to guess the size of the other end's receive buffer and
`assumes the other end never reduces the size of its receive buffer. See Stevens Vol.
`l pp. 325-326.
`
`6 The Utility Processor
`
`6.1 Summary
`
`The following is a summary of the main functions of the utility sequencer of the
`microprocessor:
`
`look at the event queues: Eventl3Type & Event23Type (we assume there will be an
`•
`event status bit for this -
`USE_EV13 and USE_EV23) in the events register; these
`are events from sequencers 1 and 2; they will mainly be XMIT requests from the XMT
`sequencer. Dequeue request and place the frame on the appropriate interface.
`• RCV-frame support: in the model, RCV is done through VinicReceiveO which is
`registered by the lower-edge driver, and is called at dispatch-level. This routine calls
`VinicTransferDataCompleteO to check if the xfer (possibly DMA) of the frame into host
`buffers is complete. Tue latter rtne is also called at dispatch level on a DMA-coi;npletion
`interrupt. It queues complete buffers to the RCV sequencer via the nonnal queue
`mechanism.
`• Other processes may also be employed here for supporting the RCV sequencer.
`•
`service the following registers: (this will probably involve micro-interrupts)
`Header Buffer Address register:
`buffers are 256 bytes long on 2?6-byte boundaries.
`31-8 - physical addr in host of a set of
`contiguous hddr buffers
`7-0 - number ofhddr buffers passed.
`Use contents to add to SmallHType queue
`
`Provisional Pat. App. of Alacritech, Inc.
`Inventors Laurence B. Boucher et al.
`Express Mail Label# EH75623010SUS
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`58
`
`ALA001 38444
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`Ex.1031.062
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`...
`
`Data Buffer Handle & Data Buffer Address registers:
`buffers are 4K long aligned on 4K boundaries ...
`Use contents to add to the FreeType queue.
`
`Command Buffer Address register:
`buffers are multiple of32 bytes up to lK long (2**5 • 32)
`31-5 - physical add.r in host of cmd buffer
`4-0 - length of cmd in bytes/32
`(i.e. multiples of32 bytes)
`Points to host cmd; get FreeSType buffer and move
`command into it; queue to Xmit0-Xmit31'ype queues.
`
`Response Buffer Address register:
`buffers are 32 bytes long on 32-byte boundaries
`31-8 - physical addr in host of a set of
`contiguous resp buffers
`7-0 - number of resp buffers passed.
`Use contents to add to the ResponseType queue.
`
`low buffer threshold support: set approp bits in the ISR when the available-buffers
`•
`count in the various queues filled by the host falls below a threshold.
`
`6.2 Further Operations of the Utility Processor
`
`The utility processor of the microprocessor housed on the INIC is responsible for setting
`up and implementing all configuration space and memory mapped operations, and also as
`described below, for managing the debug interface.
`
`All data transfers, and other INlC initiated transfers will be done via OMA.
`Configuration space for both the network processor function and the utility processor
`function will define a single memory space for each. This memory space will d~fine the
`basic commwtlcation structure for the host. In general, writing to one of these memory
`locations will perform a request for service from the INIC. This is detailed in t.l1e
`memory description for each function. This section defines much of the operatibn of the
`Host interface, but should be read in conjunction with the Host lnterface Strategy for the
`Alacritech INIC to fully define the Host/INIC interface.
`
`Two registers, DMA hardware and an interrupt function comprise the INIC interface to
`the Host through PCI. The interrupt function is implemented via a four bit register
`(PCl_INT) tied to the PCI interrupt lines. This register is directly accessed by the
`microprocessor.
`
`THE MICROPROCESSOR uses two registers, the PCI_Data_Reg and the
`PCI_Address_Reg, to enable the Host to access Configuration Space and the memory
`space allocated to the INIC. These registers are not available to the HosL but are used by
`THE MICROPROCESSOR to enable Host reads and writes. The function of these two
`registers is as follows.
`
`Provisional Pat. App. of Alacritecb, Inc.
`Inventors Laurence B. Boucher et al.
`Express Mail Label# EH756230105US
`
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`
`ALA001 38445
`
`Ex.1031.063
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`

`

`

`

`

`

`.r:tar-n"r:inr"a.»rts:"r:attittrrs
`
`processor will construct the data required and transfer it. Reads to this memory will
`generate 00 for data.
`
`6.2.2.1 Network Processor
`
`The following four byte registers, beginning at location but] of the network processor‘s
`allocated memory, are defined.
`
`()0?
`
`04-
`
`08—
`
`0C—
`
`10—
`
`14_
`
`Interrupt Status Pointer -- Initialized by the host to point to a four byte area
`where status is stored
`
`Interrupt Status — Returned status from host. Sent afier one or more
`status conditions have been reset. Also an interlock for storing any
`new status. Once status has been stored at the Interrupt Status Pointer
`location, no new status will be stored until the host writes the Interrupt
`Status Register. New status will be cred with any remaining
`unoleared status (as defined by the contents of the returned status)
`and stored again at the Interrupt Status Pointer location. Bits are
`as follows:
`Bit 31 ERR u Error bits are set
`Bit 30 — RCV — Receive has occurred
`
`Bit 29 — XMT # Transmit command complete
`Bit 25 — RMISS —- Receive drop occurred due to no buffers
`
`Interrupt Mask — Written by the host. Interrupts are masked for each
`of the bits in the interrupt stems when the same bit in the mask
`register is set. When the Interrupt Mask register is Written and as
`a result a status bit is unmasked, an interrupt is generated. Also,
`when the Interrupt Status Register is written, enabling new status
`to be stored, when it is stored if a bit is stored that is not masked
`by the Interrupt Mask. an interrupt is generated.
`
`Header Buffer Address — Written by host to pass a set of header buffers to the
`INIC.
`
`Data Buffer Handle — First register to be written by the Host to transfer a receive
`data buffer to the INIC. This data is Host reference data. It is not used by the
`INIC, it is returned with the data buffer. However, to insure integrity of the
`buffer, this register must be interlocked with the Data Buffer Address register.
`Once the Data Buffer Address register has been written, neither register can be
`written until after the Data Buffer Handle register has been read by THE
`MICROPROCESSOR.
`
`Data Buffer Address * Pointer to the data buffer being sent to the [NIC by the
`Host. Must be interlocked with the Data Buffer Handle
`
`register.
`
`18—
`
`Command Buffer Address XMTO — Pointer to a set of command
`
`buffers sent by the Host. THIE NUCROPROCESSOR will DMA the buffers to
`local DRAM found on the FreeSType queue and queue the Command
`
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`Buffer Address XMTO with the local address replacing the host
`Address.
`
`10 — Command Buffer Address SM'I‘l
`
`20 — Command Buffer Address SMT2
`
`24 a Command Buffer Address SMT3
`
`28 — Response Buffer Address -- Pointer to a set of reaponse butters sent
`by the Host. These will be heated in the same fashion as the
`Command Buffer Address registers.
`
`6.2.2.2 Utility Processor
`
`Ending status will be handled by the utility processor in the same fashion as it is: handled
`by the network processor. At present nvo ending status conditions are defined B31 —
`command complete, and B30 -— error. When end status is stored an interrupt is
`generated.
`
`Two additional registers are defined, Command Pointer and Data Pointer. The Host is
`responsible for insuring that the Data Pointer is valid and points to sufficient memory
`before storing a command pointer. Storing a command pointer initiates command decode
`and execution by the debug processor. The Host must not modify either command or
`Data Pointer until ending status has been received, at which point a new command may
`be initiated. Memory space is write only by the Host, reads will receive 00. The format
`is as follows:
`
`00 —
`
`Interrupt Status Pointer - Initialized by the host to point to a four byte area
`where status is stored
`
`04 —
`
`Interrupt Status — Returned steals from host. Sent after one or more
`status conditions have been reset. Also an interlock for storing any
`new status. Once status has been stored at the Interrupt Status Pointer
`location, no new status will be stored until the host writes the Interrupt
`Status Register. New status will be ored with any remaining
`nucleated status (as defined by the contents of the returned status)
`and stored again at the Interrupt Status Pointer location. Bits are
`as follows:
`
`Bit 31 — CC — Command Complete
`Bit 30 — ERR — Error
`Bit29 —- Transmit Processor Halted
`BitQB — Receive Processor Halted
`
`Bit27 — Utility Processor Halted
`
`
`
`.Iafl'i.est-rt?W’TJ'"1.2"»5"}H"l;“1""!iii!'53
`
`
`
`
`
`08 -
`
`Interrupt Mask — Written by the host. Interrupts are masked for each
`of the bits in the interrupt status when the same bit in the mask
`register is set. When the Interrupt Mask register is written and as
`a result a status bit is unmasked, an interrupt is generated. Also,
`
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`when the Interrupt Status Register is written, enabling new status
`to be stored, when it is stored if a bit is stored that is not masked
`by the Interrupt Mask, an interrupt is generated.
`
`0C — Command Pointer — Points to command to be executed. Storing
`this pointer initiates command decode and execution.
`
`to — Data Pointer — Points to the data buffer. This is used for both read and write data,
`determined by the command function.
`:
`
`7 Debug Interface
`
`In order to provide a mechanism to debug the microcode running on the microprocessor
`sequencers, a debug process has been defined which will run on the utility sequencer.
`This processor will interface with a control program on the host processor over PCI.
`
`7.1
`
`PCI Interface
`
`This interface is defined in the combination of the Utility Processor and the Host
`Interface Strategy sections, above.
`
`7.2 Command Format
`The first byte of the command, the command byte, defines the structure of the remainder
`of the command. The first five bits of the command byte are the command itself. The
`next bit is used to Specify an alternate processor, and the last two bits specify which
`processors are intended for the command.
`
`3‘:
`if;
`
`3 f
`
`:
`E
`E
`5"
`3.3,
`
`éfi
`
`;
`a?
`
`‘s
`
`7.2.1 Command Byte
`
`7 7- 3
`Command
`
`2
`Alt. Proc.
`
`1 - 0
`Processor
`
`7.2.2 Processor Bits
`
`00 — Any Processor
`01 _ Transmit Processor
`10 — Receive Processor
`
`1] — Utility Processor
`
`Provisional Pat. App. of Alacritech, Inc.
`Inventors Laurence B. Boucber et :11.
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`65
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`

`7.2.3 Alternate Processor
`
`This bit defines which processor should handle debug processing if the utility pr'ocessm
`is defined as the processor in debug.
`
`0 — Transmit Processor
`1 — Receive Processor
`
`7.2.4 Single Byte Commands
`
`(JO—Halt
`
`This command asynchronously halts the processor.
`
`08 — Run
`
`This command starts the processor.
`
`10 — Step
`
`This command steps the processor.
`
`a
`
`5 i
`
`7.2.5 Eight Byte Commands
`18 —Break
`
`o
`Command
`
`1
`Reserved
`
`2 — 3
`Count
`
`4:;
`Address
`
`This command sets a stop at the specified address. A count of 1 causes the specified
`processor to halt the first time it executes the instruction. A count of 2 or more causes the
`processor to halt alter that number of executions. The processor is halted just before
`executing the instruction. A count oft) does not halt the processor, but causes a_ sync
`signal to be generated. If a second processor is set to the same break address, the count
`data from the first break request is used, and each time either processor executes the
`instruction the count is decremented.
`
`20 — Reset Break
`
`0
`Command
`
`1 - 3
`Reserved
`
`4 ~ 7
`Address
`
`5;;
`:2
`is
`
`a 1
`
`.;
`fe‘E
`
`Provisional Pet. App. of Alacritech. Inc.
`Inventors Laurence E. Beecher et 21.
`Express Mail Label it EH'i56230105US
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`66
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`

`This command resets a previously set break point at the specified address. Reset break
`fully resets that address. If multiple processors Were set to that break point, all Will be
`reset.
`
`‘28 — Dump
`
`0
`
`1
`
`Command
`
`Descriptor
`
`2 - 3
`
`Count
`
`4 — '7
`
`Address
`
`This command transfers to the host the contents of the descriptor. For descriptors larger
`than four bytes, 51 count, in four byte increments is specified. For descriptors utilizing an
`address the address field is specified.
`
`7.2.6 Descriptor
`
`00 F Register
`
`I'Eil
`
`This descriptor uses both count and address fields. Both fields are four byte based (3
`count of 1 ti’ansfers four bytes).
`
`
`
`
`
`ref.it"s-i1‘lii'11:51.7"i153:till3.31.?'5511HE.
`
`
`
`
`
`01 — Sram
`
`This descriptor uses both count and address fields. Count is in four byte blocks. Address
`is in bytes, but if it is not four byte aligned, it is forced to the lower four byte aligned
`address.
`
`02 — Dram
`
`This descriptor uses both count and address fields. Count is in four byte blocks. Address
`is in bytes, but if it is not four byte aligned, it is forced to the lower four byte aligned
`address
`
`03 — Cstore
`
`This descriptor uses both count and address fields. Count is in four byte blocks. Address
`is in bytes, but if it is not four byte aligned, it is forced to the lower four byte aligned
`address
`
`Stand-alone descriptors:
`
`The following descriptors do not use either the count or address fields. They transfer the
`contents of the referenced register.
`
`04 — CPU_STATUS
`
`{IS—PC
`
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`Inventors laurence B. Boucher et 31.
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`06 — ADDR§REGA
`
`07 7 ADDR_REGB
`
`08 —- RAM_BASE
`
`09 — FILE_BASE
`
`0A — INSTR_REG_L
`
`OB - mS'I'R_REG_H
`
`0C — MAC_DATA
`
`0D — DMAfiEVENT
`
`0E — MISC_EVENT
`
`0F — Q_IN_RDY
`
`10 —- CLOU'I‘_RDY
`
`11 — LOCK. STATUS
`
`12 — STACK - This returns 12 bytes
`
`13 — Sense _ Reg
`
`This register contains four bytes of data. If error status is posted for a command, if the
`next command that is issued reads this register, a code describing the error in more detail
`may be obtained. If any command other than a dump of this register is issued after error
`status, sense information will be reset.
`
`30 # Load
`
`0
`Command
`
`l
`Descriptor
`
`2 — 3
`Count
`
`4 ~- 7
`Address
`
`This command transfers from the host the contents of the descriptor. For descriptors
`larger than four bytes, a count, in [our byte increments is specified. For descriptors
`utilizing an address the address field is specified.
`
`7.2.7 Descriptor
`
`00 4 Register
`
`
`
`
`
`4":Iiiirll'n'lt'T“lE“'Ilia:HH'lT'53}Elliill“33
`
`This descriptor uses both count and address fields. Both fields are four byte based.
`
`Provisional Pat. App. of Macritoch. Inc.
`Inventors Laurence B. Boucher et a1.
`
`Express Mail Label 3 EH756230105US
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`
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`01—Sram
`
`This descriptor uses both count and address fields. Count is in four byte blocks. . Address
`is in bytes, but if it is not four byte aligned, it is forced to the lower four byte aligned
`address.
`
`(IQ-Dram
`
`This descriptor uses both count and address fields. Count is in four byte blocks. Address
`is in bytes, but if it is not four byte aligned, it is forced to the lower four byte aligned
`address
`
`03 — Cstore
`
`This descriptor uses both count and address fields. Count is in four byte blocks. Address
`is in bytes, but if it is not four byte aligned, it is forced to the lower four byte aligned
`address. This applies to WCS only.
`
`Stand-alone descriptors:
`
`The following descriptors do not use either the count or address fields. They transfer the
`contents of the referenced register.
`
`04 -— ADDR_REGA
`
`05 ~ ADDR_REGB
`
`06 — RAM_BASE
`
`07 — FILE_BASE
`
`08 — MAC‘_DATA
`
`09 -— Q_[N_RDY
`
`0A — O_0UT_.RDY
`
`OB —» DBG_ADDR
`
`38 — Map
`
`
`
`.rtiT.titri-flfl'if}"ll?“lib[LilH"E71711PE][3*£31
`
`
`
`
`
`This command allows an instruction in ROM to be replaced by an instruction in WCS.
`The new instruction will be located in the Host buffer. It will be stored in the first eight
`bytes of the buffer, with the high bits unneed. To reset a mapped out instruction, map it
`to location 00.
`
`0
`Command
`
`l - 3
`Address to
`Map To
`
`4 — 7
`Address to
`Map Our
`
`Provisional Pat. App. of Alacrltech. Inc.
`Inventors laurence B. Boucher et 31.
`Express Mail Label .i' EH756230£05US
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`8
`
`HARDWARE SPECIFICATION
`
`FEATURES
`
`- Peripheral Component Interconnect (PCI) Interface
`
`- Universal PCl interface supports both 5.0V and 3.3V signaling environments.
`
`— Supports both 32-bit and 64 bit PCI interface.
`
`- Supports PCI clock frequencies from lSMI-Iz to 661MHz
`
`- High perfomtanoe bus mastering architecurre.
`
`- Host roe-roomr based communications reduce register accesses.
`
`- Host memory based interrupt status word reduces register room.
`
`- Plug and Play compatible.
`
`- PCI specification revision 2.1 compliant.
`
`- PCI bursts up to 512 bytes.
`
`- supports cache line operations up to 123 bytes.
`
`- Both big-endinn and little-endiau byte alignments supported.
`
`- Supports Expansion ROM.
`
`. Network Interface
`
`- Four internal 802.3 and ethernet compliant Macs.
`
`- Media Independent interface (Mil) supports external PHYS.
`
`— 103As‘a-T, lODBASE—TXIFX and 100BASE-T4 supported.
`
`— Full and halfouplex modes supported.
`
`- Automatic PHY status polling notifies system of status change.
`~ Provides SNMP statistics counters.
`
`~ Supports broadcast and multicast packets.
`
`- Provides promiscuous mode for network monitoring or rrmltiple unicast address detection.
`
`— Supports “huge packets” up to 32KB.
`
`- Mac—layer loop-back test mode.
`
`- Supports auto-negotiating Phys.
`
`si
`
`
`
`
`
`mi“.iiiu‘ittitiiiliit?"”flit.Eli3H'i-"TFill14TH]'l.
`
`
`
`
`
`Provisional Pat. App. of AlaCritOCh. Inc.
`Inventors Laurence B. Boucher et a1.
`Express Mail Label if EH756230105US
`
`70
`
`D‘@@u@;os“llou"""n"
`
`ALA00138456
`
`DELL Ex.1031.074
`Ex.1031.074
`
`DELL
`
`

`

`- Memory Interface
`
`- External Dram buffering of tranmit and receive packets.
`
`- Bufi'ering configurable as 4MB, 3MB. 16MB or 32MB.
`
`- 32-bit interface supports throughput of 224MBls
`
`- Supports external FLASH ROM up to 4 MB, for diskless boot applications.
`
`- Supports external serial EEPROM for custom configuration and Mac addresses.
`
`- Protocol Processor
`
`- High speed. custom, 32—bit processor executes 66 million instructions per second.
`
`~ Processes 1P, TCP and NETBIOS protocols.
`
`- Supports up to 256 resident 'FCPIIP contexts.
`
`- Writahle control store (WCS) allows field updates for feature enhancements.
`
`lit-"it"5?ER'll?"Elli;fl1E3!it?"EllIi}El"5.!
`
`ll‘ -
`vl’.
`
`- Power
`
`— 3.3V chip operation.
`
`- PCI controlled 5.0V!3.3V U0 cell operation.
`
`0 Packaging
`
`- 212-pin plastic ball grid may.
`
`- 91 PCI signals.
`
`- 53 MI] signals.
`
`- 58 external memory signals.
`
`— l clock signal.
`
`— 54 signals split between power and grannd.
`
`- 272 total pins.
`
`Provisional Pat. App. of Alacritech, Inc.
`Inventors laureate B. Booster et a].
`Express Mail Label # EH7562‘30105US
`
`'Il
`
`D‘flmm‘ofi-ll-omn”
`
`ALA00138457
`
`DELL Ex.1031.075
`Ex.1031.075
`
`DELL
`
`

`

`GENERAL DESCRIPTION
`
`The microprocessor is a 32-bit, hill-duplex, four channel. 10f lilo-Megabit per second (mops). Intelligent
`Network Interface Controller. designed to provide high-speed protocol Wing for server applications. It
`combines the functions of a standard network interface controller and a protocol processor within a single
`chip. Although designed specifically for server applications. The microprocessor canbe used by; PCs.
`workstations and routers or anywhere that 'I‘CPIIP protocols are being utilized.
`
`When combined with four 302.3:‘MII compliant Phys and Synchronous Dram (SDrarn), the INIC comprises
`four complete othernet nodes. It contains four 802.3lethemet compliant Macs, a PCI Bus Interface Unit (BIU),
`a memory controller. transmit fifos, receive fifos and a custom TCPfleNETBlOS protocol processor. The
`[MC supports lUBase-T . IUDBase-TX, motions—Flt and tOGBase-Ttt via the M11 interface attachment of
`appropriate Phys.
`
`The INIC Macs provide statistical information that may be used for SNMP. The Macs operate in promiswous
`mode allowing the [NIC to function as a network monitor, receive broadcast and multicast packets and
`implement multiple Mac addresses for each node.
`
`Any 802.3!MII compliant PHY can be utilized. allowing the lNIC to support lUBASE-‘I‘, IUBASE-TZ,
`lOOBASE-TX,
`lflOBase—FX and lflOBASE-T4 as well as future interface standards. PHY identification and
`initialization is accomplished through host driver initialization routines. PHY status registers can be polled
`continuously by the IN'IC and detected P‘HY stauts changes reported to the host driver. The Mac can be
`configured to support a maximum frame size of 1518 bytes or 32768 bytes.
`
`_
`
`The 64-bit. multiplexed Bill provides a direct interface to the PCI bus for both slave and master functions.
`The [NIC is capable of operating in either a 64-bit or 32—bit PCI environment. while supporting 64-bit
`addrasing in either configuration. PCI bus frequenciec up to GoMHz are supported yielding instantaneous bus
`transfer rates of SSBMBls. Both 5.0V and 3.3V signaling environments can be utilized by the INIC.
`Configurable cache-line size up to 256]! will accommodate future architectures, and Expansion ROMfFlash
`support allows for disklas system booting. Non-PC applications are supported via programmable big and little
`end'tan modes. Host based communication has been utilized to provide the best system performance possible.
`
`The INIC supports Plug-N—Play aumonfiguration through the PCI configuration space. External pull-up and
`pull-down resistors. on the mention-y no pins, allow selection of various features during chip reset. Support of
`an external eeprorn allows for local storage of configuration information such as Mac addressee.
`
`External SDram provides frame buffering. which is configurable as 4MB, 8MB, 16MB or 32MB using the
`appropriate SIMMs. Use of -10 speed grades yields an external buffer bandwidth of 224mm. The buffer
`provides temporary storage of both incoming and outgoing frames. The protocol processor accesses the frames
`within the buffer in order to implement TCPllP and NEI'BIOS. Incoming frames are processed. assembled
`then transferred to host memory under the control of the protocol processor. For transmit. data is moved from
`host memory to buffers where various headers are created before being transported out via the Mac.
`
`
`
`"Eli-“i17%{LilHIE-l
`
`aMg;
`
`
`
`a:lliie'il'i"Ll":iii"if""
`
`Provisional Pat. App. of Alacritech, Inc.
`Inventors Laurence H. Beecher et a1.
`Express Mail Label if EH756230105US
`
`T2
`
`
`
`ALA00138458
`
`DELL Ex.1031.076
`Ex.1031.076
`
`DELL
`
`

`

`BLOCK DIAGRAM
`
`'MIIA
`
`MIIB
`
`MIIC
`
`MIID
`
`thA
`6':
`Rch
`Sen
`
`thB
`8:
`Rch
`S '
`I
`
`thC
`&
`Rch
`Se
`
`thD
`&
`Rch
`Se .
`
`
`
`
`
` «fl.iilrh“KCHI]?"fl?‘“iii3:?!:15?"U:'52"?!II]91“.!'55}!
`
`
`
`
`
`EXTERNAL
`MEMORY
`BUS
`
`“PROC
`
`lKB X 128 Sram
`& DMA Ctrl
`
`
`
`INTERFACE UNIT
`
`PCI BUS
`
`PCI BUS
`
`Provisional Pat. App. of Alacritech. Inc.
`Inventors Durance B. Boucher et a1.
`Express Mail Label a? EH756230105US
`
`'33
`
`' E @Qfifif w ,6) mm @110
`
`
`
`fi '
`
`ALA00138459
`
`DELL Ex.1031.077
`Ex.1031.077
`
`DELL
`
`

`

`OUTLINE
`
`o CoresiCeIls
`
`LSI Logic Ethernet-110 Core. mom 8-: 10133156 Mac with M1] interface.
`
`L51 Logic single port Sram, triple port Sram and ROM available.
`
`LS] Logic PCI 616MHz, 5V mmpafible [IO cell.
`
`LSI Logic PLL
`
`5‘;
`{E
`5.1
`
`5-,
`ii
`1::
`4:3
`
`5:;
`Q
`lflé
`
`:*
`-
`
`6 Die Size f Pin Count
`
`LSI Logic 610 process.
`
`MQDJILE
`
`DESEE
`
`EEEED
`
`Scratch RAM. nuns sport,
`
`4.3? 115 mm,
`
`WCS,
`MAP.
`
`ROM.
`REGS,
`Mars,
`PLL.
`
`BKX49
`123x“!
`
`sport.
`sport.
`
`6.40 ns norm,
`3.50 ns norm,
`
`5.00 as 110111.,
`6.10 ns nom.,
`
`“(149 32001,
`512x32 tpon.
`.75 mm2 x 4 =
`.5 01.11:1 a
`
`MISC LOGIC.
`TOTAL CORE
`
`117.260 gates I (5035 gates I mm” =
`
`(Core side)1
`Core side
`
`Die side
`
`Die area
`
`Pads needed
`LS! PBGA
`
`2 core side + 1.0 mm (U0 cells)
`
`= 8.5 mm x 8.5 mm
`
`: 220 signals is 1.25 (vss, vdcl)
`
`AREA
`
`06.2"? :an
`
`18.29 mm1
`00.24 mm”
`
`00.45 mm“
`03.49 mm2
`03 .30 mm"
`00.55 mm1
`
`73.29 mm”
`56.22 mm1
`
`56.22 mm2
`07.50 mm
`
`08.50 mm
`
`72.25 mm“
`
`275 pins
`272 pins
`
`=
`5
`
`=
`
`=
`
`==
`=
`
`Provisional Pat. App. of Alacrilech, Inc.
`inventors Laurence B. Boucher :1 3].
`Express Mail Label fl EH756230105US
`
`74
`
`B'QQ'IEWWfi-IHSHI
`
`ALA00138460
`
`DELL Ex.1031.078
`Ex.1031.078
`
`DELL
`
`

`

`e Datapath Bandwidth
`
`(lOMBIsIlUOB-ase) x 2 (full duplex} x 4 connections
`
`Average frame size
`Frame rate = SDMWsISIZB
`
`Cpu overhead I frame = (256 B context read) + (648 header read) +
`(1283 context write) + (1283 misc.)
`
`Total bandwidth = (51213 in) + (512B 011:) + (5123 Cpu}
`
`Dram Bandwidth required = (1 53613Iframe) 3: (156.250 framesIs)
`
`Dram Bandwidth @GOMEz = (32 bytes I 16713.5)
`
`Dram Bandwidth @ “MHz = (32 byte: I lSDns)
`
`PC] Bandwidth required
`
`PC! Bandwidth available a 30 M112, 32b, average
`
`PCl Bandwidth available @ 33 MHz, 32b, average
`
`PC] Bandwidth available @ 60 MRI, 321). average
`
`2|:
`
`PC] Bandwidth available @ 66 MHZ, 32h. average
`
`80 MBIs
`
`512 B
`
`156,150 frames I s
`
`SIZBIframe
`
`15363 I frame
`
`240M315
`
`202MBI5
`
`EMNIBIs
`
`SO‘MBIS
`
`46MBIS
`
`SGMBIS
`
`”MB-'5
`
`manners
`
`92MBIs
`
`100MBIS
`
`lflmls
`
`200MBIs
`
`m 1
`
`|
`
`I1
`
`l1
`
`PC! Bandwidth available @ 30 MHz, 64]), average
`
`PC] Bandwidth available (a 33 MHz. 64h, average
`
`PCI Bandwidth available @ 60 Mill, 64b. average
`
`PCI Bandwidth available @ 66 MHz, 64h. average
`
`1- Cpn Bandwidth
`
`Receive frame interval = 5123 I 40MBIs
`
`12.8us
`
`[instructions I frame @ 60m = films/frame) I (50ninnsn'uctinn)
`instructionsIframe
`
`Inmnctlnns I frame @ 66MB: == (12.8usfframe} I (45mlin511'ueti0n)
`instructionslfi'ame
`
`Required instructions I frame (per Clive)
`
`E
`
`150 “mathMIN
`
`
`
`,...::with"I“:iii"if~"125::1:11!iii:'Ti.‘.5“tim
`
`
`
`
`
`
`
`Provisional Pet. App. of Alaeritech, Inc.
`Inventors Laurence B. Rancher et 9.1.
`
`Express Mail Label if EH756230105US
`
`75
`
`Dianne/9
`
`"I'lfi
`
`ALA00138451
`
`DELL Ex.1031.079
`Ex.1031.079
`
`DELL
`
`

`

`. Performance Features
`
`- 512 registers improve performance through reduced scratch ram accesses and reduced instructions.
`
`- Register windowing eliminates context-switching overhead.
`
`- Separate instruction and data paths eliminate memory contention.
`
`- Totally resident control store eliminates stalling during instruction fetch.
`
`- Multiple logical processors eliminate context switching and improve realitime response.
`
`- Pipelined architecmre increases operating frequency.
`
`- Shared register and scratch ram improve inter-processor corrununication.
`
`— Fly-by state-Machine assists address compare and checkmm calculation.
`
`- 'l‘CPer—eontext caching reduces latency.
`
`- Hardware implemented queues reduce Cpu overhead and. latency.
`
`- Horizontal microcode greatly improves instruction efficiency.
`- Automatic frame DMA and status between Mac and dram buffer.
`
`- Deterministic architecture coupled with context switching eliminates processor stalls.
`
`31,;
`SW
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`9:;
`
`£3:
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`
`
`
`Provisional Pat. App. of Alacritcch. Inc.
`Inventors lantern: B. Rancher et a1.
`Express Mail label {I EH756230105US
`
`76
`
`fl'ioflinfiitifino a E o
`
`'
`
`ALA00138462
`
`DELL Ex.1031.080
`Ex.1031.080
`
`DELL
`
`

`

`PROCESSOR
`
`The processor is a convenient means to provide a progranunabie state-machine which is capable of processing
`incoming frames, processing host commands. directing network traffic and directing PCI bus traffic. Three
`processors are implemented using shared hardware in a three—level pipelinetl architecuire which launches and
`completes a single instruction for