`________________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`________________
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`DELL INC.,
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`Petitioner,
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`v.
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`ALACRITECH INC.,
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`Patent Owner
`________________
`
`Case IPR2018-00372
`U.S. Patent 7,337,241
`________________
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`PATENT OWNER’S PRELIMINARY RESPONSE
`PURSUANT TO 35 U.S.C. § 313 AND 37 C.F.R. § 42.107
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`I.
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`II.
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` Case No. IPR2018-00372
`U.S. Patent No. 7,337,241
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`TABLE OF CONTENTS
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`Page
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`INTRODUCTION .................................................................................1
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`OVERVIEW OF THE ’241 PATENT ..................................................5
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`A.
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`B.
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`The ’241 Patent Specification .....................................................5
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`The ’241 Patent Claims ............................................................ 10
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`III.
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`PROSECUTION HISTORY OF THE ’241 PATENT ...................... 15
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`IV. OVERVIEW OF THE ASSERTED PRIOR ART ............................. 17
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`A. U.S. Patent No. 5,768,618 (“Erickson”) .................................. 18
`
`B.
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`C.
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`Tanenbaum, Computer Networks, 3rd ed. (1996)
`(“Tanenbaum”) ......................................................................... 20
`
`“Gigabit Ethernet Technical Brief: Achieving End-to-
`End Performance” (“Alteon”) .................................................. 21
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`D. Dr. Min Testified He Had “No Opinion” on the Prior Art ...... 22
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`V.
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`CLAIM CONSTRUCTION ............................................................... 23
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`A. Dell’s Petition Should Be Denied Because It Alleges
`Challenged Claims 1-8 and 17-24 Are Indefinite .................... 23
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`B.
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`C.
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`“[first/second] mechanism” (claims 1-5, 7, 8, 17, 20, 23) ....... 25
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`“without an interrupt dividing” (claims 1, 18, 22) ................... 27
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`VI. THE BOARD SHOULD DENY THE PETITION BECAUSE
`IT FAILS TO DISCLOSE ALL REAL PARTIES IN
`INTEREST ......................................................................................... 28
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`A.
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`B.
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`C.
`
`D.
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`Intel Effectively Controls Dell ................................................. 30
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`The Relationship Between Intel and Dell is Sufficiently
`Close ......................................................................................... 31
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`Intel and Dell Have Coordinated Interest and Action in
`Challenging the ‘241 Patent ..................................................... 33
`
`Finding Intel is the Real Party in Interest Is Consistent
`with Legislative Intent.............................................................. 34
`
`VII. THE BOARD SHOULD DECLINE INSTITUTION UNDER
`35 U.S.C. § 325(D) BECAUSE ALL THE PRIOR ART HAS
`ALREADY BEEN CONSIDERED BY THE OFFICE ..................... 35
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`VIII. THERE IS NO REASONABLE LIKELIHOOD THAT DELL
`WILL PREVAIL UNDER GROUND 1 (OBVIOUSNESS IN
`VIEW OF ERICKSON, TANENBAUM, AND ALTEON) .............. 36
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`A.
`
`B.
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`Petitioner Has Not Shown Alteon is Prior Art ......................... 37
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`None of the References Show Validation of Layer
`Headers “Without An Interrupt Dividing the Processing”
`of the Layer Headers ................................................................ 40
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`IX. THERE IS NO REASONABLE LIKELIHOOD THAT DELL
`WILL PREVAIL UNDER GROUND 2 (OBVIOUSNESS IN
`VIEW OF ERICKSON AND TANENBAUM) ................................. 43
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`X.
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`THERE IS NO REASONABLE LIKELIHOOD THAT DELL
`WILL PREVAIL UNDER GROUND 3 (OBVIOUSNESS IN
`VIEW OF ERICKSON, TANENBAUM, AND ALTEON) .............. 47
`
`XI. ALACRITECH RESERVES ITS RIGHTS UNDER THE
`PENDING OIL STATES CASE AT THE UNITED STATES
`SUPREME COURT ........................................................................... 47
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`XII. CONCLUSION .................................................................................. 48
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`TABLE OF AUTHORITIES
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`Page
`
`Cases
`Alacritech, Inc. v. CenturyLink, Inc.,
`2:16-cv-00693-JRG-RSP (E.D. Tex.) ................................................... 1, 31
`Alacritech, Inc. v. Dell Inc.,
`2:16-cv-00695-RWS-RSP (E.D. Tex.) .................................................. 1, 31
`Alacritech, Inc. v. Wistron Corp.,
`2:16-cv-00692-JRG-RSP (E.D. Tex.) ................................................... 1, 31
`ams AG v. 511 Innovations, Inc.,
`Case IPR2016-01788 (PTAB Mar. 15, 2017) ........................................... 26
`Benson & Ford, Inc. v. Wanda Petroleum Co.,
` 833 F.2d 1172 (5th Cir. 1987) .................................................................. 36
`Bruckelmyer v. Ground Heaters, Inc.,
` 445 F.3d 1374 (Fed. Cir. 2006) ................................................................ 46
`Cox Commc’ns, Inc. v. Sprint Commc’n Co. LP,
` 838 F.3d 1224 (Fed. Cir. 2016) .......................................................... 27, 28
`In re Cronyn,
` 890 F.2d 1158 (Fed. Cir. 1989) ................................................................ 47
`In re Hall,
` 781 F.2d 897 (Fed. Cir. 1986) .................................................................. 45
`In re Steele,
` 305 F.2d 859 (CCPA 1962) ...................................................................... 26
`Nautilus, Inc. v. Biosig Instruments, Inc.,
` 134 S. Ct. 2120 (2014) ............................................................................. 30
`Oil States Energy Servs. LLC v. Greene’s Energy Group, LLC,
` Case No. 16-712 (U.S. Jun. 12, 2017)...................................................... 55
`Williamson v. Citrix Online, LLC,
` 792 F.3d 1339 (Fed. Cir. 2015) ................................................................ 27
`
`Statutory Authorities
`35 U.S.C. § 102(b) ........................................................................................ 45
`35 U.S.C. § 103(a) .......................................................................................... 1
`35 U.S.C. 112 ................................................................................................ 25
`35 U.S.C. 112(f) ............................................................................................ 25
`35 U.S.C. § 112(6) ........................................................................................ 24
`35 U.S.C. § 312(a)(2) .................................................................................... 31
`35 U.S.C. § 313 ............................................................................................... 1
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`35 U.S.C. § 314 ............................................................................................... 5
`35 U.S.C. § 314(a) ........................................................................................ 44
`35 U.S.C. § 316(e) ........................................................................................ 44
`35 U.S.C. § 325(D) ....................................................................................... 42
`
`Rules and Regulations
`37 C.F.R. § 42.8(b)(1) .................................................................................. 31
`37 C.F.R. § 42.100(b) ................................................................................... 24
`37 C.F.R. § 42.107(a) ..................................................................................... 1
`37 C.F.R. § 42.108 .......................................................................................... 5
`37 C.F.R. § 42.204(b) ................................................................................... 25
`37 C.F.R. § 42.204(b)(3) ........................................................................ 25, 26
`Office Patent Trial Practice Guide, 77 Fed. Reg. 48756 (Aug. 14,
`2012) ............................................................................ 32, 33, 35, 37, 43, 46
`
`Legislative Materials
`157 Cong. Rec. S1034 (Mar. 1, 2011) .......................................................... 40
`H.R. Rept. No 112-98 (2011) (Judiciary Committee Report on H.R.
`1249, June 1, 2011) ................................................................................... 40
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`U.S. Patent No. 7,337,241
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`PATENT OWNER’S LIST OF EXHIBITS
`
`Ex. 2001
`
`Declaration of Paul Prucnal, Ph.D.
`
`Ex. 2002
`
`Ex. 2003
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`Ex. 2004
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`Ex. 2005
`
`Ex. 2006
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`Ex. 2007
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`Ex. 2008
`
`Intel Corporation’s Motion to Intervene, Case No. 2:16-
`cv-00693-JRG-RSP, Dkt. 71 (E.D. Tex., Oct. 31, 2016).
`
`Declaration of Christopher Kyriacou, Case No. 2:16-cv-
`00693-JRG-RSP, Dkt. 71-5 (E.D. Tex., Oct. 31, 2016).
`
`Jonathan Corbet; Alessandro Rubini; Greg Kroah-
`Hartman (2005), Linux Device Drivers, 3rd edition,
`Chapter 10, “Interrupt Handling”
`
`Defendant Dell Inc.’s First Supplemental Response to
`Plaintiff’s Second Set of Common Interrogatories to
`Defendants and Intervenors (No. 11)
`
`January 13, 1997 Wayback Machine Archive of
`www.alteon.com homepage, available at
`https://web.archive.org/web/19970113130740/
`http://www.alteon.com:80/
`
`Declaration of Garland Stephens, Case No. 2:16-cv-
`00693-JRG-RSP, Dkt. 71-2 (E.D. Tex., Oct. 31, 2016).
`
`Excerpts of Declaration of Mr. Mark R. Lanning
`Regarding Claim Construction
`
`Ex. 2009
`
`Not used
`
`Ex. 2010
`
`Curriculum Vitae of Paul Prucnal, Ph.D.
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`I.
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`INTRODUCTION
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`U.S. Patent No. 7,337,241
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`Pursuant to 35 U.S.C. § 313 and 37 C.F.R. § 42.107(a), Patent Owner
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`Alacritech Inc. (“Alacritech”) submits this Preliminary Response to the Petition for
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`Inter Partes Review (“the Petition”) filed in this matter.1 Petitioner Dell Inc.
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`(“Dell”) seeks Inter Partes Review (“IPR”) of claims 1-24 of U.S. Patent No.
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`7,337,241 (“the ’241 patent”), as allegedly being unpatentable under 35 U.S.C. §
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`103(a). The ’241 patent is assigned to Alacritech and is the subject of co-pending
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`litigation, Alacritech, Inc. v. CenturyLink, Inc., 2:16-cv-00693-JRG-RSP (E.D.
`
`Tex.); Alacritech, Inc. v. Wistron Corp., 2:16-cv-00692-JRG-RSP (E.D. Tex.); and
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`Alacritech, Inc. v. Dell Inc., 2:16-cv-00695-RWS-RSP (E.D. Tex.), which were all
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`consolidated for pre-trial purposes (“the Litigation”).
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`The ’241 patent is directed to accelerated network processing using an
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`“intelligent” network interface card (INIC). Through a series of novel
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`improvements over traditional network interface cards, the claimed invention is
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`able to reduce (or completely eliminate) the number of times the host CPU is
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`interrupted when preparing new packets to be transmitted or processing received
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`1 This submission is timely as it is being filed within three months following the
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`mailing date of the Notice of Filing Date Accorded to Petition. The three-month
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`date following the January 16, 2018 mailing date is Monday, April 16, 2018.
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`(Paper No. 7.)
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`packets. As explained in more detail below, by relieving the host CPU of frequent
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`and debilitating interrupts, the claimed invention provides enhanced network and
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`system performance, faster data throughput, increased system stability, and an
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`overall better user experience.
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`In its Petition, Dell asserts that the ’241 patent is invalid on three grounds:
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`(1) that claims 1-8 of the ’241 patent are obvious over U.S. Patent No. 5,768,618 to
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`Erickson (“Erickson”) (Ex. 1005), Computer Networks, A. Tanenbaum, 3rd ed.
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`(1996) (“Tanenbaum”) (Ex. 1006), and “Gigabit Ethernet Technical Brief:
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`Achieving End-to-End Performance” by Alteon Networks (“Alteon”) (Ex. 1033);
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`(2) that claims 9-17, 19-21, and 24 of the ’241 patent are obvious over Erickson
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`and Tanenbaum; and (3) that claims 18, 22, and 23 of the ’241 patent are obvious
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`over Erickson, Tanenbaum, and Alteon. As set forth below, Dell’s Petition is
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`deficient on numerous grounds; thus, the Board should not institute this IPR on any
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`of the grounds enumerated in the Petition.
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`With respect to Ground 1, Petitioner has not established that Alteon was
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`publicly accessible prior to the October 14, 1997 priority date of the ’241 patent
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`and hence qualifies as a “printed publication.” Petitioner has therefore not met its
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`burden to show Alteon is prior art to the ’241 patent. Moreover, each of Erickson,
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`Tanenbaum, and Alteon was already considered by the Office during the original
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`prosecution of the ’241 patent. This Petition is therefore merely cumulative of the
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`arguments already considered and rejected by the Office in initial examination.
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`The Board should not second guess the Examiner and substitute its own opinion
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`for that of the Examiner. Finally, none of the references—alone or in
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`combination—show or reasonably suggest “the network layer header and the
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`transport layer header are validated without an interrupt dividing the processing of
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`the network layer header and the transport layer header,” as recited by independent
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`claim 1. Dell’s only support for this limitation is passing references to interrupts in
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`Alteon that do not describe or relate to the claimed features of (i) validating
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`network layer and transport layer headers or (ii) validating the layer headers
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`without an interrupt dividing the processing of the headers, as required by claim 1.
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`For these reasons, Ground 1 should not be instituted.
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`Ground 2, the only ground that does not rely on the Alteon reference, also
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`consists exclusively of references (Erickson and Tanenbaum) that were already
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`considered by the PTO; therefore, Petitioner’s arguments are merely cumulative to
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`arguments already considered and rejected by the Office. In addition, neither
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`Erickson nor Tanenbaum discloses the limitation “the network layer header and the
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`transport layer header are prepended at one time as a sequence of bits during the
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`prepending of each packet header” (independent claim 9), or “wherein the
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`prepending of each outbound packet header occurs without an interrupt dividing
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`the prepending of the outbound media access control layer header, the outbound
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`(IP) header and the outbound TCP header” (independent claim 17). These claims,
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`like independent claim 1, result in fewer or no interrupts to the host CPU because
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`multiple layer headers are prepended “at one time as a sequence of bits” or
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`expressly “without an interrupt” to the host CPU during the prepending of the
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`multiple headers. For these reasons, Ground 2 should not be instituted.
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`Ground 3 relies on Alteon, which Petitioner has not established qualifies as a
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`prior art “printed publication” to the challenged claims. Ground 3 should not be
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`instituted on this basis alone. Moreover, Ground 3 only includes dependent claims
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`depending from independent claim 17. Ground 3 suffers from the same
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`deficiencies as Ground 2 (which challenges claim 17) and should not be instituted
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`for at least the same reasons.
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`Accordingly, none of the references identified by Dell, either alone or in
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`combination with each other, gives rise to a reasonable likelihood that Dell will
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`prevail with respect to any challenged claim of the ’241 patent. The Board should
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`not institute review on any claim of the ’241 patent.2 See 35 U.S.C. § 314; 37
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`C.F.R. § 42.108.
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`2 Alacritech also respectfully reserves its rights under the Oil States case pending
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`before the United States Supreme Court, as set forth in Section XI of this
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`Preliminary Response.
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`II. OVERVIEW OF THE ’241 PATENT
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`A. The ’241 Patent Specification
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`The ’241 patent describes a novel system for accelerating network
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`processing. An intelligent network interface card (INIC) communicates with a
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`host computer. The INIC provides “a fast-path that avoids protocol processing for
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`most large multi-packet messages, greatly accelerating data communication.” (Ex.
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`1001 at Abstract.) In some embodiments, the INIC “contains specialized hardware
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`circuits that are much faster at their specific tasks than a general purpose CPU.”
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`(Id.)
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`As explained in the background of the ’241 patent, when a conventional
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`network interface card prepares to send data from a first host to a second host,
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`“some control data is added at each layer of the first host regarding the protocol of
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`that layer, the control data being indistinguishable from the original (payload) data
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`for all lower layers of that host.” (Id. at 3:67-4:3.) For example, an application
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`layer attaches an application layer header to the payload data and sends the
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`combined data to the presentation layer of the sending host, which receives the
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`combined data, operates on it and adds a presentation layer header to the data,
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`resulting in another combined data packet. The data resulting from combining the
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`payload data, application layer header, and presentation layer header is then passed
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`to the session layer, which performs required operations including attaching a
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`session layer header to the data and presenting the resulting combination of data to
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`the transport layer. This process continues as the information moves to lower
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`layers, with a transport layer header, network layer header, and data link layer
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`header and trailer attached to the data at each of those layers, with each step
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`typically including data moving and copying, before sending the data as bit packets
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`over the network to the second host. (Id. at 4:4-20.)
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`This process of adding a layer header to the data from the preceding layer is
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`sometimes referred to as “encapsulation” because the data and layer header is
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`treated as the data for the immediately following layer, which, in turn, adds its own
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`layer header to the data from the preceding layer. (Ex. 2001 at ¶¶ 66-67.) Each
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`layer is generally not aware of which portion of the data from the preceding layer
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`constitutes the layer header or the user data; as such, each layer treats the data it
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`receives from the preceding layer as some generic payload. (Id.)
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`(Ex. 1008, Stevens at .034, Figure 1.4 (adapted from Petition at 1).)
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`On the receiving side, the receiving host generally performs the reverse of
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`the sending process, beginning with receiving the bits from the network. Headers
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`are removed, one at a time, and the received data is processed, in order, from the
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`lowest (physical) layer to the highest (application) layer before transmission to a
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`destination within the receiving host (e.g., to the operating system space where the
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`received data may be used by an application running on the receiving host). (Ex.
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`1001 at 4:20-26.) Each layer of the receiving host recognizes and manipulates
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`only the headers associated with that layer, since to that layer the higher layer
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`header data is included with and indistinguishable from the payload data.
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`“Multiple interrupts, valuable central processing unit (CPU) processing time and
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`repeated data copies may also be necessary for the receiving host to place the data
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`in an appropriate form at its intended destination.” (Id. at 4:30-33.)
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`Because the processing of each layer typically involves a copy and data
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`manipulation operation (for example a checksum computation operation), the host
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`CPU must be “interrupted” at least one time per layer in order to process the data
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`and construct (transmit side) or deconstruct (receive side) the packet. An interrupt
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`is a signal to the processor emitted by hardware or software indicating an event
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`that needs immediate attention. (Ex. 2001 at ¶ 68.) An interrupt alerts the
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`processor to a high-priority condition requiring the interruption of the current code
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`the processor is executing. (Id.) This process involved with traditional network
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`interface cards results in “repeated copying and interrupts to the CPU” of the host
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`computer. (Ex. 1001 at 5:24-28.) When the host CPU is interrupted, it generally
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`must stop all other tasks it is currently working on, including tasks completely
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`unrelated to the network processing. (Ex. 2001 at ¶ 69.) Frequent interrupts to the
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`host CPU can be very disruptive to the host system generally and cause system
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`instability and degraded system performance. (Id.)
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`The invention of the ’241 patent includes a “fast-path” where the host CPU
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`is relieved of certain TCP/IP processing, which is instead performed by the INIC.
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`In other words, the invention “allows data from the message to be processed via a
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`fast-path which accesses message data directly at its source or delivers it directly to
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`its intended destination.” (Ex. 1001 at 5:18-22.) The fast-path “bypasses
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`conventional protocol processing of headers that accompany the data” and
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`“employs a specialized microprocessor designed for processing network
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`communication, avoiding the delays and pitfalls of conventional software layer
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`processing, such as repeated copying and interrupts to the CPU.” (Id. at 5:22-28).
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`The fast-path is shown in Figure 24 of the ’241 patent, which is reproduced
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`below. In this embodiment, the INIC performs at least the IP and TCP layer
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`processing, freeing up the CPU on the host (“client”) computer to do other tasks.
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`The fast-path also reduces or eliminates the number of interrupts sent to the CPU
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`on the host/client. The more traditional “slow-path” is also shown, where the
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`host/client is responsible for the IP and TCP layer processing. In the slow-path,
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`the CPU on the host/client is interrupted at least one time for each layer or
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`processing.
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`(Ex. 1001.026 at Fig. 24.)
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`The results of the claimed invention include more efficient network
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`processing and “a huge reduction in interrupts.” (Id. at 11:37-42.) For fast-path
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`communications, only one interrupt occurs at the beginning and end of an entire
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`upper-layer message transaction, and “there are no interrupts for the sending or
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`receiving of each lower layer portion or packet of that transaction.” (Id. at 11:42-
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`46.) As stated above, the claimed arrangement allows for enhanced network and
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`system performance, faster data throughput, increased system stability, and an
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`overall better user experience.
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`B.
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`The ’241 Patent Claims
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`The ’241 patent includes three independent claims. Independent claim 1
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`(reproduced below) recites a method for network communication. Notably, claim
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`1 recites, inter alia, “processing the packets by a first mechanism, so that for each
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`packet the network layer header and the transport layer header are validated
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`without an interrupt dividing the processing of the network layer header and the
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`transport layer header.” As described above, by preparing packets for transmission
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`using an INIC instead of the host CPU, interrupts to the host CPU can be reduced
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`or eliminated altogether. This claimed feature is not found in any of the prior art
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`cited by Petitioner.
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`Claim 1. A method for network communication, the
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`method comprising:
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`receiving a plurality of packets from the network,
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`each of the packets including a media access control
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`layer header, a network layer header and a transport
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`layer header;
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`processing the packets by a first mechanism, so
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`that for each packet the network layer header and the
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`transport layer header are validated without an interrupt
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`dividing the processing of the network layer header and
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`the transport layer header;
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`sorting
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`the packets, dependent upon
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`the
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`processing, into first and second types of packets, so that
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`the packets of the first type each contain data;
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`sending, by the first mechanism, the data from
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`each packet of the first type to a destination in memory
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`allocated to an application without sending any of the
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`media access control layer headers, network layer
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`headers or transport layer headers to the destination.
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`(Ex. 1001.142 at 98:32-49). Claim 2 depends from claim 1 and adds the further
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`limitation that the media access control layer header for each packet is processed
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`without an interrupt dividing the processing of the media access control layer
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`header and the network layer header. (Id. at 98:50-55.) Claim 3 also depends from
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`claim 1 and additionally requires that an upper layer header of at least one of the
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`packets is processed by a second mechanism, thereby determining the destination,
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`wherein the upper layer header corresponds to a protocol layer above the transport
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`layer. (Id. at 98:56-60.) Likewise, claim 4 depends from claim 1 and adds the
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`limitation that an upper layer header of at least one of the packets of the second
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`type is processed by a second mechanism, thereby determining the destination.
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`(Id. at 98:61-64.) Claim 5 depends from claim 1 and adds the limitation that a
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`transport layer header of another packet is processed by a second mechanism, prior
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`to receiving the plurality of packets from the network, thereby establishing a
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`Transmission Control Protocol (TCP) connection for the packets of the first type.
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`(Ex. 1001.142-43 at 98:65-99:3). Claim 6 recites that the sorting of the packets
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`includes classifying each of the packets of the first type as having an Internet
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`Protocol (IP) header and a Transmission Control Protocol (TCP). (Ex. 1001.143 at
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`99:4-7). Claim 7 depends from claim 1 and adds the limitation that a second
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`plurality of packets is transmitted to the network, each of the second plurality of
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`packets containing a media access control layer header, a network layer header and
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`a transport layer header, the method further including processing the second
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`plurality of packets by the first mechanism, so that for each packet the media
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`access control layer header, the network layer header and the transport layer header
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`are prepended at one time as a packet header. (Id. at 99:8-17.) Claim 8 specifies
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`that the first mechanism is a sequencer running microcode. (Id. at 99:18-19.)
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` Independent claim 9 (reproduced below) recites a method for
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`communicating information over a network. Notably, claim 9 recites, inter alia,
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`“wherein the network layer header is Internet Protocol (IP), the transport layer
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`header is Transmission Control Protocol (TCP) and the media access control layer
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`header, the network layer header and the transport layer header are prepended at
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`one time as a sequence of bits during the prepending of each packet header.” As
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`described above, by preparing packets for transmission using an INIC instead of
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`the host CPU, multiple headers can be prepended at one time instead of
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`interrupting the host CPU between each header operation. This claimed feature is
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`not found in any of the prior art cited by Petitioner.
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`Claim 9. A method for communicating information over
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`a network, the method comprising:
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`
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`obtaining data from a source in memory allocated
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`by a first processor;
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`dividing the data into multiple segments;
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`prepending a packet header to each of the
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`segments by a second processor, thereby forming a
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`packet corresponding to each segment, each packet
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`header containing a media access control layer header, a
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`network layer header and a transport layer header,
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`wherein the network layer header is Internet Protocol
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`(IP), the transport layer header is Transmission Control
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`Protocol (TCP) and the media access control layer
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`header, the network layer header and the transport layer
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`header are prepended at one time as a sequence of bits
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`during the prepending of each packet header; and
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`
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`transmitting the packets to the network.
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`(Ex. 1001.143 at 99:19-35.)
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`Independent claim 17 (reproduced below) recites a method for
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`communicating information over a network. Notably, claim 17 recites, inter alia,
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`“prepending, by the second mechanism, an outbound packet header to each of the
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`segments . . . wherein the prepending of each outbound packet header occurs
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`without an interrupt dividing the prepending of the outbound media access control
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`layer header, the outbound (IP) header and the outbound TCP header.” This
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`claimed feature is not found in any of the prior art cited by Petitioner.
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`Claim 17. A method for communicating information
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`over a network, the method comprising:
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`
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`providing, by a first mechanism, a block of data
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`and a Transmission Control Protocol (TCP) connection;
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`
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`dividing, by a second mechanism, the block of data
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`into multiple segments;
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`prepending, by
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`the second mechanism, an
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`outbound packet header to each of the segments, thereby
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`forming an outbound packet corresponding to each
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`segment, the outbound packet header containing an
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`outbound media access control
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`layer header, an
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`outbound Internet Protocol (IP) header and an outbound
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`TCP header, wherein the prepending of each outbound
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`packet header occurs without an interrupt dividing the
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`prepending of the outbound media access control layer
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`header, the outbound (IP) header and the outbound TCP
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`header; and
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`transmitting the outbound packets to the network.
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`(Ex. 1001.143 at 100:3-18.)
`III. PROSECUTION HISTORY OF THE ’241 PATENT
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`The ’241 patent issued on February 26, 2008. It was filed on September 27,
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`2002 as Application No. 10/260,878 as a continuation of Application No.
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`10/092,967 filed March 6, 2002, which in turn claims the benefit of Application
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`No. 10/023,240, filed December 15, 2001, which in turn claims the benefit of
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`Application No. 09/464,283, filed December 15, 1999, which in turn claims the
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`benefit of Application No. 09/439,603, filed November 12, 1999, which in turn
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`claims the benefit of Application No. 09/067,544, filed April 27, 1998, which in
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`turn claims the benefit of Provisional Application No. 60/061,809, filed on Oct.
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`14, 1997.3
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`The ’241 patent was subject to a thorough examination by Examiners Eric J.
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`Kuiper and Jerry B. Dennison, who allowed the application on July 30, 2007 after
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`two rounds of claim amendments and arguments. (Ex. 1002 at 597-602.) In
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`connection with claim 1, the applicants explained that the prior art of record did
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`not “teach any processing of a network layer header or a transport layer header, let
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`alone ‘processing the packets by a first mechanism, so that for each packet the
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`network layer header and the transport layer header are validated without an
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`interrupt dividing the processing of the network layer header and the transport
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`layer header.’” (Id. at 333-334 (emphasis added).)
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`Similar arguments were made with response to independent claims 9 and 17.
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`(Id. at 341-43, 345-46.) In connection with claim 9, the applicants argued that the
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`prior art of record did not show or suggest “wherein the prepending of each packet
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`header occurs without an interrupt dividing the prepending….” (Id. at 342
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`(emphasis added).)4 In connection with claim 17, the applicants argued that the
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`3 See Ex. 1001.094 at 1:8-2:23 for a listing of other related applications.
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`4 In response to the second Office Action, the interrupt language was replaced
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`with language requiring “the network layer header and the transport layer header
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`are prepended at one time as a sequence of bits during the prepending….” (Ex.
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`prior art of record did not show or suggest “the processing and validating of these
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`headers all occurring without interrupts