`
`t
`
`let a highly-active interface lock out the others (which would happen with a single
`queue).
`The transmit request may be a segment that is less than the MSS, or it may be as.much as
`a full 64K SMB READ. Obviously the fonner request will go out as one segment, the
`latter as a number ofMSS-sized segments. The transmitting TCB must hold on tp the
`request until all data in it has been transmitted and acked. Appropriate pointers to do this
`will be kept in the TCB. A large buffer is acquired from the free buffer fifo, and the MAC
`and TCP/IP headers are created in it. It may be quicker/simpler to keep a basic frame
`header set up in the TCB and either dma directly this into the frame each time. Then data
`is dmad from host memory into the frame to create an MSS-sized segment. This dma also
`checksums the data. Then the checksum is adjusted for the pseudo-header and placed into
`the TCP header, and the frame is queued to the MAC transmit interface which may be
`controlled by the third sequencer. The final step is to update various window fieids etc in
`the TCB. Eventually either the entire request will have been sent and acked, or a
`retransmission timer will expire in which case the context is flushed to the host. In either
`case, the INIC will place a command response in the Response queue containing the
`command buffer handle from the original transmit command and appropriate st&tus.
`The above discussion has dealt how an actual transmit occurs. However the real
`challenge in the transmit processor is to determine whether it is appropriate to transmit at
`the time a transmit request arrives. There are many reasons not to transmit: the receiver's
`window size is <= 0, the Persist timer has expired, the amount to send is less thap a full
`segment and an ACK is expected I outstanding, the receiver's window is not half-open
`etc. Much of the transmit processing will be in determining these conditions.
`
`5.3.4 Transmit Details - No Valid Context
`
`The main difference between this and a context-based transmit is that the queued request
`here will already have the appropriate MAC and TCP/IP (or whatever) headers in the
`frame to be output. Also the request is guaranteed not to be greater than MSS-sized in
`length. So the processing is fairly simple. A large buffer is acquired and the frame is
`dmad into it, at which time the checksum is also calculated. If the frame is TCP/IP, the
`checkswn will be appropriately adjusted ifnecessary (pseudo-header etc) and pfaced in
`the TCP header. The frame is then queued to the appropriate MAC transmit intepace.
`Then the command is immediately responded to with appropriate status through the
`Response queue.
`
`5.3.5 Transmit Notes
`
`1. Slow-start: the INIC will handle the slow-start algorithm that is now a part of the
`TCP standard. This obviates waiting until the connection is sending a full-rate
`before passing it to the INIC.
`2. Window Probe vs Window Update: an explanation for posterity . ...
`A Window Probe is sent from the sending TCB to the receiving TCB, and it means the
`sender has the receiver in PERSIST state. Persist state is entered when the receiver
`advertises a zero window. It is tbus the state of the transmitting TCB. In this state, be
`sends periodic window probes to the receiver in case an ACK from the receiver bas been
`lost The receiver will return his latest window size in the ACK.
`
`Provisional Pat. App. of Alacritech, Inc.
`Inventors Laurence B. Boucher et al.
`Express Mail Label# EH756230105US
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`57
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`ALA00138443
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`Ex.1031.061
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`DELL
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`A Window Update is sent from the receiving TCB to the sending TCB, usually to tell him
`that the receiving window has altered. It is mostly triggered by the upper layer when it
`accepts some data. This probably means the sending TCB is viewing the receiving TCB
`as being in PERSIST state.
`3. Persist state: it is designed to handle Persist state on the INIC. It seems
`unreasonable to throw a TCB back to the host just because its receiver advertised a
`zero window. This would nonnally be a transient situation, and would tent-1 to
`happen mostly with clients that do not support slow-start. Alternatively, tl:i.e code
`can easily be changed to throw the TCB back to the host as soon as a receiver
`advertises a zero window.
`4. MSS-sized frames: the INIC code will expect all transmit requests for which it has
`no TCB to not be greater than the MSS. If any request is, it will be dropped and an
`appropriate response status posted.
`S. Silly Window avoidance: as a receiver, the INIC will do the right thing here and
`not advertise small windows - this is easy. However it is necessary to also do
`things to avoid this as a sender, for the cases where a stupid client does advertise
`small windows. Without getting into too much detail here, the mechanism requires
`the INIC code to calculate the largest window advertisement ever advertised by the
`other end. It is an attempt to guess the size of the other end's receive buffer and
`assumes the other end never reduces the size of its receive buffer. See Stevens Vol.
`l pp. 325-326.
`
`6 The Utility Processor
`
`6.1 Summary
`
`The following is a summary of the main functions of the utility sequencer of the
`microprocessor:
`
`look at the event queues: Eventl3Type & Event23Type (we assume there will be an
`•
`event status bit for this -
`USE_EV13 and USE_EV23) in the events register; these
`are events from sequencers 1 and 2; they will mainly be XMIT requests from the XMT
`sequencer. Dequeue request and place the frame on the appropriate interface.
`• RCV-frame support: in the model, RCV is done through VinicReceiveO which is
`registered by the lower-edge driver, and is called at dispatch-level. This routine calls
`VinicTransferDataCompleteO to check if the xfer (possibly DMA) of the frame into host
`buffers is complete. Tue latter rtne is also called at dispatch level on a DMA-coi;npletion
`interrupt. It queues complete buffers to the RCV sequencer via the nonnal queue
`mechanism.
`• Other processes may also be employed here for supporting the RCV sequencer.
`•
`service the following registers: (this will probably involve micro-interrupts)
`Header Buffer Address register:
`buffers are 256 bytes long on 2?6-byte boundaries.
`31-8 - physical addr in host of a set of
`contiguous hddr buffers
`7-0 - number ofhddr buffers passed.
`Use contents to add to SmallHType queue
`
`Provisional Pat. App. of Alacritech, Inc.
`Inventors Laurence B. Boucher et al.
`Express Mail Label# EH75623010SUS
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`58
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`ALA001 38444
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`Ex.1031.062
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`DELL
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`...
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`Data Buffer Handle & Data Buffer Address registers:
`buffers are 4K long aligned on 4K boundaries ...
`Use contents to add to the FreeType queue.
`
`Command Buffer Address register:
`buffers are multiple of32 bytes up to lK long (2**5 • 32)
`31-5 - physical add.r in host of cmd buffer
`4-0 - length of cmd in bytes/32
`(i.e. multiples of32 bytes)
`Points to host cmd; get FreeSType buffer and move
`command into it; queue to Xmit0-Xmit31'ype queues.
`
`Response Buffer Address register:
`buffers are 32 bytes long on 32-byte boundaries
`31-8 - physical addr in host of a set of
`contiguous resp buffers
`7-0 - number of resp buffers passed.
`Use contents to add to the ResponseType queue.
`
`low buffer threshold support: set approp bits in the ISR when the available-buffers
`•
`count in the various queues filled by the host falls below a threshold.
`
`6.2 Further Operations of the Utility Processor
`
`The utility processor of the microprocessor housed on the INIC is responsible for setting
`up and implementing all configuration space and memory mapped operations, and also as
`described below, for managing the debug interface.
`
`All data transfers, and other INlC initiated transfers will be done via OMA.
`Configuration space for both the network processor function and the utility processor
`function will define a single memory space for each. This memory space will d~fine the
`basic commwtlcation structure for the host. In general, writing to one of these memory
`locations will perform a request for service from the INIC. This is detailed in t.l1e
`memory description for each function. This section defines much of the operatibn of the
`Host interface, but should be read in conjunction with the Host lnterface Strategy for the
`Alacritech INIC to fully define the Host/INIC interface.
`
`Two registers, DMA hardware and an interrupt function comprise the INIC interface to
`the Host through PCI. The interrupt function is implemented via a four bit register
`(PCl_INT) tied to the PCI interrupt lines. This register is directly accessed by the
`microprocessor.
`
`THE MICROPROCESSOR uses two registers, the PCI_Data_Reg and the
`PCI_Address_Reg, to enable the Host to access Configuration Space and the memory
`space allocated to the INIC. These registers are not available to the HosL but are used by
`THE MICROPROCESSOR to enable Host reads and writes. The function of these two
`registers is as follows.
`
`Provisional Pat. App. of Alacritecb, Inc.
`Inventors Laurence B. Boucher et al.
`Express Mail Label# EH756230105US
`
`59
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`ALA001 38445
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`Ex.1031.063
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`DELL
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`LohTOT"ensraooag
`
`processorwill construct the data required and transfer it. Reads to this memory will
`generate 00 for data.
`
`6.2.2.1 Network Processor
`
`The following four byte registers, beginning at location h00 of the network processor’s
`allocated memory, are defined.
`
`00— Interrupt Status Pointer -- Initialized by the hostto point to a four byte area
`wherestatus is stored
`04— Interrupt Status — Returned status from host. Sent after one or more
`status conditions have been reset. Also an interlock for storing any
`new status. Oncestatus has been stored at the Interrupt Status Pointer
`location, no new status will be stored until the host writes the Interrupt
`Status Register. New status will be ored with any remaining
`uncleared status (as defined by the contents of the returned status)
`and stored again at the Interrupt Status Pointer location. Bits are
`as follows:
`Bit 31 -ERR - Errorbits are set
`Bit 30 — RCV — Receive has occurred
`Bit 29 — XMT — Transmit command complete
`Bit 25 — RMISS — Receive drop occurred due to no buffers
`
`08— Interrupt Mask — Written by the host. Interrupts are masked for each
`of the bits in the interrupt status when the samebit in the mask
`register is set. When the Interrupt Mask register is written and as
`a result a status bit is unmasked, an interruptis generated. Also,
`whenthe Interrupt Status Register is written, enabling new status
`to be stored, when it is stored if a bit is stored that is not masked
`by the Interrupt Mask,an interrupt is generated.
`
`OC— Header Buffer Address — Written by host to pass a set of header buffers to the
`INIC.
`
`10- Data Buffer Handle — First register to be written by the Hostto transfer a receive
`data buffer to the INIC. This data is Host reference data. It is not used by the
`INIC, it is returned with the data buffer. However,to insure integrity of the
`buffer, this register must be interlocked with the Data Buffer Addressregister.
`Once the Data Buffer Addressregister has been written, neither register can be
`written until after the Data Buffer Handle register has been read by THE
`MICROPROCESSOR.
`
`14— Data Buffer Address -— Pointer to the data buffer being sent to the INIC by the
`Host. Must be interlocked with the Data Buffer Handle
`register.
`
`18— Command Buffer Address XMTO — Pointer to a set of command
`buffers sent by the Host. THE MICROPROCESSORwill DMA the buffers to
`local DRAM found on the FreeSType queue and queue the Command
`
`Provisional Pat. App. of Alacritech, Inc.
`Inventors Laurence B. Boucher et al.
`Express Mail Label # EH756230105US
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`63
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`Buffer Address XMTO with the local address replacing the host
`Address.
`
`1C— Command Buffer Address SMT1
`
`20— Command Buffer Address SMT2
`
`24-— Command Buffer Address SMT3
`
`28— Response Buffer Address -- Pointer to a set ofresponse buffers sent
`by the Host. These will betreated in the same fashion as the
`Command Buffer Address registers.
`
`6.2.2.2 Utility Processor
`
`Ending status will be handled by theutility processorin the samefashion as it is handled
`by the network processor. At present two ending status conditions are defined B31 —
`command complete, and B30 -— error. Whenendstatus is stored an interrupt is
`generated.
`
`Two additional registers are defined, Command Pointer and Data Pointer. The Host is
`responsible for insuring that the Data Pointer is valid and points to sufficient memory
`before storing a commandpointer. Storing a command pointer initiates command decode
`and execution by the debug processor. The Host must not modify either command or
`Data Pointer until ending status has been received, at which point a new command may
`be initiated. Memory space is write only by the Host, reads will receive 00. The format
`is as follows:
`
`00-— InterruptStatus Pointer -- Initialized by the host to pointto a four byte area
`where status is stored
`
`04— Interrupt Status — Returned status from host. Sent after one or more
`status conditions have been reset. Also an interlock for storing any
`new status. Once status has been stored at the Interrupt Status Pointer
`location, no new status will be stored until the host writes the Interrupt
`Status Register. New status will be ored with any remaining
`uncleared status (as defined by the contents of the returned status)
`and stored again at the Interrupt Status Pointer location. Bits are
`as follows:
`
`Bit 31 — CC —- Command Complete
`Bit 30 - ERR -- Error
`Bit29 — Transmit Processor Halted
`Bit28 — Receive Processor Halted
`Bit27 — Utility Processor Halted
`
`eeaa|
`
`08— Interrupt Mask — Written by the host. Interrupts are masked for each
`of the bits in the interrupt status when the samebit in the mask
`register is set. When the Interrupt Mask register is written and as
`a result a status bit is unmasked, an interrupt is generated. Also,
`
`Provisional Pat. App. of Alacritech, Inc.
`Inventors Laurence B. Boucheretal.
`Express Mail Label # EH756230105US
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`64
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`2 Gane ”Sosnat
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`ALA00138450
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`Ex.1031.068
`DELL Ex.1031.068
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`DELL
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`i
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`Zaher"oRese
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`when the Interrupt Status Register is written, enabling new status
`to be stored, when itis stored if a bit is stored that is not masked
`by the Interrupt Mask, an interrupt is generated.
`
`0C— CommandPointer — Points to commandto be executed. Storing
`this pointer initiates command decode and execution.
`
`10-— Data Pointer — Points to the data buffer. This is used for both read and write data,
`determined by the command function.
`
`7 Debug Interface
`
`In order to provide a mechanism to debug the microcode running on the microprocessor
`sequencers, a debug process has been defined which will run on the utility sequencer.
`This processor will interface with a control program on the host processor over PCI.
`
`71
`
`PCI Interface
`
`This interface is defined in the combination of the Utility Processor and the Host
`Interface Strategy sections, above.
`
`7.2 Command Format
`
`The first byte of the command, the commandbyte,defines the structure of the remainder
`of the command. The first five bits of the command byte are the commanditself. The
`nextbit is used to specify an alternate processor, and thelast two bits specify which
`processors are intended for the command.
`
`7.2.1. Command Byte
`
`7-3
`Command
`
`2
`Alt. Proc.
`
`1-0
`Processor
`
`7.2.2 Processor Bits
`
`00 — Any Processor
`01 — Transmit Processor
`10 — Receive Processor
`11 — Utility Processor
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`Provisional Pat. App. of Alacritech, Inc.
`Inventors Laurence B. Boucheret al.
`
`Express Mail Label # EH756230105US
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`ALA00138451
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`Ex.1031.069
`DELL Ex.1031.069
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`DELL
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`7.2.3 Alternate Processor
`
`This bit defines which processor should handle debug processingifthe utility processor
`is defined as the processor in debug.
`
`0— Transmit Processor
`1 — Receive Processor
`
`7.24 Single Byte Commands
`
`00 — Halt
`
`This command asynchronously halts the processor.
`
`08 — Run
`
`This commandstarts the processor.
`
`10 —Step
`
`This command steps the processor.
`
`7.2.5 Eight Byte Commands
`
`18 — Break
`
`0
`Command
`
`1
`Reserved
`
`2-3
`Count
`
`4-7
`Address
`
`This command sets a stop at the specified address, A count of 1 causes the specified
`processorto halt the first time it executes the instruction. A count of 2 or more'causes the
`processorto halt after that number of executions. The processoris halted just before
`executingthe instruction. A count of 0 does not halt the processor, but causes a sync
`signal to be generated. If a second processoris set to the same break address, the count
`data from the first break request is used, and each time either processor executes the
`instruction the count is decremented.
`
`20 — Reset Break
`
`Command
`
`Reserved
`
`Address
`
`q aFRESaCaaSh
`seae"ey
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`Provisional Pat. App. of Alacritech, Inc.
`Inventors Laurence B, Boucheretal.
`Express Mail Label # EH756230105US
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`66
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`2 Gap) 4 2M
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`O88 Hawt
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`ALA00138452
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`Ex.1031.070
`DELL Ex.1031.070
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`DELL
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`This command resets a previously set break point at the specified address. Reset break
`fully resets that address. If multiple processors were setto that break point, all will be
`reset.
`
`28 — Dump
`
`0
`Command
`
`1
`Descriptor
`
`2-3
`Count
`
`4-7
`Address
`
`This commandtransfers to the host the contents of the descriptor. For descriptors larger
`than four bytes, a count, in four byte increments is specified. For descriptors utilizing an
`address the address field is specified.
`
`7.2.6 Descriptor
`
`00 — Register
`
`This descriptor uses both count and address fields. Both fields are four byte based (a
`count of 1 transfers four bytes).
`
`01 —Sram
`
`This descriptor uses both count and address fields. Count is in four byte blocks. Address
`is in bytes, butif it is not four byte aligned, it is forced to the lower four byte aligned
`address.
`
`02 —Dram
`
`This descriptor uses both count and address fields. Countis in four byte blocks. Address
`is in bytes, butif it is not four byte aligned, it is forced to the lower four byte aligned
`address
`
`03 — Cstore
`
`This descriptor uses both count and address fields. Countis in four byte blocks. Address
`is in bytes, but if it is not four byte aligned,it is forced to the lower four byte aligned
`address
`
`Stand-alone descriptors:
`
`The following descriptors do not use either the count or address fields. They transfer the
`contents of the referenced register.
`
`04 — CPU_STATUS
`
`05-—PC
`
`aAhTae"BSSat
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`Provisional Pat. App. of Alacritech, Inc.
`Inventors Laurence B. Boucher et al.
`Express Mail Label # EH756230105US
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`67
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`ALA00138453
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`Ex.1031.071
`DELL Ex.1031.071
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`DELL
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`06 —- ADDR_REGA
`
`07 -ADDR_REGB
`
`08 -RAM_BASE
`
`09 — FILE_BASE
`
`0A-—INSTR_REG_L
`
`0B —INSTR_REGH
`
`0C~MAC_DATA
`
`0D —DMA_EVENT
`
`OE ~ MISC_EVENT
`
`OF -Q_IN_RDY
`
`10~QOUT_RDY
`
`11-LOCK STATUS
`
`12 —STACK- This returns 12 bytes
`
`13—Sense_ Reg
`
`This register contains four bytes of data. If error status is posted for a command, if the
`next commandthat is issued reads this register, a code describing the error in more detail
`may be obtained. If any commandother than a dumpofthis register is issued after error
`status, sense information will be reset.
`
`30 — Load
`
`0
`Command
`
`1
`Descriptor
`
`2-3
`Count
`
`4-7
`Address
`
`This commandtransfers from the host the contents of the descriptor. For descriptors
`larger than four bytes, a count, in four byte incrementsis specified. For descriptors
`utilizing an address the address field is specified.
`
`ACSAOC"UESoo
`
`7.2.7 Descriptor
`
`00 — Register
`
`This descriptor uses both countand address fields. Both fields are four byte based.
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`Provisional Pat. App. of Alacritech, Inc.
`Inventors Laurence B. Boucher et al.
`
`Express Mail Label # EH756230105US
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`Ex.1031.072
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`01 -—Sram
`
`This descriptor uses both count and address fields. Countis in four byte blocks. ; Address
`is in bytes, but if it is not four byte aligned,it is forced to the lowerfour byte aligned
`address.
`
`02 - Dram
`
`This descriptor uses both count and addressfields. Count is in four byte blocks. Address
`is in bytes, but if it is not four byte aligned,it is forced to the lower four byte aligned
`address
`
`03 — Cstore
`
`This descriptor uses both count and address fields. Count is in four byte blocks. Address
`is in bytes, but if it is not four byte aligned, it is forced to the lower four byte aligned
`address. This applies to WCS only.
`
`Stand-alone descriptors:
`
`The following descriptors do not use either the count or address fields. They transfer the
`contents of the referenced register.
`
`04—- ADDR_REGA
`
`05 —- ADDR_REGB
`
`06 -RAM_BASE
`
`07 — FILE_BASE
`
`08 -MAC_DATA
`
`09~-QINRDY
`
`0A-Q_OUT_RDY
`
`0B —- DBG_ADDR
`
`38 — Map
`
`AisTOT"SOSTfaooS
`
`This commandallowsan instruction in ROM to be replaced by an instruction in WCS.
`The new instruction will be located in the Host buffer. It will be stored in the first eight
`bytes of the buffer, with the high bits unused. To reset a mapped out instruction, map it
`to location 00.
`
`0
`Command
`
`l=3
`Address to
`Map To
`
`4-7
`Address to
`Map Out
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`Provisional Pat, App. of Alacritech, Inc.
`Inventors Laurence B. Boucheretal.
`Express Mail Label # EH756230105US
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`HARDWARE SPECIFICATION
`
`FEATURES
`
`* Peripheral Component Interconnect (PCI) Interface
`
`- Universal PCI interface supports both 5,0V and 3,3¥ signaling environments,
`
`- Supports both 32-bit and 64 bit PCI interface.
`
`- Supports PCI clock frequencies from 15MHz to 66MHz
`
`- High performance bus mastering architecture.
`
`- Host memory based communications reduce register accesses,
`
`- Host memory based interruptstatus word reduces register reads.
`
`- Plug and Play compatible.
`
`- PCIspecification revision 2.1 compliant.
`
`- PCI bursts up to 512 bytes.
`
`- Supports cache line operations up to 128 bytes.
`
`- Both big-endian andlittle-endian byte alignments supported.
`
`- Supports Expansion ROM.
`
`« Network Interface
`
`- Four internal 802.3 and ethernet compliant Macs.
`
`- Media Independent Interface (MII) supports external PHYs.
`
`- 1OBASE-T, 100BASE-TX/FX and 100BASE-T4 supported.
`
`- Full and half-duplex modes supported.
`
`- Automatic PHY status polling notifies system of status change.
`~ Provides SNMPsialistics counters.
`
`- Supports broadcast and multicast packets.
`
`4T°OEPSire
`
`tinto
`
`- Provides promiscuous mode for network monitoring or multiple unicast address detection.
`
`- Supports “huge packets” up to 32KB.
`
`- Mac-layer loop-back test mode.
`
`- Supports auto-negotiating Phys.
`
`Provisional Pat. App. of Alacritech, Inc.
`Inventors Laurence B. Boucheretal.
`Express Mail Label # EH756230105US
`
`70
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`2 ean?” sMosaehant
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`ALA00138456
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`Ex.1031.074
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`DELL
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`* Memory Interface
`
`- External Dram buffering of transmit and receive packets.
`
`- Buffering configurable as 4MB, 8MB, 16MB or 32MB.
`
`- 32-bit interface supports throughput of 224MB/s
`
`- Supports external FLASH ROM upto 4 MB, for diskless boot applications.
`
`~ Supports external serial EEPROM for custom configuration and Mac addresses,
`
`* Protocol Processor
`
`- High speed, custom, 32-bit processor executes 66 million instructions per second.
`
`- Processes IP, TCP and NETBIOSprotocols.
`
`- Supports up to 256 resident TCP/IP contexts.
`
`- Writable control store (WCS)allows field updates for feature enhancements.
`
`StainCRE"ROGERIESpphSyi 0
`
`he
`
`« Power
`
`- 3.3V chip operation.
`
`- PCI controlled 5.0V/3.3V I/O cell operation.
`
`¢ Packaging
`
`- 272-pin plastic ball grid array.
`
`- 91 PCIsignals.
`
`- 68 MII signals.
`
`- 58 external memory signals.
`
`- 1 clock signal.
`
`- 54 signals split between power and ground.
`
`- 272 total pins.
`
`Provisional Pat. App. of Alacritech, Inc.
`Inventors Laurence B. Boucher et al.
`Express Mail Label # EH756230105US$
`
`71
`
`sap?’sMosasihat
`
`ALA00138457
`
`Ex.1031.075
`DELL Ex.1031.075
`
`DELL
`
`
`
`GENERAL DESCRIPTION
`
`The microprocessor is a 32-bit, full-duplex, four channel, 10/100-Megabit per second (Mbps),Intelligent
`Network Interface Controller, designed to provide high-speed protocol processing for server applications. It
`combines the functions of a standard network interface controller and a protocol processor within a single
`chip. Although designed specifically for server applications, The microprocessor can be used by: PCs,
`workstations and routers or anywhere that TCP/IP protocols are being utilized.
`
`When combined with four 802.3/MII compliant Phys and Synchronous Dram (SDram), the INIC comprises
`four complete ethernet nodes. It contains four 802.3/ethernet compliant Macs, a PCI Bus Interface Unit (BIU),
`a Memory controller, transmit fifos, receive fifos and a custom TCP/IP/NETBIOSprotocol processor. The
`INIC supports 10Base-T , 100Base-TX, 100Base-FX and 100Base-T4 via the MII interface attachment of
`appropriate Phys.
`
`The INIC Macs provide statistical information that may be used for SNMP. The Macs operate in promiscuous
`mode allowing the [NIC to function as a network monitor, receive broadcast and multicast packets and
`implement multiple Mac addresses for each node.
`
`Any 802.3/MII compliant PHY can be utilized, allowing the INIC to support 1OBASE-T, 1OBASE-T2,
`100BASE-TX, 100Base-FX and 100BASE-T4 as well as future interface standards. PHY identification and
`initialization is accomplished through host driver initialization routines. PHY status registers can be polled
`continuously by the INIC and detected PHY status changes reported to the host driver. The Mac can be
`configured to support a maximum frame size of 1518 bytes or 32768 bytes.
`
`.
`
`The 64-bit, multiplexed BIU provides a direct interface to the PCI busfor both slave and master functions.
`The INICis capable of operating in either a 64-bit or 32-bit PCI environment, while supporting 64-bit
`addressing in either configuration. PCI bus frequencies up to 66MHz are supported yielding instantaneous bus
`transfer rates of 533MB/s. Both 5.0V and 3.3V signaling environments can be utilized by the INIC.
`Configurable cache-line size up to 256B will accommodate future architectures, and Expansion ROM/Flash
`support allows for diskless system booting. Non-PC applications are supported via programmablebig and little
`endian modes. Host based communication has been utilized to provide the best system performance possible.
`
`The INIC supports Plug-N-Play auto-configuration through the PCI configuration space. External pull-up and
`pull-down resistors, on the memory I/Opins, allow selection of various features during chip reset. Support of
`an external eeprom allows for local storage of configuration information such as Mac addresses.
`
`External SDram provides frame buffering, which is configurable as 4MB, 8MB, 16MB or 32MB usingthe
`appropriate SIMMs. Use of -10 speed grades yields an external buffer bandwidth of 224MB/s. The buffer
`provides temporary storage of both incoming and outgoing frames. The protocol processor accesses the frames
`within the buffer in order to implement TCP/IP and NETBIOS. Incoming frames are processed, assembled
`then transferred to host memory under the control of the protocol processor. For transmit, data is moved from
`host memory to buffers where various headers are created before being transmitted out via the Mac.
`
`BraooS
`ohLonFOE"
`
`Provisional Pat. App. of Alacritech, Inc.
`Inventors Laurence B. Boucheretal.
`Express Mail Label # EH756230105US
`
`72
`
`2) BpS| 2
`
`
`
`obese Hawt
`
`ALA00138458
`
`Ex.1031.076
`DELL Ex.1031.076
`
`DELL
`
`€
`
`
`BLOCK DIAGRAM
`
`MITA
`
`MIIB
`
`MIIC
`
`MIID
`
`XmtA
`&
`RevA
`Sec
`
`2GTieBoeEeagcs
`
`uPROC
`
`XmtB
`&
`RevB
`Seq
`
`XmtC
`&
`RevC
`Seq
`
`XmtD
`&
`RevD
`Seq
`
`EXTERNAL
`MEMORY
`BUS
`
`1KB X 128 Sram
`
`& DMA Ctrl
`
`INTERFACE UNIT
`
`PCI BUS
`
`PCI BUS
`
`Provisional Pat. App. of Alacritech, Inc.
`Inventors Laurence B. Boucheretal.
`Express Mail Label # EH756230105US
`
`73
`
`
`
`Peep” sobe
`
`im
`
`ALA00138459
`
`Ex.1031.077
`DELL Ex.1031.077
`
`DELL
`
`
`
`OUTLINE
`
`e Cores/Cells
`
`LSI Logic Ethernet-110 Core, 100Base & 10Base Mac with MII interface.
`
`LSI Logic single port Sram,triple port Sram and ROM available.
`
`LSI Logic PCI 66MHz, SV compatible I/O cell.
`
`LSI Logic PLL
`
`« Die Size / Pin Count
`
`LSI Logic G10 process.
`
`MODULE
`
`DESCR
`
`SPEED
`
`Scratch RAM,
`
`1Kx128 sport,
`
`4.37 ns nom.,
`
`Wcs,
`
`MAP,
`ROM,
`
`REGs,
`Macs,
`
`PLL,
`
`8Kx49 sport,
`
`6.40 ns nom.,
`
`sport,
`128x7
`1Kx49 32col,
`
`3.50 ns nom.,
`5.00 ns nom.,
`
`6.10 ns nom.,
`
`512x32 tport,
`75 mn’ x 4 =
`
`Smm =
`
`MISC LOGIC,
`
`117,260 gates / (5035 gates /mm? =
`
`AREA
`
`06.77 mm?
`
`18.29 mm*
`
`00.24 mm?
`00.45 mm?*
`
`03.49 mm*
`03.30 mm*
`
`00.55 mm?
`
`23.29 mm?
`
`(Core side)*
`Core side
`
`Die side
`
`Die area
`
`Pads needed
`LSI PBGA
`
`= core side + 1.0mm (I/O cells)
`
`= 8.5 mmx 8.5 mm
`
`= 220 signals x 1.25 (vss, vdd)
`
`=
`=
`
`=
`
`=
`
`=
`=
`
`56.22 mm’
`07.50 mm
`
`08.50 mm
`
`72.25 mom
`
`275 pins
`272 pins
`
`ra
`
`FROSa ie
`FiiheOE"Gig
`
`OTALCORE|S56.22mmz=°°=
`
`Provisional Pat. App. of Alacritech, Inc.
`Inventors Laurence B. Boucheret al-
`Express Mail Label # EH756230105US
`
`74
`
`eps v sSMose|hat
`
`ALA00138460
`
`Ex.1031.078
`DELL Ex.1031.078
`
`DELL
`
`
`
`e Datapath Bandwidth
`
`(10MB/s/100Base) x 2 (full duplex) x 4 connections
`
`Average frame size
`Frame rate = 80MB/s / 512B
`
`=
`
`=
`=
`
`80 MB/s
`
`512B
`
`156,250 frames / s
`
`Cpu overhead / frame = (256 B context read) + (64B header read) +
`(128B context write) + (128B misc.)
`=
`
`Total bandwidth = (512B in) + (512B out) + (512B Cpu)
`
`-
`
`Dram Bandwidth required = (1536B/frame) x (156,250 frames/s) =
`
`Dram Bandwidth @ 60MHz = (32 bytes / 167ns)
`
`Dram Bandwidth @ 66MHz = (32 bytes / 150ns)
`
`PCI Bandwidth required
`
`PCI Bandwidth available @ 30 MHz, 32b, average
`
`PCI Bandwidth available @ 33 MHz, 32b, average
`
`PCI Bandwidth available @ 60 MHz, 32b, average
`
`PCI Bandwidth available @ 66 MHz, 32b, average
`
`PCI Bandwidth available @ 30 MHz, 64b, average
`
`PCI Bandwidth available @ 33 MHz, 64b, average
`
`PCI Bandwidth available @ 60 MHz, 64b, average
`
`PCI Bandwidth available @ 66 MHz, 64b, average
`
`e Cpu Bandwidth
`
`Receive frame interval = 512B / 40MB/s
`
`=
`
`=
`
`=
`
`=
`
`=
`
`=
`
`==
`
`=
`
`=
`
`-
`
`=
`
`4
`
`512B / frame
`
`1536B / frame
`
`240MB/s
`
`202MB/s
`
`224MB/s
`
`80MB/s
`
`46MB/s
`
`S0MB/s
`
`92MB/s
`
`100MB/s
`
`92MB/s
`
`100MB/s
`
`184MB/s
`
`200MB/s
`
`Instructions / frame @ GOMHz = (12.8us/frame) / (50ns/instruction)
`instructions/frame
`
`Instructions / frame @ 66MHz = (12.8us/frame) / (45ns/instruction)
`instructions/frame
`
`Required instructions / frame (per Clive)
`
`=
`
`250 instructions/frame
`
`we
`
`
`
`£GhTOT"sosTtsog
`
`Provisional Pat. App. of Alacritech, Inc.
`Inventors Laurence B. Boucher etal.
`Express Mail Label # EH756230105US
`
`75
`
`(2 Spe) Y 2
`
`
`
`OS60 Hawt
`
`ALA00138461
`
`Ex.1031.079
`DELL Ex.1031.079
`
`DELL
`
`
`
`e Performance Features
`
`- 512 registers improve performance through reduced scratch ram accesses and reduced instructions.
`
`- Register windowing eliminates context-switching overhead.
`
`- Separate instruction and data paths eliminate memory contention.
`
`- Totally resident control store eliminates stalling during instruction fetch.
`
`- Multiple logical processors eliminate context switching and improve real-time response.
`
`- Pipelined architecture increases operating frequency.
`
`- Shared register and scratch ram improve inter-processor communication.
`
`- Fly-by state-Machine assists address compare and checksum calculation.
`
`- TCP/TP-context caching reduces latency.
`
`- Hardware implemented queues reduce Cpu overhead and latency.
`
`- Horizontal microcode greatly improves instruction efficiency.
`- Automatic frame DMA and status between Mac and dram buffer.
`
`- Deterministic architecture coupled with context switching eliminates processorstalls.
`
`m=-i
`
`d
`
`fr
`te
`
`a = b
`
`e o ~
`
`~ &
`
`Provisional Pat. App. of Alacritech, Inc.
`Inventors Laurence B. Boucher et al.
`Express Mail Label # EH756230105US
`
`76
`
`2 «dh? SMostihat
`
`ALA00138462
`
`Ex.1031.080
`DELL Ex.1031.080
`
`DELL
`
`
`
`PROCESSOR
`
`The processoris a convenient means to provide a programmable state-machine which is capable of processing
`incoming frames, processing host commands, directing networktraffic and directing PCIbus traffic. Three
`processors are implemented using shared hardware in a three-level pipelined architecture which launches and
`completes a single instruction for every clock cycle. The instructions are executed in three distinct phases
`corresponding to each of the pipeline stages where each phase is responsible for a different function.
`
`The first instruction phase writes the instruction results of the last instruction to the destination operand,
`modifies the program counter (Pc), selects the address source for the instruction to fetch, then fetches the
`instruction from the control store. The fetched instruction is then stored in the instruction register at the end of
`the clock cycle.
`
`The processorinstructions reside in the on-chip control-store, which is implemented as a mixture of ROM and
`Sram. The ROM contains 1K instructions starting at address 0x0000